M66271FP [RENESAS]
Operation Panel Controller; 操作面板控制器
| 型号： | M66271FP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Operation Panel Controller |
| 文件： | 总28页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M66271FP
Operation Panel Controller
REJ03F0267-0200
Rev.2.00
Mar 18, 2008
Description
The M66271FP is a graphic display-only controller for displaying a high duty dot matrix type LCD which is used
widely for PPC, FAX and multi-function telephones.
It is capable of controlling a monochrome STN LCD system of up to 320 × 240 dots.
The IC has a built-in 9600-byte VRAM as a display data memory.
All of the VRAM addresses are externally opened. Address mapping in the MPU memory space allows direct
addressing of all display data from the MPU, thus providing efficient display data processing such as drawing.
The built-in arbiter circuit (cycle steal system) which gives priority to display access allows timing-free access from
MPU to VRAM, preventing display screen distortion.
The IC provides interface with a 8-bit/16-bit MPU with a READY (WAIT) pin.
And this IC has a function for LCD module built-in system by lessening connect pins between MPU.
Features
•
Displayable LCD
Monochrome STN dot matrix type LCD of up to 76800 dots (equivalent to 320 × 240 dots)
Maximum display duty:
1/240 (set to 240 line)
1/255 (Max)
:
•
•
Display memory
Built-in 9600-byte (76800-bit) VRAM (equivalent to one screen of 320 × 240 dots LCD)
All addresses of built-in VRAM are externally opened.
Interface with MPU
Capability of switching 8-bit type MPU/16-bit type MPU
With WAIT output pin (Accessing register from MPU without WAIT output. Accessing VRAM from MPU with
WAIT output.)
Capability of controlling BHE or LWR/HWR at the interface with a 16-bit MPU.
Interface with LCD
LCD display data are 4-bit parallel output
4 kinds of control signals: CP, LP, FLM and M
Display functions
•
•
Graphic display only (characters drawn graphically)
Binary display only (without tone display function)
Vertical scrolling is allowed within memory range (small size LCD only)
Additional function for LCD module built-in system
15 kinds of interface with MPU: A <4:1>, D <7:0>, IOCS, LWR, RD
Accessing VRAM from MPU through I/O register
Capability of interfacing with 8-bit type MPU only
5 V single power supply
•
•
•
80-pin QFP
Application
•
•
•
•
PPC/FAX operation panel, display/operation panel of other OA equipment
Multi-function/public telephones
PDA/electronic notebook/information terminal
Other applications using LCD of 76800 dots or less
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 1 of 27
M66271FP
Block Diagram 1
V
DD
8
23 34 42 52 53 77
15
:
22
MPU address
bus
Address
buffer
A <13:0>
LCD control
signal
61
66
LCDENB
CP
26
:
Control
register
Display data
transfer clock
31
LCD display
timing
control
Display data latch
pulse
67
68
62
LP
First line marker
signal
FLM
M
circuit
LCD alternating
signal
43
:
50
Data
MPU data bus
D <15:0>
buffer
53
:
VRAM
Control register
2
IOCS
MCS
chip select
69
70
71
72
LCD display
data
control
circuit
6
3
VRAM chip select
9600-byte
LCD display
data bus
UD <3:0>
High write strobe
Low write strobe
Read strobe
8/16 MPU select
Reset
HWR
4
LWR
MPU I/F
control
circuit
5
RD
12
11
14
9
MPUSEL
RESET
BHE
Bus high enable
MPU clock
MPUCLK
WAIT
7
Wait
Bus arbiter
timing
control
Clock
control
78
79
Oscillator input
Oscillator output
(Cycle steal
control)
OSC1
OSC2
(Basic timing
control)
1
10 13 24 25 35 40 41 51 64 65 80
SS
32 33 36 37 38 39 73 74 75 76
V
N.C
Block Diagram 2 (In case of LCD module built-In system)
No use pins
V
DD
3
6
7
9
11 12 14 15
8
23 34 42 52 63 77
_
_
_
31 53 60
20
22 26
16
:
MPU address
bus
Address
buffer
LCD control
signal
Display data
transfer clock
Display data latch
pulse
A <4:1>
61
LCDENB
19
Control
register
66 CP
LCD display
timing
67
LP
First line marker
signal
LCD alternating
signal
control
circuit
FLM
68
62
M
VRAM
address
index
43
:
Data
buffer
MPU data bus
D <7:0>
register
50
Data port
register
VRAM
Control register
chip select
2
IOCS
69
70
71
72
LCD display
data
control
circuit
9600-byte
LCD
display
data bus
UD <3:0>
MPU I/F
control
circuit
4
5
Low write strobe
Read strobe
LWR
RD
Bus arbiter
timing
control
Clock
control
78
79
Oscillator input
Oscillator output
OSC1
OSC2
(Basic timing
control)
1
10 13 24 25 35 40 41 51 64 65 80
SS
32 33 36 37 38 39 73 74 75 76
V
N.C
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 2 of 27
M66271FP
Pin Arrangement
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
V
SS
V
SS
Display data transfer clock
Display data latch pulse
First line marker
N.C
N.C
N.C
N.C
V
V
CP
LP
FLM
UD <0>
UD <1>
UD <2>
UD <3>
N.C
SS
LCD display data bus
DD
N.C
N.C
M66271FP
N.C
N.C
N.C
A <13>
A <12>
A <11>
A <10>
A <9>
MPU address bus
V
DD
Oscillator input
Oscillator output
OSC1
OSC2
V
A <8>
V
SS
SS
N.C: No connection
(Top view)
Outline: PRQP0080GB-A (80P6N-A)
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 3 of 27
M66271FP
Pin Description
Input/
Output
Input/
Number
of Pins
16
Item
MPU
Pin Name
D <15:0>
Function
MPU data bus
interface
Output
Connect to MPU data bus.
Selecting 8-bit MPU by MPUSEL input, D <15:8> connect to VDD or VSS
A <13:0>
Input
MPU address bus
14
Connect to MPU address bus. When selecting 8-bit MPU, use A <13:0>. And
selecting16-bit MPU, use A <13:1> for the address bus with combining A <0> and
BHE by the method of access to internal VRAM (Refer to figure 1). Use A <4:0> for
selecting address of control register.
Input
Input
Input
Chip select input of control register
When this pin is "L", select the internal control register. Assign to I/O space of MPU.
Chip select input of VRAM
When this pin is "L", select the internal VRAM. Assign to memory space of MPU.
High-write strobe input
When this pin is "L", data write to the internal VRAM. HWR is valid only in using 16-
bit MPU controlled byte access by LWR and HWR. (Refer to figure 1)
Low-write strobe input
When this pin is ''L", data write to the internal control register or VRAM. (Refer to
figure 1)
1
1
1
IOCS
MCS
HWR
Input
Input
1
1
LWR
RD
Read strobe input
When this pin is "L", data read from the internal control register or VRAM. (Refer to
figure 1)
MPUSEL
Input
Input
8/16-bit MPU select input
According to MPU, set "VSS" for 8-bit MPU and set "VDD" for 16-bit MPU
Reset input
Use reset signal of MPU. When this pin is "L", initialize all internal control register
and counter.
1
1
RESET
MPUCLK
Input
Input
MPU clock
Input of MPU clock.
Bus-high-enable input
This pin is valid when using 16-bit MPU controlled byte access by A <0> and BHE
(Refer to figure 1). Connect to "VDD" when using 8-bit MPU.
Set to ''L'' when using the additional function for the LCD module built-in system.
WAIT output for MPU
1
1
BHE
Output
1
WAIT
This signal makes WAIT for MPU.
Change WAIT ''L'' at timing of falling edge of overlapping with MCS and (RD or LWR
or HWR).
And return to "H" at synchronizing with the rising edge of MPUCLK after internal
processing.
(Output WAIT only when requested access from MPU to VRAM during cycle steal
access.)
LCD
interface
UD <3:0>
CP
Output
Output
Output
Display data bus for LCD
4
1
1
Transfer the LCD display data with 4-bit parallel signal.
Mutually output upper/lower data every CP output.
Display data transfer clock
Shift clock for the transfer of display data to LCD.
Take the display data of UD <3:0> to LCD at falling edge of CP.
Display data latch pulse
LP
This clock use both as the latch pulse of display data for LCD and the transfer of
scanning signal.
LP output when finish the transfer of display data of a line.
Latch of display data and the transfer of scanning signal at falling edge of LP.
First line marker signal
FLM
Output
1
Output the start pulse of scanning line.
This signal is "H" active, the IC for driving scanning line catch FLM at falling edge of
LP.
M
Output
Output
LCD alternating signal output
Signal for driving LCD by alternating current.
LCD (ON/OFF) control signal output
1
1
LCDENB
Output data which is set at bit "0" of mode register (R1) in control register. This
signal can use for controlling the LCD power supply, because LCDENB set to "L" by
RESET.
Oscillator OSC1
OSC2
Input
Output
—
—
—
Input pin for oscillator
Output pin for oscillator
Power supply (source + 5 V)
Ground
Generate an internal clock.
For crystal oscillator or external clock signal.
1
1
7
12
10
Others
VDD
VSS
N.C
No connection
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 4 of 27
M66271FP
Absolute Maximum Ratings
(Ta = 0 to +70°C unless otherwise noted)
Item
Supply voltage
Symbol
Ratings
–0.3 to +6.5
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
10
Unit
V
VDD
VI
Input voltage
V
Output voltage
VO
IO
V
Output current
mA
mW
°C
Power dissipation
Storage temperature
Pd
Tstg
600
–55 to +150
Recommended Operating Conditions
(Ta = 0 to +70°C unless otherwise noted)
Item
Supply voltage
Symbol
VDD
Min
4.5
—
0
Typ
5.0
0
Max
5.5
Unit
V
Supply voltage
VSS
VI
—
V
Input voltage
—
VDD
VDD
+70
V
Output voltage
VO
0
—
V
Operating temperature
Topr
0
+25
°C
Electrical Characteristics
(VDD = 5 V ± 10%, Ta = 0 to +70°C unless otherwise noted)
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
VDD = 5.5 V
High-level input voltage
All inputs except for
VIH
2.2
—
—
V
OSC1, RESET and
MPUSEL
Low-level input voltage
VIL
—
—
0.8
V
VDD = 4.5 V
High-level input voltage
Low-level input voltage
OSC1
VIH
VIL
3.5
—
—
—
—
—
V
V
V
VDD = 5.5 V
VDD = 4.5 V
VDD = 5.0 V
1.0
3.7
Positive-going threshold
voltage
MPUSEL,
VT+
2.3
RESET
Negative-going threshold
voltage
VT–
VOH
1.25
4.1
—
—
2.3
—
V
V
VDD = 5.0 V
High-level output voltage All outputs except
for OSC2 and
VDD
IOH = –4 mA
IOL = 4 mA
= 4.5 V
outputs of D <15:0>
Low-level output voltage
VOL
—
—
0.4
V
High-level output voltage OSC2
Low-level output voltage
High-level input current
VOH
VOL
IIH
4.1
—
—
—
—
—
—
—
—
—
—
0.4
10
V
V
A
A
A
VDD
IOH = –50 µA
IOL = 50 µA
= 4.5 V
VDD = 5.5 V, VI = VDD
VDD = 5.5 V, VI = VSS
VDD = 5.5 V, VO = VDD
Low-level input current
IIL
–10
10
Off-state high-level
output current
D <15:0>
IOZH
Off-state low-level
output current
IOZL
—
—
—
—
–10
40
A
VDD = 5.5 V, VO = VSS
Operating supply current
(Average)
IDD (A)
mA
VDD = 5.5 V,
VI = VDD or VSS
fosc = 10 MHz,
Output = open
Stand-by supply current
IDD (S)
—
—
500
A
VDD = 5.5 V,
IOCS, MCS = VDD
Other's VI = VDD or VSS
(valid)
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 5 of 27
M66271FP
Switching Characteristics
(VDD = 5 V ± 10%, Ta = 0 to +70°C, CL = 50 pF)
Item
Symbol
ta (IOCS-D)
Min
Typ
Max
Unit
IOCS data access time
—
—
70
ns
MCS data access time
ta (MCS-D)
RD data access time
ta (RD-D)
Output disable time after IOCS
Output disable time after MCS
Output disable time after RD
tdis (IOCS-D)
tdis (MCS-D)
tdis (RD-D)
—
—
—
—
20
40
ns
ns
WAIT output propagation time after MCS
WAIT output propagation time after WR
WAIT output propagation time after RD
WAIT output propagation time after MPUCLK
CP output propagation time after OSC
LP output propagation time after OSC
tpHL (MCS-WAIT)
tpHL (WR-WAIT)
tpHL (RD-WAIT)
tpLH (CLK-WAIT)
tpd (OSC-CP)
tpLH (OSC-LP)
tpHL (OSC-LP)
ta (UD)
—
—
—
—
—
—
20
40
40
ns
ns
ns
UD access time
—
—
—
—
40
40
ns
ns
FLM output propagation time after OSC
tpLH (OSC-FLM)
tpHL (OSC-FLM)
tpd (OSC-M)
M output propagation time after OSC
—
—
—
—
40
40
ns
ns
LCDENB output propagation time after OSC
tpLH (OSC-LE)
tpHL (OSC-LE)
tpd (D-WAIT)
Data definite time before canceling WAIT
Timing Requirements
0
—
—
ns
(VDD = 5 V ± 10%, Ta = 0 to +70°C)
(1) Accessing to Control Register
Item
Symbol
Min
Typ
Max
Unit
IOCS pulse width
tW (IOCS)
70
—
—
ns
LWR pulse width
tW (LWR)
Data set up time before falling edge of IOCS
Data set up time before falling edge of LWR
Data hold time after rising edge of IOCS
Date hold time after rising edge of LWR
tsu (D-IOCS)
tsu (D-LWR)
th (IOCS-D)
th (LWR-D)
0
—
—
—
—
—
—
ns
ns
ns
15
15
Address set up time before falling edge of IOCS tsu (A-IOCS)
Address set up time before falling edge of LWR
Address set up time before falling edge of RD
Address hold time after rising edge of IOCS
Address hold time after rising edge of LWR
Address hold time after rising edge of RD
tsu (A-LWR)
tsu (A-RD)
th (IOCS-A)
th (LWR-A)
th (RD-A)
15
—
—
ns
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 6 of 27
M66271FP
(2) Accessing to VRAM
Item
Symbol
tW (MCS)
Min
Typ
Max
Unit
MCS pulse width
70
—
—
ns
WR pulse width
tW (WR)
Data set up time before falling edge of MCS
Data set up time before falling edge of WR
Data hold time after rising edge of MCS
Data hold time after rising edge of WR
Address set up time before falling edge of MCS
Address set up time before falling edge of WR
Address set up time before falling edge of RD
Address hold time after rising edge of MCS
Address hold time after rising edge of WR
Address hold time after rising edge of RD
tsu (D-MCS)
tsu (D-WR)
th (MCS-D)
th (WR-D)
tsu (A-MCS)
tsu (A-WR)
tsu (A-RD)
th (MCS-A)
th (WR-A)
th (RD-A)
0
—
—
—
—
—
—
ns
ns
ns
15
15
15
—
—
ns
(3) Clock and Accessing to LCD Display
Item
Symbol
Min
50
Typ
Max
Unit
ns
MPUCLK cycle time
MPUCLK "H" pulse width
MPUCLK "L" pulse width
OSC cycle time
tC (CLK)
—
tC (CLK)
2
—
—
tWH (CLK)
tWL (CLK)
tC (OSC)
tWH (OSC)
tWL (OSC)
tC (CP)
—
ns
—
50*
—
—
ns
ns
tC (OSC)
2
OSC "H'' pulse width
OSC "L" pulse width
CP cycle time
—
tC (OSC)
(1/n)
—
—
—
—
ns
ns
tC (OSC)
2 • (1/n)
CP "H" pulse width
CP "L" pulse width
FLM pulse width
tWH (CP)
tWL (CP)
tW (FLM)
2 • tC (OSC) • LPW
—
—
ns
(1/n)
Note: Clock frequency of OSC1 input is less than fmax = 20 MHz.
Limit of OSC clock for the internal operation is fmax = 10 MHz.
When OSC1 is more than 10 MHz from external input, set OSC clock up to 10 MHz by using division of OSCC
register.
Division is set with rising edge of OSC1 input.
1/n = Division of OSC1
LPW = Setting value of LPW register
Test Circuit
V
DD
Item
tdis (LZ)
tdis (HZ)
ta (ZL)
SW1
Closed
Open
SW2
Open
Input
VDD
RL = 1 k
Closed
Open
SW1
SW2
Closed
Open
D <15:0>
ta (ZH)
Closed
(1) Input pulse level: 0 to 3 V
Input pulse rise/fall time: tr, tf = 3 ns
Input decision voltage: 1.5 V
Output decision voltage: VDD/2
C
L
DUT
P.G
RL = 1 k
50
Outputs
except for
D <15:0>
CL
(However, tdis (LZ) is 10% of output amplitude and tdis
(HZ) is 90% of that for decision.)
V
SS
(2) Load capacity CL include float capacity of
connection and input capacity of probe.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 7 of 27
M66271FP
Outline
M66271FP is graphic display only controller for displaying a dot matrix type LCD. This IC has a built-in display data
memory (VRAM) which is equivalent to 320 × 240 dots LCD.
•
Control register
When access the control register from MPU side, use IOCS, LWR, RD, A <4:0> and D <7:0>. Refer to table 1,
when set control type inputs.
Control registers are R1 to R8 for the normal mode function and R9 to R11 for the exclusive register for the LCD
module built-in system.
•
•
VRAM
When access VRAM from MPU side, use MCS, HWR, LWR, RD, BHE, A <13:0> and D <15:0>. And enable to
correspond to both 8-bit and 16-bit MPU by using MPUSEL input. Refer to figure 1 and table 2 to 6 for a form of
VRAM and input setting for 8/16-bit MPU.
Cycle steal system
Cycle steal is interact method of transferring display data for LCD from VRAM and accessing VRAM from MPU
on the basic cycle of OSC.
Basic timing is two clocks of OSC, and assign first clock to the access from MPU to VRAM and second clock to the
transfer of display data from VRAM to LCD.
In accessing VRAM from MPU, output WAIT. Change WAIT to "L" at the timing of the falling edge of
overlapping with MCS and (RD or LWR/HWR). And return to "H" at synchronizing with rising edge of MPUCLK
after internal processing.
Cycle steal system can transfer data with more efficient. This function access with the cycle steal method as taking
WAIT for MPU during the display term with necessity for the display data transfer from built-in VRAM to LCD.
On other side, don't output WAIT for keeping throughput of MPU during horizontal synchronous term with no
necessity for the display data transfer from VRAM to LCD side.
Refer to the following description of cycle steal.
•
Output to LCD side
LCD display data UD <3:0> output synchronized with the rising edge of CP output per 4 bits.
LP output synchronized with the falling edge of OSC when finish the transfer of display data for a line.
Enable to adjust the fittest value of the frame frequency requested by the LCD PANEL side with adjusting pulse
width by LPW register.
FLM output, when finish the transfer of display data of 1st line.
M output is the LCD alternating signal which is signal for driving LCD by alternating current.
M-cycle enable to set variably by M-cycle variable register in line unit, and enable to utilize for preventing LCD
from being inferior.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 8 of 27
M66271FP
Difference in VRAM between 8-bit and 16-bit MPU
(1) When accessing built-in VRAM by 8-bit MPU
(MPUSEL = "L", BHE = "H", HWR = "H": set)
A <13:0>
A <13:0>
CEC
MCS
VRAM
WEC
9600-byte
LWR
DI <7:0>
D <7:0>
DO <7:0>
RD
(2) When accessing built-in VRAM by 16-bit MPU
(2-1) In case MPU use A <0> and BHE for byte access
(MPUSEL = "H", HWR = "H": set)
(2-2) In case MPU use LWR and HWR for byte access
(MPUSEL = "H", BHE = "H", A <0> = "H": set)
A <13:1>
A <13:1>
A <13:1>
A <13:1>
A <0>
A <0>
VRAM
VRAM
CEC
CEC
MCS
MCS
4800-byte
4800-byte
WEC
WEC
LWR
LWR
(Lower byte)
(Lower byte)
DI <7:0>
DI <7:0>
D <7:0>
D <7:0>
DO <7:0>
DO <7:0>
A <13:1>
A <13:1>
BHE
A <0>
CEC
VRAM
VRAM
CEC
4800-byte
4800-byte
WEC
WEC
HWR
(Upper byte)
(Upper byte)
D <15:8>
DI <15:8>
D <15:8>
DI <15:8>
DO <15:8>
DO <15:8>
RD
RD
Figure 1 Difference in VRAM between 8-bit and 16-bit MPU
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 9 of 27
M66271FP
Combination of Control Input Pins for MPU Interface
Table 1 to 6 show conditions of input setting when access the control register and VRAM from MPU.
(1) Access control register (Use address = A <4:0>, Data = D <7:0>)
Table 1
IOCS
L
L
LWR
RD
H
Operation
Write to control register
Read from control register
Invalid
L
H
X
L
H
X
(2) Writing to VRAM
(2-1)When use 8-bit MPU (MPUSEL = "L", BHE = HWR = "H": set)
Table 2
MPU
SEL
Odd
Address
Even
Address
Valid Data Bus
Width of MPU
MCS
BHE A <0> HWR LWR
L
L
H
L
H
X
X
H
L
Invalid
Write
Write
Invalid
Invalid
8-bit
H
X
Invalid
H
(2-2)When use 16-bit MPU (In MPU controls byte access with A <0> and BHE, MPUSEL = HWR = "H": set)
Table 3
MPU
SEL
Upper
Byte
Lower
Byte
Valid Data Bus
Width of MPU
MCS
L
BHE A <0> HWR
LWR
L
H
L
H
X
L
H
L
H
Write
Invalid
Write
Write
Invalid
Invalid
Invalid
Write
16-bit
H
L
Upper 8-bit
Lower 8-bit
Lower 8-bit
H
Invalid
Invalid
Invalid
Invalid
Invalid
L
H
Invalid
Write
H
X
L
← Even if
A <0> = "H",
enable to write
H
Invalid
H
X
(2-3)When use 16-bit MPU
(In MPU controls byte access with LWR and HWR, MPUSEL = BHE = A <0> = "H": set)
Table 4
MPU
SEL
Upper
Byte
Lower
Byte
Valid Data Bus
Width of MPU
MCS
BHE A <0> HWR LWR
H
L
H
H
L
H
X
L
H
L
Write
Write
Write
Invalid
Write
16-bit
Upper 8-bit
Lower 8-bit
Invalid
Invalid
H
X
Invalid
H
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 10 of 27
M66271FP
(3) Reading from VRAM
(3-1)When use 8-bit MPU (MPUSEL = "L", BHE = "H": set)
Table 5
MPU
SEL
Odd
Address
Even
Address
Valid Data Bus
Width of MPU
MCS
BHE
A <0>
RD
L
L
H
L
H
X
L
Invalid
Read
Read
Invalid
Invalid
8-bit
H
X
Invalid
H
(3-2)When use 16-bit MPU (MPUSEL = ''H": set)
Table 6
MPU
SEL
Upper
Byte
Lower
Byte
Valid Data Bus
Width of MPU
MCS
L
BHE
X
A <0>
RD
L
H
X
Read
Read
16-bit
H
Invalid
Invalid
H
X
Note: Avoid setting combination except above, as cause of error action.
X = "L" or "H''
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 11 of 27
M66271FP
Description of Cycle Steal
Basic Timing
Basic timing of M66271FP is two clocks of OSC (internal clock after dividing OSC1 input).
Assign first clock to accessing from MPU to VRAM and second clock to transferring of display data from VRAM to
LCD.
Access
from MPU
to VRAM
Data transfer
from VRAM
to LCD
MPU
LCD
OSC
(Internal clock after
dividing OSC1 input)
CP output
(Display data transfer)
Basic cycle
Figure 2 Basic Timing
Operation Cycle of MPU Access (During WAIT Output)
Writing or reading operation for VRAM during cycle steal needs 1 cycle in best case or 3 cycles in worst case,
according to the condition of the internal cycle steal at staring access requested from MPU.
Ex.) Assuming that MCS input is later than RD, LWR and HWR input.
Cycle of
LCD access
Cycle of
MPU access
Cycle of
LCD access
Cycle of
MPU access
Cycle of
LCD access
Best case
MCS
WAIT
Cancel WAIT, when synchronize
with rising edge of MPUCLK
MPUCLK
Worst case
MCS
WAIT
Cancel WAIT, when synchronize
with rising edge of MPUCLK
MPUCLK
Figure 3 Operation Cycle of MPU Access
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 12 of 27
M66271FP
Function of Cycle Steal Control
M66271FP has a function for processing data of a line with more efficient. This function access with the cycle steal
method as taking WAIT for MPU during the display term with necessity for the display data transfer from built-in
VRAM to LCD.
On other side, don't output WAIT for keeping throughput of MPU during the horizontal synchronous term with no
necessity for the display data transfer from VRAM to LCD side.
But certainly set a term of accessing with the cycle steal method by CSW register, for controlling an error action near
the end of horizontal synchronous term.
Ex.) Assuming 320 × 240 dots LCD
1 Line
Output when finish transfer
of display data with a line
LP
1
1
2
3
78
79
80
Output every transfer of
a display data
CP
4-bit transfer
UD <3:0>
Setting by CR register
Displaying term (Cycle steal method)
Setting by LPW register
Horizontal synchronous term
(No necessity for data transfer from VRAM to LCD side)
(Necessity for data transfer from VRAM to LCD side)
CSE
(Internal signal)
Setting by CSW register
Start WAIT for MPU according to
cycle steal access
Access with bus timing of MPU
without WAIT for MPU.
Start WAIT for MPU in timing of CSE "H"
according to bus timing of MPU
Figure 4 Function of Cycle Steal Control
Handling of Oscillator Pin
<2> Input from external clock directly
<1> Crystal oscillator
Crystal oscillator
Clock
generator
OSC1
M66271FP
OSC2
OSC1
M66271FP
OSC2
C1
Rf
Open
Rd
C2
Note: As far as possible, connect C, R and the crystal oscillator at near the pin.
Figure 5 Oscillator Pin
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 13 of 27
M66271FP
Additional Function for LCD Module Built-in System
As all of the VRAM address in M66271FP are externally opened for addressing VRAM from MPU directly.
When consider the LCD module built-in system, connect pins are increased.
But M66271FP has an additional function for the LCD module built-in system by lessening connect pins.
Outline of the additional function for the LCD module built-in system.
•
Interface pins with MPU
15 kinds of interface with MPU: A <4:1>, D <7:0>, IOCS, LWR, RD
Method of accessing the internal VRAM
•
Access the internal VRAM through the VRAM address index register (IDXL, IDXH) and the data port register (DP)
which are used for I/O register.
The following show the process of accessing VRAM.
No use pins set the following.
Setting to MPUSEL, BHE = "L"
HWR = "H", MCS = "H", WAIT = open, MPUCLK = "L", MPUSEL = "L",
BHE = "L", A <0> = "L", A <13:5> = "L", D <15:8> = "L",
RESET = Power on reset or soft ware reset.
(In case of soft ware reset RESET = "H": set)
Select VRAM address index register (IDXL,
Enable to change IDXL and IDXH, even if either.
IDXH), and write access address (14-bit) as
data.
Access the DP after writing the mode register (DISP (R1 − D2)) = "0".
Always enable to access (CSES register = "0"), because the display
signal fix "H" or "L" in DISP = "0" and a term is no wait access.
Access DP without WAIT function.
VRAM address is automatically increased of +1, when finished
access to DP.
When access to continuous address, it doesn't need to set IDXL
and IDXH.
Select Data port register (DP).
Reading/Writing data for appointed
VRAM address.
VRAM address is increased of +1.
Application
LCD side
MPU side
Common
driver
Graphic LCD PANEL
A <4:1>
D <7:0>
IOCS
LWR
RD
M66271FP
Segment driver
Crystal
Oscillator
Note: LCD module of small size for only graphics
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 14 of 27
M66271FP
Control Register
M66271FP has 9 kinds of control register.
To set mode from MPU to control register, use IOCS, LWR, RD, A <4:0> and D <7:0>.
(1) Kind of control register
Control Register Table
Kind of Register
No. Name
Mode
Address
Data
D4 D3
Functions of Register
R/W
R/W
A4 A3 A2 A1 A0 D7
D6
D5
D2
D1
D0
R1
D6 to D0 set the basic mode.
register
0
0
0
0
0
0
CSES
RESET ←– OSCC –→ DISP
REV
LCDE
D7 is the status register of
cycle steal state.
D7 = Only "R"
R2
Horizontal
display
character
number
register
Set the number of horizontal
display characters per line.
W
0
0
1
0
←––––––––– CR ––––––––––––→
R3
Horizontal
synchronous
pulse width
register
Set the pulse width of LP per
line.
W
0
0
1
0
0
←–––––––––––––– LPW –––––––––––––––––→
R4
R5
Cycle steal
enable width
register
Set the term of cycle steal
W
0
0
0
1
1
0
1
0
0
0
←–––––––––––––– CSW ––––––––––––––––→ enable access during
horizontal synchronous term.
Set the number of display line
←––––––––––––––– SLT ––––––––––––––––––→ of vertical direction.
Vertical line
number
W
register
R6
R7
R8
Display start
address
register
Set the display start address
of VRAM.
R/W
0
0
1
1
0
1
1
0
0
0
←––––––––––––––– SAL ––––––––––––––––→
←–––––––––– SAH –––––––––––→
Set lower 8-bit to SAL and
upper 6-bit to SAH.
Max = 257FH
M cycle
variable
register
Set the cycle of LCD
W
0
1
1
0
1
0
1
0
0
0
←–––––––––––––––– MT –––––––––––––––––→ alternating signal from M.
R9
Data port
register
Data port register for
←–––––––––––––––– DP –––––––––––––––––→ accessing VRAM through the
register.
R/W
R/W
R10
VRAM
address
index
Set the address for accessing
VRAM.
1
1
0
0
0
1
1
0
0
0
←–––––––––––––––– IDXL ––––––––––––––––→
Set lower 8-bit to IDXL and
upper 6-bit to IDXH.
register
R11
Max = 257FH
←––––––––– IDXH –––––––––––→
And automatically increase in
continuous address.
Note: Data port register (DP) and VRAM address index register (IDXL, IDXH) are exclusive register, when using this IC
for the LCD module built-in system.
When RESET, each register is initialize the setting which is assumed LCD size of 320 × 240 dots.
Then, even if each register has not setting, output the signal to LCD side, it is possible to be alternation of LCD.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 15 of 27
M66271FP
(2) Description of register
(2-1)Mode register [R1]
Address
R/W
Function
Reset
00000
R/W
D7 = Only "R"
0
•
Status register for identifying active or inactive in
cycle steal function.
D7
0
CSES
No wait access
•
•
Set "1" during active with cycle steal function.
CSES is for only reading, not for writing.
1
Cycle steal access
0
•
•
Software reset.
D6
0
RESET
Reset OFF
Surely return to reset off after reset on.
1
Reset ON
000
•
•
•
Set the division of OSC clock for internal operation
from OSC1 input pin.
OSCC
When reset, OSCC = 000, OSC1 clock doesn't
divide.
Division of OSC1
D5
D4
0
D3
0
0
0
0
0
1
1
Don't set except left table.
0
1
1/2 Division
1/4 Division
1/8 Division
1/16 Division
1
0
1
1
0
0
0
•
•
•
Control the displaying ON/OFF of LCD.
When reset, DISP = 0, set display OFF.
D2
DISP
0
1
Display OFF
Display ON
REV (D1) set "1", and when DISP = "0" display data
UD <3:0> output "1" in reversal mode.
0
•
•
•
Control normal/reversal of LCD display.
When reset, REV = 0, set normal display.
D1
0
REV
Normal display
In using LCD of permeation method, REV = "1" has
effect.
1
Reversal display
0
•
•
Set the output data from LCDENB output pin.
D0
0
LCDE
When reset, LCDE = 0, LCDENB output "0" (Vss
potential).
LCDENB = "0" output
LCDENB = "1" output
•
This function is prepared for controlling the voltage
of LCD.
1
When the power supply is ON after finish each
register setting, LCDE = "1", supply voltage of LCD.
Conversely for setting power supply OFF, first LCDE
= "0", the voltage of LCD is OFF. Therefore enable
to prevent LCD from being unusual voltage as DC.
This function use for satisfy the need of LCD.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 16 of 27
M66271FP
(2-2)Horizontal display characters number register [R2]
Address R/W
00010
Function
Reset
W
28H
CR
Character Number
Display Dot Number
D7
D6
D5
0
D4
0
D3
0
D2
0
D1
D0
0
0
0
1
—
1
—
8
0
0
0
0
1
0
0
0
0
0
2
16
↓
↓
↓
1
1
1
1
1
1
63
504
•
•
The number of horizontal display characters per line can set to the extent of Max = 504 dots (= 63
characters)
When reset, CR = "28H" (= 40 characters = 320 dots)
Note: Definition of the number of display characters.
The number of display characters means data which is corresponding with 1 byte of VRAM.
In case of binary, 1 bit of VRAM corresponds to 1 dot of display, then 1 character means 8 dots of display.
(2-3)Horizontal synchronous pulse width register [R3]
Address
R/W
Function
Reset
00100
W
01H
LPW
Character Number
D7
0
D6
0
D5
0
D4
D3
0
D2
0
D1
0
D0
0
0
0
0
—
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
2
↓
↓
1
1
1
1
1
1
1
1
255
•
•
Set the length of horizontal synchronous pulse width which appeared per line in character unit.
Horizontal synchronous pulse output from LP output pin, and use for changing serial/parallel of
displaying data.
Adjusting this pulse width is possible to set frame frequency the fittest value.
And the actual LP output pulse is (LPW setting value – 1CP) in consideration of timing with CP output.
When reset, LPW = "01H" (= 1 character)
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 17 of 27
M66271FP
(2-4)Cycle steal enable width register [R4]
Address
R/W
Function
Reset
00110
W
00H
CSW
Character Number
D7
0
D6
0
D5
0
D4
D3
0
D2
0
D1
0
D0
0
0
0
0
—
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
2
↓
↓
1
1
1
1
1
1
1
1
255
•
•
During the horizontal synchronous term, set term of access by cycle steal method in character number
unit.
Setting value of CSW sets below LPW value.
When reset, CSW = "00H"
Note: Be careful with first and second byte of display data UD <3:0> output indefinite data
when setting value of CSW is still reset (00H).
Surely CSW set over 01H.
(When select 8-bit MPU, 1 byte is indefinite.
When 16-bit and SAL: D <0> = 0, 2 byte are indefinite.
When 16-bit and SAL: D <0> = 1, 1 byte is indefinite.)
(2-5)Vertical line number register [R5]
Address
01000
R/W
Function
Reset
W
F0H
SLT
D4
Vertical Line Number
D7
0
D6
0
D5
0
D3
0
D2
0
D1
0
D0
0
0
0
0
1
0
—
1
0
0
0
0
0
0
0
0
0
0
0
1
2
↓
↓
1
1
1
1
1
1
1
1
255
•
•
•
SLT combine the setting of display driving duty of LCD.
Setting of SLT is sure to adjust to the number of display line of LCD.
When reset, SLT = "F0H" (= 240 lines).
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 18 of 27
M66271FP
(2-6)
Display start address register [R6, R7]
Address R/W
Function
Reset
01010
SAL
R/W
0000H
SAH
SAL
Display Start
Address
D7
D6
D5
0
D4
D3
0
D2
0
D1
0
D0
0
D7
D6
0
D5
0
D4
D3
0
D2
0
D1
0
D0
0
0
0
0
0
0
0
0
0
0
0000H
0001H
0002H
↓
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
↓
↓
1
0
0
1
0
1
0
1
1
1
1
1
1
1
257FH
•
•
•
•
•
D6 and D7 output "0" when read SAH.
It is possible to set display start address to the extent of 257FH (= 9600 address).
Don't set over 2580H.
01100
SAH
When reset, SAL and SAH = "0000H"
Display start address is established by the writing data to SAH register. Even if only change SAL,
surely set SAH after SAL.
•
•
When select 8-bit MPU, start address set in SAL <D7 to D0> + SAH <D5 to D0>.
When select 16-bit MPU, start address set in SAL <D7 to D1>+ SAH <D5 to D0>.
Even it selecting 16-bit MPU, enable to set display start address in character unit.
In case the display reading data from VRAM start at D <15:12>, set SAL <D0> = "0", and if start at D
<7:4>, set SAL <D0> = "1". (Refer to figure 8)
(2-7)M cycle variable register [R8]
Address R/W
Function
Reset
01110
W
00H
MT
Cycle of M
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
Toggle change at every 1 frame.
Toggle change at every 1 line (1LP).
Toggle change at every 2 lines.
↓
↓
1
1
1
1
1
1
1
1
Toggle change at every 255 lines.
•
Set the cycle of M. In case of MT = 01H, M repeat reversal (toggle) at every 1 line (at every 1 count of
LP).
•
•
When reset, MT = "00H", toggle M signal at every 1 frame.
We recommend this register set suitable value for user's LCD.
(2-8)Data port register [R9]
Address R/W
Function
Reset
10000
R/W
XXH
(indefinite)
DP
Data Port (8-bit)
D7
D6
D5
D4
D3
D2
D1
D0
•
Exclusive data port register for the LCD module built-in system.
Reading or writing 8-bit data between MPU and VRAM through this register.
VRAM address index register (IDXL, IDXH) is increased of +1, when finished access to DP.
Output indefinite data when reset.
•
•
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 19 of 27
M66271FP
(2-9)VRAM address index register [R10, R11]
Address R/W
Function
Reset
10010
IDXL
R/W
0000H
IDXH
IDXL
Accessing
VRAM Address
D7
D6
D5
0
D4
D3
0
D2
0
D1
0
D0
0
D7
0
D6
0
D5
D4
D3
0
D2
0
D1
0
D0
0
0
0
0
0
0
0
0
0
0
0000H
0001H
0002H
↓
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
↓
↓
1
0
0
1
0
1
0
1
1
1
1
1
1
1
257FH
10100
IDXH
•
•
Exclusive VRAM address index register for the LCD module built-in system.
It is possible to change the register only one side, because IDXH and IDXL are independent each
other.
•
•
•
•
It is possible to set VRAM access address to the extent of 257FH (= 9600 address).
Don't set address over 2580H.
D6 and D7 output "0" when read IDXH
When reset, IDXL and IDXH = "0000H".
Description of LCD Display
Relation between Setting of Control Register and LCD Displaying
1 horizontal line
CR
CSW
Expectant
LCD PANEL
Condition of control register
(CR × 8) × SLT ≤ 76800 dots
SLT
1 horizontal line
× Vertical line number SLT
CR
LPW
Horizontal synchronous pulse width
Character number of horizontal display
OSC
3
n − 1
2
1
2
n − 2
1
n
CP
Data is indefinite
UD <3:0>
1 Character number = 8 dots display
LP
(1) Time for processing a horizontal line (TH)
2
CR, LPW, CSW: Unit of character number
SLT: Unit of line number
TH =
× (CR + LPW)
fosc: Internal OSC clock frequency
after dividing OSC1 input
fosc
(2) Time for processing a frame (TFR)
By adjusting LPW, it is possible to set a frame frequency
which is requested from LCD PANEL the fittest value.
TFR = TH × SLT
Figure 6 Relation between Setting of Control Register and LCD Displaying
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 20 of 27
M66271FP
Relation between Address of VRAM and LCD Display
ex. 1) When display start address = 0000
0000 0001
H
VRAM address mapping on the LCD PANEL
0000 0001
H
H
H
H
VRAM
9600-byte
LCD
PANEL
SLT line
257EH
257FH
257EH 257FH
CR 8 dots
ex. 2) When display start address = 1000
0000 0001
H
H
H
1000
H 1001H
LCD
PANEL
VRAM
9600-byte
1000
H
1001H
257EH
257FH
0000
H
0001H
257EH 257FH
Remark) VRAM address counter return to "0000 ",
H
after count up address to "257F ".
H
Figure 7 Relation between Address of VRAM and LCD Display
Relation between VRAM Data, LCD Display and Display Start Address Register
(1) When select 8-bit MPU
UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0
LCD display data
D7
1
D6
0
D5
1
D4
0
D3
0
D2
1
D1
0
D0
1
Data of one address for VRAM
LCD PANEL
(2) When select 16-bit MPU (SAL: D0 = "0")
UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0
LCD display data
D15 D14 D13 D12 D11 D10
D9
0
D8
1
D7
0
D6
0
D5
0
D4
0
D3
1
D2
1
D1
1
D0
1
Data of one address for VRAM
1
0
1
0
0
1
LCD PANEL
(3) When select 16-bit MPU (SAL: D0 = "1")
Invalid display data
UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0
LCD display data
D15 D14 D13 D12 D11 D10
D9
0
D8
1
D7
0
D6
0
D5
0
D4
0
D3
1
D2
1
D1
1
D0
1
Data of one address for VRAM
1
0
1
0
0
1
LCD PANEL
•
Only upper byte data of the display start address is invalid data (cut off data).
Output the display data normally from next address of the display start address.
•
Figure 8 Relation between VRAM Data, LCD Display and Display Start Address Register
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 21 of 27
M66271FP
Output Signal of LCD Side
Ex.) Assuming 320 × 240 dots LCD
(In setting of CR = 40 characters, LPW = 2 characters, SLT = 240 lines, OSCC = 1 division, MT = 1 toggle per line)
(1) Output signal per line
Division of OSC1 = 1
OSC1
80
79
80
1
1
2
2
Output every display data transfer
CP
4-bit parallel output
UD <3:0>
LP
Output when finish the transfer of
one line of display data.
(2) Output signal per frame
239
240
1
239
240
1
LP
FLM
M
Output at finishing the transfer of
first line display data.
Cycle of reversing output of M is
able to be set by MT register.
(3) LCDENB output signal
OSC1
LCDENB
(4) Reset-1st line of 1st frame
RESET
OSC1
LCDENB
LP
FLM
M
"L"
1
2
3
4
5
6
CP
1st line of 1st frame
(5) 1st line-2nd line
OSC1
LP
FLM
M
76
77
78
79
80
1
2
3
4
5
6
7
8
CP
1st line
2nd line
(6) 240th line of 1st frame-1st line of 2nd frame
OSC1
LP
FLM
M
"L"
76
77
78
79
80
1
2
3
4
5
6
7
8
CP
240th line of 1st frame
1st line of 2nd frame
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 22 of 27
M66271FP
Timing Diagram
(1) Write to Control Register (RD = "H")
Without WAIT
tw (IOCS)
tw (LWR)
IOCS
LWR
"H"
tsu (D-IOCS)
th (IOCS-D)
th (LWR-D)
WAIT
tsu (D-LWR)
Data input is established
Address is established
D <7:0>
tsu (A-IOCS)
tsu (A-LWR)
th (IOCS-A)
th (LWR-A)
A <4:0>
(2) Read from Control Register (LWR = "H")
Without WAIT
IOCS
RD
"H"
WAIT
tdis (IOCS-D)
tdis (RD-D)
ta (IOCS-D)
ta (RD-D)
Data output is established
D <7:0>
tsu (A-IOCS)
tsu (A-RD)
th (IOCS-A)
th (RD-A)
Address is established
A <4:0>
Note: 1. Writing/Reading operation for the control register is performed during overlapping IOCS and (LWR or RD).
Limits of IOCS, LWR and RD are prescribed by the input signal of last change to "L" in starting access, and
by the input signal of first change to "H" in ending access.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 23 of 27
M66271FP
(3) Write to VRAM (RD = "H")
Term of non cycle steal access
tw (MCS)
tw (WR)
MCS
LWR
(+HWR)
"H"
th (MCS-D)
th (WR-D)
tsu (D-MCS)
WAIT
tsu (D-WR)
D <7:0>
(D <15:0>)
Data input is established
Address is established
tsu (A-MCS)
th (MCS-A)
th (WR-A)
tsu (A-WR)
A <13:0>
(+BHE)
(4) Read from VRAM (LWR, HWR = "H")
Term of non cycle steal access
MCS
RD
"H"
WAIT
tdis (MCS-D)
tdis (RD-D)
ta (MCS-D)
ta (RD-D)
D <7:0>
(D <15:0>)
Data output is established
tsu (A-MCS)
tsu (A-RD)
th (MCS-A)
th (RD-A)
A <13:0>
Address is established
Note: 2. Writing/Reading operation for VRAM during non cycle steal access is performed during overlapping MCS
and [LWR (+HWR) or RD].
Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting
access, and by the input signal of first change to "H" in ending access.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 24 of 27
M66271FP
(5) Write to VRAM (RD = "H")
Term of cycle steal access
t
C (CLK)
t
WH (CLK) WL (CLK)
t
MPUCLK
tw (MCS)
tw (WR)
MCS
LWR
(+HWR)
tpLH (CLK-WAIT)
tpHL (MCS-WAIT)
WAIT
tsu (D-MCS)
tsu (D-WR)
th (MCS-D)
th (WR-D)
tpHL (WR-WAIT)
D <7:0>
(D <15:0>)
Data input is established
th (MCS-A)
th (WR-A)
tsu (A-MCS)
tsu (A-WR)
A <13:0>
(+BHE)
Address is established
(6) Read from VRAM (LWR, HWR = "H")
Term of cycle steal access
t
C (CLK)
WL (CLK)
t
WH (CLK)
t
MPUCLK
MCS
RD
tpLH (CLK-WAIT)
WAIT
tpHL (MCS-WAIT)
tpHL (RD-WAIT)
tdis (MCS-D)
tdis (RD-D)
ta (MCS-D)
ta (RD-D)
tpd (D-WAIT)
D <7:0>
Data output is established
tsu (A-MCS)
tsu (A-RD)
th (MCS-A)
(D <15:0>)
th (RD-A)
Address is established
A <13:0>
Notes: 3. Reading/writing operation for VRAM during cycle steal needs 1 tc (Internal) in best case or 3 tc (Internal) in
worst case, according to the condition of the internal cycle steal at starting access requested from MPU.
tc (Internal) = Clock cycle time after setting division of OSC1.
Data output D in reading is established before changing WAIT to "H".
4. Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting
access, and by the input signal of first change to "H" in ending access.
5. Always once return MCS, LWR (+HWR) or RD to "H" after canceling WAIT output.
In case of latching "L", as don't output next WAIT, this is cause of error action.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 25 of 27
M66271FP
(7) Interface Timing with LCD (OSCC = 1 division: set)
(When OSCC = 1 division, OSC clock for internal operation = OSC1 input.)
1. Transfer of LCD display data
t
C (OSC)
t
WH (OSC)
tWL (OSC)
OSC1
t
C (CP)
tpd (OSC-CP)
t
WH (CP)
t
WL (CP)
CP
LP
tpLH (OSC-LP)
tpHL (OSC-LP)
ta (UD)
Data is indefinite
UD <3:0>
2. LCD control signal
OSC1
CP
LP
tpHL (OSC-FLM)
tpLH (OSC-FLM)
FLM
M
tW (FLM)
tpd (OSC-M)
tpLH (OSC-LE)
tpHL (OSC-LE)
LCDENB
Note: 6. Output signal to LCD side is synchronized with OSC clock for internal operation.
When division is set to 1/2 to 1/16 by OSCC register, switching characteristics is defined by rising edge of
OSC1.
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 26 of 27
M66271FP
Package Dimensions
JEITA Package Code
P-QFP80-14x20-0.80
RENESAS Code
Previous Code
80P6N-A
MASS[Typ.]
1.6g
PRQP0080GB-A
HD
*1
D
64
41
65
40
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Dimension in Millimeters
Reference
80
Symbol
25
Min Nom Max
D
E
A2
HD
HE
A
19.8 20.0 20.2
13.8 14.0 14.2
2.8
22.5 22.8 23.1
16.5 16.8 17.1
3.05
1
24
c
ZD
Index mark
F
A1
bp
c
0.1 0.2
0.3 0.35 0.45
0.13 0.15 0.2
0
*3
bp
0°
10°
y
e
L
e
y
0.65 0.8 0.95
Detail F
0.10
ZD
ZE
L
0.8
1.0
0.4 0.6 0.8
REJ03F0267-0200 Rev.2.00 Mar 18, 2008
Page 27 of 27
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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