M66273FP [MITSUBISHI]
LCD CONTROLLER with VRAM; LCD控制器， VRAM
| 型号： | M66273FP |
| 厂家： | 
Mitsubishi Group |
| 描述： | LCD CONTROLLER with VRAM |
| 文件： | 总34页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
DESCRIPTION
· Displayable LCD
· Binary display
The M66273 is a graphic display-only controller for dot matrix type STN-
LCD which is used widely for OA equipment, PDA, amusement
equipment, etc.
Monochrome STN-LCD of up to 153600 dots(equivalent to 1/2
VGA)
· 4 gray scale display
The M66273 is an advanced product from the M66272 at the point of MPU
interface and timing specifications. This LCD display functions are the
same with the M66272.
It is capable of displaying six types of LCD by combining the panel
configuration(single or dual scan), LCD display function(binary or gray
scale), LCD display data bus width(4 or 8 bit).
Monochrome STN-LCD of up to 76800 dots(equivalent to 1/4 VGA)
Reflective color STN-LCD of up to 76800 dots (equivalent to 1/4
VGA)
· Interface with MPU
· Capability of switching the interface with two-way 8/16-bit MPU
· Provides WAIT output pin(WAIT output when access from MPU to
VRAM is gained)
Binary/
gray scale
Panel
configuration
Displayable LCD size
Equivalent to 640 x 240
LCD display data
· Capability of controlling BHE or LWR/HWR at the interface with a
4bit
8bit
4bit
8bit
4bit
4bit
Binary
16-bit MPU
· Interface with LCD
Single scan
Dual scan
Gray scale
Equivalent to 320 x 240
· LCD display data bus is a 4-bit or 8-bit parallel output.
· 4 kinds of control signals: CP, LP, FLM and M
· Display functions
Binary
Gray scale
Equivalent to 320 x 240 x 2 screens
Equivalent to 320 x 120 x 2 screens
· Graphic display only
· Binary or 4 gray scale display(gray scale palette is used to set
pseudo medium 2 gray scale.)
The M66273 can support the reflective color type LCD (ECB : Electrically
Controlled Birefringence).
· Reflective color(ECB) uses a gray scale function.
· Vertical scrolling is allowed within memory range.
· Additional function for LCD module built-in system
· Capability of interfacing with two-way 8/16-bit MPU(16-bit MPU
byte access is not allowed.)
· Access from MPU to VRAM is gained via the I/O register.
· 5V or 3V single power supply
The IC has a built-in 19200-byte VRAM as a display data memory. All of
the VRAM addresses are externally opened. Direct addressing of display
data can be performed from MPU, thus display data processing such as
drawing can be efficiently carried out.
The built-in arbiter circuit(cycle steal system) which gives priority to
display access allows timing-free access from MPU to VRAM, preventing
display screen distortion.
The IC provides has a function for LCD module built-in system by
lessening connect pins between the MPU and the IC.
APPLICATION
PPC/FAX operation panel, display/operation panel of other OA
equipment, multifunction/public telephone
· PDA/electronic notebook/information terminal, portable terminal
FEATURES
· Display memory
· Game, Amusements, Kids computer, etc.
·Built-in 19200-byte(153.6-Kbit) VRAM(Equivalent to 640 x 240 dots x 1
screen, 320 x 240 dots x 2 screens)
· All addresses of built-in VRAM are externally opened.
PIN CONFIGURATION
(TOP VIEW)
65
VSS
40
VSS
CP
DISPLAY DATA LATCH PULSE LP
FLM
66
DISPLAY DATA TRANSFER CLOCK
39
N.C
38
67
68
69
70
N.C
N.C
CSE
VSS
VDD
37
FIRST LINE MARKER SIGNAL
36
VD<0>
VD<1>
VD<2>
VD<3>
CYCLE STEAL
ENABLE
35
34
71
72
73
33
32
31
30
29
28
27
26
25
WAITCNT WAIT CONTROL
LCD DISPLAY DATA BUS
M66273FP
VD<4>
VD<5>
VD<6>
VD<7>
VDD
A<14>
A<13>
A<12>
74
75
76
MPU ADDRESS
A<11>
BUS
77
78
A<10>
A<9>
A<8>
VSS
N.C
79
80
N.C
VSS
Outline 80P6N-A
N.C : No Connection
1
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
VDD
BLOCK DIAGRAM 1
8
23 34 42 52 63 77
15
22
26
LCD CONTROL
ADDRESS
BUFFER
A<14:0>
MPU ADDRESS
BUS
61 LCDENB
SIGNAL
DISPLAY DATA
TRANSFER CLOCK
CONTROL
REGISTER
32
66
CP
LCD
DISPLAY DATA
LATCH PULSE
FIRST LINE MARKER
SIGNAL
LCD ALTERNATING
SIGNAL
DISPLAY
TIMING
CONTROL
CIRCUIT
67 LP
68 FLM
62 M
43
DATA
BUFFER
50
53
MPU DATA BUS D<15:0>
CONTROLREGISTER
60
VRAM
2
IOCS
LCD
DISPLAY
DATA
CONTROL
CIRCUIT
CHIP SELECT
69
76
19200byte
6
3
4
MCS
HWR
LWR
RD
VRAM CHIP SELECT
LCD DISPLAY
DATA BUS
VD<7:0>
HIGH WRITE STROBE
LOW WRITE STROBE
MPU I/F
CONTROL
CIRCUIT
5
READ STROBE
12
MPUSEL
RESET
BHE
8/16MPU SELECT
RESET
11
14
33
9
BUS HIGH ENABLE
WAIT CONTROL WAITCNT
BUS
MPUCLK
MPU CLOCK
ARBITER
TIMING
CONTROL
WAIT
WAIT
CSE
7
CYCLE STEAL ENABLE
36
(CYCLE
CLOCK
CONTROL
STEAL
CONTROL)
(BASIC
TIMING
CONTROL)
25
1
10 13 24
35
37 38 39 78 79
40 41 51 64 65 80
VSS
N.C
BLOCK DIAGRAM 2 (When interfacing with the LCD module built-in system and having the maximum number of pins connected with MPU)
INPUT FIXED PIN
OPEN PIN
VDD
7
36
8
23 34 42 52 63 77
3
6
11 1214 15
32 33
26
16
22
LCD CONTROL
SIGNAL
ADDRESS
BUFFER
61
66
MPU ADDRESS
BUS
A<7:1>
LCDENB
DISPLAY DATA
CONTROL
REGISTER
CP
LCD
TRANSFER CLOCK
DISPLAY DATA
LATCH PULSE
DISPLAY
TIMING
CONTROL
CIRCUIT
67LP
FIRST LINE MARKER
68FLM
62M
SIGNAL
43
LCD ALTERNATING
SIGNAL
VRAM
ADDRESS
INDEX
50
53
MPU DATA BUS D<15:0>
CONTROL REGISTER
DATA
BUFFER
R E G I S T E
60
DATA
P O R T
R E G I S T E
VRAM
2
LCD
DISPLAY
DATA
CONTROL
CIRCUIT
IOCS
CHIP SELECT
69
76
19200byte
LCD DISPLAY
DATA BUS
VD<7:0>
MPU I/F
CONTROL
CIRCUIT
4
5
LOW WRITE STROBE
READ STROBE
LWR
RD
BUS
ARBITER
TIMING
CONTROL
CLOCK
CONTROL
9
MPU CLOCK
MPUCLK
(BASIC
TIMING
CONTROL)
1
10 13 24 25 35 40 41 5164 65 80
VSS
37 38 39 78 79
N.C
2
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
PIN DESCRIPTIONS
Number
of pins
Input/
Item
Function
Pin name
D<15:0>
Output
MPU data bus
Input/
16
When selecting 8 bit MPU by MPUSEL input, connect D<15:8> to "VDD" or "VSS".
Output
MPU address bus
When selecting 8-bit MPU, use A<14:0>.
When selecting 16-bit MPU, use A<14:1> as a address bus. By combining A<0> and BHE, access to
internal VRAM can be gained.
When driving two screens (dual scan mode), notice that the allowable setup range of VRAM address
is restricted. When IOCS control use A <7:0>, and MCS control use A <14:0> for selecting address of
control register.
15
A<14:0>
Input
Chip select input of control register
Input
Input
IOCS
MCS
1
1
When this pin is "L", select the internal control register. Assign to I/O space of MPU.
Chip select input of VRAM / control register
When this pin is "L", select the internal VRAM. Assign to memory space of MPU.
And this pin can for chip select of control register.
In detail, refer to "COMBINATIONS OF CONTROL INPUT PINS ON THE MPU INTERFACE" and "CONTROL
REGISTER".
High-Write strobe input
When this pin is "L", write data to the internal VRAM. HWR is valid only in using 16-bit MPU
controlled byte access by LWR and HWR.
HWR
1
Input
Low-Write strobe input
Input
Input
Input
1
1
1
LWR
RD
When this pin is "L", write data to the internal control register or VRAM.
Read strobe input
When this pin is "L", read data from the internal control register or VRAM.
MPU
interface
8/16-bit MPU select input
MPUSEL
According to MPU, set "VSS" for 8-bit MPU and set "VDD" for 16-bit MPU.
Reset input
Use reset signal of MPU. When this pin is "L", initialize (reset) all internal control registers and
1
1
1
Input
RESET
counters.
MPU clock
MPUCLK Input
Input system clock output from MPU.
Bus-High-Enable input
This pin is valid when using 16-bit MPU controlling byte access with A<0> and BHE.
Connect to "VDD" to select 8-bit MPU.
Input
BHE
Wait control input
This pin is used for controlling WAIT output timing when requested access from MPU to VRAM.
Use this pin, when it is necessary to output WAIT earlier than the timing of falling edge of overlapping with
MCS and RD or LWR and HWR.
WAITCNT
1
Input
And then connect AS, ALE or etc of MPU.
Connect WAITCNT to "VDD" or "VSS", when it is necessary to output WAIT at the timing of falling edge of
overlapping with MCS and RD or LWR and HWR.
WAIT output for MPU
This signal makes WAIT for MPU. In case of fixed WAITCNT input("VSS" or "VDD" )change WAIT to
"L" at the timing of falling edge of overlapping with MCS and RD or LWR and HWR. And in case of
using WAITCNT input, change WAIT to "L" at timing of falling edge of WAITCNT on MCS = "L".
And WAIT output return to "H" at synchronization with the rising edge of MPUCLK after internal
processing. (Output WAIT only when requested access from MPU to VRAM is gained during cycle
steal access.)
WAIT
CSE
Output
Output
1
1
Cycle Steal Enable output
State output of internal cycle steal access.
3
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
PIN DESCRIPTIONS
Input/
Output
Number
of pins
Item
Pin name
Function
Display data bus for LCD
Transfer the LCD display data in synchronization with a rising edge of CP by putting 4-bit or 8-bit in
parallel.
VD<7:0>
Output
8
The VD<n:0> output pin in use differs depending on the number of driven screens and the display
mode.
Display data transfer clock
Shift clock for the transfer of display data to LCD.
Take the display data of VD<n:0> to LCD at falling edge of CP.
CP
LP
Output
Output
1
1
Display data latch pulse
This clock use both as the latch pulse of display data for LCD and the transfer of scanning signal.
LP is output when it finishes transferring display data of a line.
Latch of display data and the transfer of scanning signal at falling edge of LP.
LCD
interface
First Line Marker signal output
FLM
M
Output the start pulse of scanning line.
This signal is "H" active, the IC for driving scanning line catches FLM at falling edge of LP.
Output
Output
1
1
1
LCD alternating signal output
Signal for driving LCD by alternating current.
LCD (ON/OFF) control signal output
Output data which is set at bit "0" of mode register (R1) in the control register. This signal can be used
for controlling the LCD power supply, because LCDENB is set to "L" by RESET.
LCDENB
VDD
Output
Power supply pin
Ground
7
Others
VSS
N.C
7
No connection
10
DIFFERENCE BETWEEN M66273FP AND M66272FP
The M66273FP is an adv anced product f rom the M66272FP at the point of MPU interface and timing
specif ications.
LCD display functions are the same with the M66272FP.
The following shows dif f erence between the M66273FP and the M66272FP without timing specif ications.
Refer to the later item about timing specif ications and detail specifications.
Specif ication
Pin f unction
M66273FP
M66272FP
WAITCNT input ( WAIT control input)
SWAP input ( Bus swap input)
It is capable of selecting WAIT output trigger input.
In case of fixed WAITCNT input, change WAIT to "L" at the
timing of the falling edge of overlapping with MCS and RD or
LWR/HWR, and in case of using WAITCNT input, change
WAIT to "L" at the timing of the falling edge of WAITCNT on
MCS="L".
WAIT output change to "L" at the timing of the falling
edge of overlapping with MCS and RD or LWR/HWR.
WAIT output
control
Use IOCS or MCS pins for chip select of
Use IOCS pin for chip select of control register.
Access to
control register.
control register
(capable of controlling VRAM and control register by MCS
pin.)
Bus swap function Set by SWAP register.
Set by SWAP pin.
4
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
OUTLINE
·
Cycle steal system
The M66273 is a graphic display only controller for displaying a dot
matrix type STN-LCD.
· LCD display mode
It is capable of displaying six types of LCD by combining the panel
configuration, binary/gray scale, LCD display data bus width.
Cycle steal system is interact method of transforming display data for
LCD from VRAM and accessing VRAM from MPU on the basic
cycle (MAINCLK) of internal operation.
Basic timing is two clocks of MAINCLK, and assign first clock to the
access from MPU to VRAM and second clock to the transfer of
display data from VRAM to LCD.
LCD display
data
Display Panel
Binary/
gray scale
Displayable LCD
size
mode
configuration
In accessing VRAM from MPU, output WAIT. In case of fixed
WAITCNT input, change WAIT to "L" at the timing of the falling edge
of overlapping with MCS and RD or LWR / HWR,and in case of
using WAITCNT input, change WAIT to "L" at the timing of the falling
edge of WAITCNT on MCS="L", And return to "H" at synchronizing
with rising edge of MPUCLK after internal processing.
1
4bit
8bit
4bit
8bit
Equivalent to 640
x 240
Binary
2
3
4
Single
scan
Equivalent to 320
x 240
Gray scale
For the cycle steal system, this IC provides a cycle steal control
function to improve data transfer efficiency in a line. This func-tion
gains access with the cycle steal system by taking WAIT for MPU
during the display term with necessity for the display data transfer
from built-in VRAM to LCD. On the other side, it does not output
WAIT for keeping throughput of MPU during horizontal synchronous
term (idle running term) with no necessity for the display data
transfer from VRAM to LCD side.
Equivalent to 320 x
240 x 2 screens
5
6
4bit
4bit
Binary
Dual
scan
Equivalent to 320 x
120 x 2 screens
Gray scale
· Control register
When accessing the control register from MPU, use pins IOCS,
LWR, RD, A<7:0> and D<7:0>, or MCS, LWR, RD,A<14:0> and
D<7:0> (However, use D<15:0> only when 16-bit MPU controls the
LCD module built-in support function.)
In detail,refer to "Description of cycle steal".
Refer to Table-1, setting of control input.
· Output to LCD side
LCD display data VD<7:0> is output in parallel per 4 bits or 8 bits in
synchronization with the rising edge of CP.
Pin VD<n:0> differs depending on the display mode.
The IC contains the following registers as control registers.
Operation control
R1 to R11
R12 to 14 or R15 to 16
R17 to R80
Supporting LCD module built-in type
Gray scale pattern table
Single scan
Dual scan
4-bit transfer
4-bit transfer
8-bit transfer
· VRAM
VD<7:4>
VD<3:0>
This IC has a built-in 19200-byte VRAM which is equivalent to two
screens of 320 x 240 dots LCD.
VD<3:0>
VD<7:0>
When accessing VRAM from MPU, use pins MCS, HWR, LWR,
RD, BHE, A<14:0> and D<15:0>.
1
3
2
4
5
6
Display mode
When display data for a line has been sent, LP outputs data in
synchronization with the falling edge of MAINCLK.
The IC enables adjustment to an optimum value of the frame
frequency as requested from the LCD PANEL side by adjusting pulse
width of LP with the LPW register value.
Use of MPUSEL input can support both 8/16 bit MPU.
Refer to table-2 to 6, VRAM specifications for 8/16 bit MPU and input
setting in access.
The VRAM address settable range is restricted depending on the
panel configuration, as follows.
FLM is output when the display data for the first line has been sent.
M output is an LCD alternating signal for driving LCD with alternating
current.
M output cycles can be set in lines with the M output cycle variable
register and is available to prevent LCD from deterioration.
VRAM address settable range
· When single scan mode
·A<14:0>=0000 to 4AFFH --- 19200 byte
0000H
· Gray scale display function
Gray scale display can assign 2-bit VRAM data to a picture element
of LCD display to show the display density at four levels.
Gray scale display pattern tables 0 and 1 (4 x 4 matrix x 16 patterns x
2 medium gray scale), consisting of SRAM of 64 bytes in total, can
set any gray scale display pattern.
VRAM
4AFFH
· When dual scan mode
·For the 1st screen --- A<14:0>=0000 to 257FH --- 9600 byte
·For the 2nd screen --- A<14:0>=2580 to 4AFFH --- 9600 byte
In detail,refer to "Description of gray scale function".
· Application to reflective color type LCD
0000H
The above gradation display function is available to control about four
display colors on the reflective color type LCD with ECB (Electrically
Controlled Birefringence).
VRAM for the 1st screen
257FH
2580H
VRAM for the 2nd screen
4AFFH
5
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
COMBINATIONS OF CONTROL INPUT PINS ON THE MPU INTERFACE
Tables 1 to 6 show input setting conditions for access to the control register and VRAM from the MPU side.
(1) Access to the control register
For data, D<7:0> is used.
(Only when 16bit MPU is used to control the LCD module built-in system, D<15:0> is used for data.)
Table-1
IOCS MCS LWR RD
A<14:0>
Operation
L
L
H
H
H
H
H
L
L
H
L
H
L
H
L
0000H to 009EH
0000H to 009EH
5000H to 509EH
5000H to 509EH
Writes to control register
Reads from control register
Writes to control register
Reads from control register
Invalid
IOCS
control
MCS
control
L
H
H
X
X
(2) Write to VRAM
(2-1) For use of 8bit MPU (Set as follow: MPUSEL="L", BHE=HWR="H")
MPU
SEL
L
Valid data bus width
for MPU
Even address
MCS BHE A<0> HWR LWR Odd address
Table-2
L
H
L
H
L
Invalid
Write
Write
8bit
H
X
X
Invalid
H
X
Invalid
Invalid
H
(2-2) For use of 16bit MPU - 1 (For MPU controlling byte access with A<0> and BHE, set as follow: MPUSEL=HWR="H")
MPU
SEL
Valid data bus width
for MPU
Table-3
MCS BHE A<0> HWR LWR Upper byte
Lower byte
H
L
L
L
H
L
Write
Invalid
Write
Invalid
Invalid
Write
Invalid
Invalid
Invalid
Write
16bit
H
L
H
L
Upper 8bit
Lower 8bit
H
L
H
L
H
X
H
X
H
X
Invalid
Invalid
H
(2-3) For use of 16bit MPU - 2 (For MPU controlling byte access with LWR and HWR, set as follow: MPUSEL=BHE="H", A<0>="L")
MPU
SEL
Valid data bus width
for MPU
Table-4
Lower byte
A<0>
L
Upper byte
MCS BHE
HWR LWR
H
L
H
L
L
Write
Write
Write
Invalid
16bit
Upper 8bit
H
L
Invalid
Write
Lower 8bit
H
X
H
X
Invalid
Invalid
H
(3) Read from VRAM
(3-1) For use of 8bit MPU (Set as follows: MPUSEL="L", BHE="H")
MPU
Valid data bus width
for MPU
A<0>
Even address
Table-5
MCS BHE
RD
L
Odd address
SEL
L
L
H
L
Invalid
Read
Read
8bit
H
Invalid
H
X
X
Invalid
Invalid
H
(3-2) For use of 16bit MPU (Set as follow: MPUSEL="H")
MPU
Valid data bus width
for MPU
Lower byte
Read
Table-6
MCS BHE A<0>
RD
Upper byte
Read
SEL
H
L
X
X
L
16bit
H
X
Invalid
Invalid
H
Notes : Combinations except for the above cause malfunction. Be sure to make settings according to the above combinations.
: X=either "L" or "H"
6
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
CONTROL REGISTER
M66273 is equipped with 80 types of built-in control registers.
IOCS, LWR, RD, A<7:0> and D<7:0>, or MCS, LWR, RD, A<14:0>
and D<7:0> are used for setting from the MPU to control register.
And for address in IOCS control,use A<7:0>=00H to 9EH,and in MCS
control, use A<14:0>=5000H to 509EH.
(However, D<15:0> is to be used only when registers R15 and R16
only for LCD module built-in system are used.)
R1 to R11
For operation control
R12 to R14, or R15 to R17
R17 to R80
Only for LCD module built-in system
For gradation pattern table
(1) Types of control registers
· List of registers for operation control
Address
Address
Types of register
Data
(ICOS control)
(MCS control)
R/W
Reset
No.
Name
A<14:0> D7
D6
D5
D4
DIV
D3
D2
DISP REV
D1
D0
LCDE
A<7:0>
00H
RESET IDXON
5000H
5002H
5004H
5006H
5008H
500AH
R1 Basic operation mode
R2 LCD output mode
R/W
R/W
00H
00H
28H
04H
02H
78H
WAITCSWAP
CR
DUAL GRAY
4/8
02H
Number of horizontal display characters
W
W
W
W
R3
04H
LPW
Horizontal synchronous pulse width
R4
Cycle steal enable width
R5
Number of vertical lines
R6
06H
CSW
08H
SLT
0AH
D0
0
SA1L
SA1H
SA2L
500CH
500EH
5010H
R7
00H
00H
80H
0CH
0EH
10H
1st screen display start address
R/W
R8
D0
0
R9
2nd screen display start address
R/W
W
SA2H
MT
R10
5012H
5014H
25H
00H
12H
14H
M output frequency variable
R11
· List of registers only for LCD module built-in type support function
(For 8bit MPU only)
R12
R13
IDX8L
00H
5016H
5018H
501AH
16H
18H
1AH
VRAM address index
R/W
R/W
IDX8H
DP8
00H
R14 Data port
Undetermined
(For 16bit MPU only)
Address Address
Types of register
Data
(ICOS control)(ICOS control)
Reset
R/W
D0
D0
No.
Name
A<14:0> D15
A<7:0>
1CH
D14
D1
R15
VRAM address index
501CH
501EH
IDX16
DP16
0000H
R/W
R/W
0
D0
D15
1EH
R16
Data port
Undetermined
· List of registers for gray scale pattern table
Types of register
Address Address
Data
(ICOS control()ICOS control9
Reset
R/W
R/W
No.
Name
D7
D6
FRC0-1-2
D5
D4
D3
D2
D1
D0
A<7:0> A<14:0>
20H
FRC0-1-1
FRC0-1-3
to
R17 Gray scale pattern 0-1
R18 Gray scale pattern 0-2
5020H
22H
FRC0-1-4
5022H
to
to
to
to
to
Undetermined
5CH
5EH
60H
62H
FRC0-16-2
FRC0-16-4
FRC1-1-2
FRC1-1-4
FRC0-16-1
FRC0-16-3
FRC1-1-1
FRC1-1-3
to
505CH
505EH
5060H
5062H
to
R47 Gray scale pattern 0-31
Gray scale pattern 0-32
R48
R49 Gray scale pattern 1-1
R50 Gray scale pattern 1-2
to
to
to
to
R/W
Undetermined
9CH
9EH
FRC1-16-2
FRC1-16-4
FRC1-16-1
FRC1-16-3
509CH
509EH
R79 Gray scale pattern 1-31
R80 Gray scale pattern 1-32
7
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
(2) Description of registers
Address is listed for ICOS control. Incase of MCS control,set to address adding 50H to upper 7 bit (50**H).
[R1] Basic operation mode
Set the Basic operation mode
Function
·Software reset.
Restriction
Address
Reset
0
R/W
·Surely return to reset
D7
RESET
Reset OFF
Reset ON
off after reset on.
And then, can't set
0
1
another bits (D6 to
D0) at the same time.
·Set to decide whether or not the function only for LCD
module built-in system is used.
D6
IDXON
Index mode OFF
Index mode ON
0
1
0
·Set Index mode OFF for reset.
DIV
D5 D4 D3
Division of
·Set the division of MPUCLK input to set the
reference clock cycle (MAINCLK) for internal
operation.
·Don't set except for the
settings in the table at
left.
MPUCLK input
1
1/2 division
1/4 division
1/8 division
1/16 division
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
·Resetting does not divide MPUCLK.
000
00H R/W
·Control display ON/OFF of LCD.
D2
0
DISP
·In the reverse mode with REV (D1) set to "1", "1" is output to
display data VD<n:0> with DISP="0".
·Reset sets display OFF.
Display OFF
Display ON
0
0
1
·Controls normal/reverse of LCD display.
·Resetting sets normal display.
D1
0
REV
Normal display
Reverse display
1
·Sets the data output from the LCDENB output pin.
D0
0
LCDE
·Resetting outputs "0" (Vss potential) to the LCDENB output pin.
LCDENB="0"output
LCDENB="1"output
1
·This function is prepared for controlling the apply voltage to LCD.
When the power supply is turned ON after registers have been
completely set, set this LCDE to "1" to apply the LCD voltage.
Conversely for turning OFF the power supply to the system, set
the LCDE to "0" to turn OFF the LCD voltage.
This prevents abnormal DC voltage from being applied to the
LCD.
0
This function depends on the LCD functions.
Use the function, if necessary.
8
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
[R2] MPUI/LCD mode
Set the display data output mode on the LCD side.
Address
R/W
Function
Restriction
Reset
0
·To read R2, "0" is output to D7 , D6.
D7 , D6 are not used.
·Set to select trigger signal of WAIT output.
·When setting WAITC to "0", change WAIT to "L" at timing of
falling edge of overlapping with MCS and RD or LWR and
HWR. And return to "H" at synchronization with the rising
edge of MPUCLK offer internal processing.
·When setting WAITC to "T", change WAIT to "L" at timing of
falling edge of WAITCNT on MCS="L".And return to "H" at
synchronization with rising edge of MPUCLK after internal
processing.
·set when register is
initialized.
D5
0
WAITC
MCS and RD or H/LWR
control
·When setting to
"0",connect
WAITCNT control
1
WAITCNT input to
VSS or VDD.
0
·Output WAIT only when requested access from MPU to
VRAM is gained during cycle steal access.
·Resetting set WAITC ="0".
·When selecting 16 bit MPU, set SWAP to "0" to transfer
VD<n:0> in order of Upper/Lower byte of MPU data
bus,reversally set to "1" in order of Lower/Upper byte.
·When selecting 8 bit MPU, set to "0"
·set when register is
initialized.
D4
0
SWAP
02H
R/W
Order of upper/lower byte
Order of lower/upper byte
1
0
·Even if setting to "1", use D<7:0> to access to register of
8 bit width.
·Resetting set SWAP="0".
·To read R2, "0" is output to D3.
0
0
D3 is not used.
·Set the LCD panel configuration.
·set when register is
initialized.
D2
0
DUAL
·Resetting sets the 1 screen driving panel.
1 screen driving panel
2 screen driving panel
1
·Set the LCD display mode (binary or gray scale).
·Resetting sets the binary display mode.
·set when register is
initialized.
D1
0
GRAY
0
0
Binary display mode
Gray scale display mode
1
·Set the transfer path width of the LCD display data path
VD<n:0>.
·set when register is
initialized.
D0
0
4/8
4bit transfer
8bit transfer
·Resetting sets 4bit transfer.
1
9
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
[R3] Number of horizontal display characters
Address
Function
Reset
Restriction
R/W
·Sets the number of hori-zontal
display characters per line.
·Resetting sets "28H" (=40
characters).
·For CR, maximum of 255
CR
D7 to D0
00H
Number of LCD display dots
Number of
characters
characters can be set.
Binary display Gray scale display
2
·In display modes
3
4
6
,
and , the number
of even cha-racters can be
set.
01H
1
2
8
4
8
04H
W
28H
02H
16
FFH
255
2040
1020
(Note) Definition of the number of characters
The number of display characters means data corresponding to 1byte of VRAM.
One character : In the case of binary, one character means 8dots of LCD display.
In the case of gray scale display, one character means 4dots of LCD display (because 2bits of VRAM corresponds to 1dot of LCD display).
[R4] Horizontal synchronous pulse width
Restriction
Address
Function
Reset
R/W
2
·In the unit of characters, set the width of horizontal synchronous
pulse generated per line.
·In display modes
LPW
D7 to D0
00H
Number of
characters
3
4 6
and , only the
,
,
Horizontal synchronous pulse is output from the LP pin and is
used for serial/parallel conversion of displayed data.
Adjustment of LPW can set the frame frequency to an optimum
value.
number of even characters
can be set.
1
5
·In display modes and
01H
06H
W
04H
, set LPW to 02H or more.
02H
2
2
The LP output pulse actually generated takes the value(LPW
setup value - 2CP), taking into account the CP output timing.
Only in the case of display mode 4however, the LP output
pulse takes the value (LPW set value - 1CP).
·Resetting sets "04H" (= 4 characters).
·In display modes
3
4
6
,
,
and , set LPW
to 04H or more.
FFH
255
[R5] Cycle steal enable width
Restriction
Address
Function
Reset
R/W
·In unit of characters, set the period of access by the cycle steal
system near the end of the horizontal synchronous portion set
with LPW.
·Set CSW to the LPW set
CSW
D7 to D0
00H
Number of
characters
value or less.
2
·In display modes
3
4
6
·With CSW=LPW, gain access by the permanent cycle steal
system.
,
and , only the
number of even
1
2
01H
08H
W
02H
·Resetting sets "02H" (=2 characters).
characters can be set.
·In display modes 1and
02H
5
,set CSW to 01H or more.
2
·In display modes
,
3
4
6
,
and , set CSW
FFH
255
to 02H or more.
[R6] Number of vertical lines
Restriction
Address
Function
Reset
R/W
·Be sure to set SLT ac-
cording to the number of
LCD display lines.
·For SLT, a maximum of
510 even lines can be
set.
·Sets the number of lines displayed in the direction of LCD vertical
line.
SLT
D7 to D0
00H
Number of
vertical lines
·SLT also sets the LCD display driving duty.
·In dual scan mode, the actual number of displayed lines is given
by SLT x 2 screens.
2
4
01H
0AH
W
78H
·Resetting sets "78H" (=240 lines).
02H
FFH
510
10
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
[R7, R8] 1st screen display start address
Function
Address
R/W
Reset
Restriction
·At the display start add-ress,
even addresses can only
be set.
· For single scan;
0000H to 4AFEH
·Sets the 1st screen display
start address.
SA1H
SA1L
1st screen display start
address
D7 D6 to D0 D7 to D0
·The display start address is
determined by writing data
into SA1H.
0CH
00H
00H
00H
00H
00H
00H
02H
04H
0000H
0002H
0004H
(SA1L)
· For dual scan;
Sets 0000H to 257EH.
Settings except for the
above must not be made.
·To modify the display start
address, be sure to
respecify in order of SA1L-
SA1H even when only
SA1L is modified.
·Reading SA1H outputs "0" to
D7.
R/W
·Resetting sets "0000H".
0EH
(SA1H)
4AH
FEH
4AFEH
[R9, R10] 2nd screen display start address
Function
Address
R/W
Reset
80H
Restriction
·At thedisplaystart add-
ress,onlyeven addre-
sses can be set, and;
·Can set 2580Hto 4AFEH.
Settings except for the
above must not be
made.
·Used for dual scan mode
only to set the 2nd
SA2H
SA2L
2nd screen display start
address
D7 D6 to D0 D7 to D0
screen display start
address.
·The display start address is
determined by writing data
into SA2H.
10H
(SA2L)
25H
25H
25H
80H
82H
84H
2580H
2582H
2584H
R/W
·To modify the display start
address, be sure to
respecify in order of
SA2L - SA2H even when
only SA2L is modified.
·Reading SA2H outputs "0" to
D7.
12H
(SA2H)
·Resetting sets "2580H".
4AH
FEH
25H
4AFEH
[R11] M output cycle variable
Function
Restriction
Address
Reset
R/W
·Sets the output cycle of M signal
output from the M terminal.
With MT=01H,for example, M sig-
nal repeatedly reverses (toggles)
every line.
MT
D7 to D0
00H
Output cycle of M signal
Makes toggle change every frame.
Makes toggle change every line (=1LP).
Makes toggle change every 2 lines.
01H
14H
00H
W
·Resetting sets "00H".
02H
·It is recommended to set this
register to an optimum value ac-
cording to the LCD specification.
Makes toggle change every 255 lines.
FFH
11
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
[R12, R13] VRAM address index (8bit MPU only)
Address
Function
Reset
Restriction
R/W
·VRAM addresses to
access can be set to
0000H to 4AFFH.
·VRAM address index register only for LCD
module built-in system. Sets the VRAM
address to access.
IDX8H
IDX8L
D6 to D0 D7 to D0
VRAM address
16H
(IDX8L)
to access
D7
00H
00H
00H
00H
00H
01H
02H
0000H
Settings except for the
above must not be made.
·Since IDX8H and IDX8L are independent from
each other,either one of the register values
can also be set and modified.
0001H
R/W
0002H
In addition, automatic increments are made
for consecutive addresses.
18H
(IDX8H)
00H
·Reading IDX8H outputs "0" to D7.
·Resetting sets "0000H".
4AH
FFH
4AFFH
[R14] Data port (8bit MPU only)
Address
R/W
Function
Reset
Restriction
·Data port register only for LCD module built-
in type support additional functions. Via this
register, 8bit data is read/written between
MPU and VRAM.
DP8
Data port (8bit)
D7 to D0
XXH
(Undetermined)
1AH
R/W
·Completion of access to DP8 increments the
IDX8H and IDX8L values by +1.
· Resetting outputs undetermined data.
[R15] VRAM address index (16bit MPU only)
Address
Function
Reset
Restriction
R/W
·VRAM address to ac-cess
can be set to 0000H to
4AFEH.
·VRAM address index register only for LCD
module built-in type support addi-tional
functions. Sets the VRAM address to
access.
·Automatically incremented for consecu-tive
addresses.
IDX16
D14 to D0
VRAM address
to access
D15
0000H
0002H
0004H
0000H
Settings except for the
above must not be made.
·Set the VRAM address
with D<14:1> and fix it to
D<0>=0.
0002H
0000H
R/W
1CH
0004H
·Reading IDX16 outputs "0" to D15.
·Resetting sets "0000H".
4AFEH
4AFEH
Note : With SWAP="1" set, set the byte-swapped data for the VRAM address to access.
(Set low order bytes of VRAM address to D<15:8> and set high order bytes of VRAM address to D<7:0>.)
[R16] Data port (16bit MPU only)
Restriction
Address
Function
Reset
R/W
R/W
·Data port register only for LCD module built-
in type support additional functions. Via this
register, 16bit data is read/ written between
MPU and VRAM.
DP16
Data port (16bit)
D15 to D0
XXXXH
(Undetermined)
1EH
·Completion of access to DP16 incre-ments
the IDX16 value by +1.
·Resetting outputs undetermined data.
Note : Registers R12 to R16 are used only for LCD module built-in system.
Register setting is not needed if these functions are not used.
12
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
[R17 to R80] Gradation patterns 0-1 to 32 and 1-1 to 32
Address
Function
Reset
Restriction
R/W
·Set gradation patterns
when the register is
initialized.
·Sets data of gradation
pattern 0.
Register
Name
Address
A<7:0>
Data
D7 to D4
D3 to D0
No.
Gradation pattern 0
provides 16 patterns of
4 x 4 matrix.
Gray scale pattern 0-1
Gray scale pattern 0-2
FRC0-1-2 FRC0-1-1
FRC0-1-4 FRC0-1-3
·When access to R17 to
R80, must be set
R17
R18
20H
22H
20H
to
XXH
(Undeter-
mined)
R/W
DISP=OFF.
5EH
Can't access to R17
to R80 on DISP=ON.
·All registers R17 to R80
must be set.
to
to
to
to
to
FRC0-16-2 FRC0-16-1
FRC0-16-4 FRC0-16-3
Gray scale pattern 0-31
Gray scale pattern 0-32
R47
R48
5CH
5EH
·Sets data of gradation
pattern 1.
Register
Name
Address
Data
D7 to D4
D3 to D0
No.
A<7:0>
60H
Gradation pattern 1
provides 16 patterns of
4 x 4 matrix.
FRC1-1-2 FRC1-1-1
FRC1-1-4 FRC1-1-3
Gray scale pattern 1-1
R49
60H
to
XXH
(Undeter-
mined)
R50 Gray scale pattern 1-2
62H
R/W
9EH
to
to
to
to
to
FRC1-16-2 FRC1-16-1
FRC1-16-3
9EH FRC1-16-4
Gray scale pattern 1-31
R79
9CH
R80 Gray scale pattern 1-32
Gray scale pattern 0-1
FRC0-1-1
Gray scale pattern table 0 or 1
Register running Nos. 1 to 32
Gray scale pattern table 0 or 1
Number of patterns : 1 to 16
Number of lines : 1 to 4
Gray scale pattern setting example
Gray scale pattern 0-1 = 48H
Gray scale pattern 0-2 = 12H
1st frame
1st line
FRC0-1-1
FRC0-1-2
2nd line
3rd line
4th line
FRC0-1-3
FRC0-1-4
Note : Registers R17 to R80 are used to set gray scalepatterns for gray scale display.
Register setting is not needed for binary display.
13
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Description of LCD display
Relationships between control register setting and LCD display
1 horizontal line
CR
LPW
CSW
SA2H,L
SA1H,L
2nd screen
Control register setting conditions
1st
screen
·1st screen drive
Binary --- (CR x 8) x SLT
Gray scale ---
·2nd screen drive
<=153600 dots
<= 76800 dots
LCD screen to
be display ed
SLT
Binary --- (CR x 8) x (SLT x 2)
Gray scale ---
<=153600 dots
<= 76800 dots
1 horizontal line
x Number of vertical lines SLT
Number of horizontal display
characters CR
Horizontal synchronous
pulse width LPW
MAINCLK
m-2 m-1
m
1
2
1
2
3
CP
Data not determined
VD<n:0>
LP
(1) Time required for processing 1 horizontal line (TH)
2
CR,LPW,CSW : Unit of characters
SLT : Unit of even lines
1
5
x (CR+LPW)
·Display modes and
TH =
fMAINCLK
fMAINCLK : Frequency of MAINCLK for
internal operation
1
2
3
4
6
·Display mode
,
,
and
x (CR+LPW)
TH =
fMAINCLK
Adjustment of LPW can set the number of
frame frequencies requested on the LCD panel
side to an optimum value.
(2) Time required for processing 1 frame (TFR)
TFR = TH x SLT
Relationships between control register setting and LCD display
14
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Relationships between display start address and LCD display
Example) When 8bit MPU is used :
With display start address = 1000H
0000H 0001
1000H 1001H
LCD screen
VRAM
1000H 1001H
~
~
~
~
4AFEH 4AFFH 0000H 0001H
~
~
~
~
4AFEH 4AFFH
·The data of display start address (SA1H, L, SA2H,
L) is displayed upper left in the LCD.
·The display start address is loaded from register
in frames.
Relationships between display start address and LCD display
Relationships between VRAM address, data and LCD display
VRAM address, data
0000H
For 16bit MPU A<14:0>
E41BH
D<15:0>
0000H
0001H
For 8bit MPU
A<14:0>
D<7:0>
E4H
1BH
D4
16bit MPU (when
D13 D12 D11 D10 D9 D8 D7 D6 D5
D15 D14
D7 D6
D3 D2 D1 D0
setting SWAP = "0")
D5 D4 D3 D2 D1 D0 D7 D6 D5 D4
D3
1
D2 D1 D0
8bit MPU
1
a
1
1
c
0
d
0
e
1
f
0
g
0
h
0
i
0
j
0
k
1
l
0
n
1
o
1
p
b
m
2580H
A<14:0>
FA50H
D<15:0>
A<14:0>
2580H
FAH
2581H
50H
D<7:0>
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6
1
1
1
1
1
0
F
1
0
0
1
J
0
1
L
0
0
0
0
A
B
C
D
E
G
H
I
K
M
N
O
P
LCD display
1
2
3
4
Display mode
Display mode
VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0
VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0
Display mode
Display mode
VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0
VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0
1
a
1
b
1
c
0
d
0
e
1
f
0
g
0
h
a
b
c
e
f
g
h
i
j
k
l
m
n
o
p
d
LCD screen
LCD screen
Display mode
5
VD7 VD6 VD5 VD4 VD7 VD6 VD5 VD4
Display mode
6
VD7 VD6 VD5 VD4 VD7 VD6 VD5 VD4
1
a
1
b
1
c
0
d
0
e
1
f
0
g
0
h
a
b
c
e
f
g
h
i
j
k
l
m
n
o
p
d
1st screen of LCD
VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0
1st screen of LCD
VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0
1
1
1
1
1
0
F
1
0
A
B
C
D
E
G
H
A
B
C
D
E
F
G
H
I
K
L
M
N
O
P
J
2nd screen of LCD
2nd screen of LCD
: Gray scale display image
15
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Relationships between SWAP setting and LCD display
When 16bit MPU is in use, setting the SWAP register can modify the sending order of LCD display data in bytes.
SWAP setting
For D<15:0>, sends VD<n:0> in order of upper / lower bytes.
For D<15:0>, sends VD<n:0> in order of lower / upper order bytes.
0
1
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VRAM data
1
1
1
0
0
1
0
0
0
0
0
1
1
0
1
1
High order byte = E4H
Low order byte = 1BH
·Setting SWAP = "1"
D7 to
·Setting SWAP = "0"
D15 to
1 1 1 0 0 1 0 0 0 0 0 1 1 0 1 1
E4H 1BH
D8D7
to
D0
D0D15
to
D8
0 0 0 1 1 0 1 1 1 1 1 0 0 1 0 0
1BH E4H
LCD screen
LCD screen
Relationships between LCD display mode and VD<n:0> pin
1
3
5
6
,
Dual scan mode 4bit parallel Display mode
VD7 VD6 VD5 VD4
Single scan mode 4bit parallel Display mode
VD3 VD2 VD1 VD0
,
LCD screen
1st screen of LCD
VD3 VD2 VD1 VD0
Single scan mode 8bit parallel Display mode 2 ,
VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0
4
2nd screen of LCD
LCD screen
16
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Output signal on the LCD side
1
Example) Assuming 320 x 240 dots LCD is used in display mode
(CR = 40 characters, LPW = 2 characters, SLT = 240 lines, DIV = division value 1, MT = 1)
(1) Output per line
MAINCLK
80
1
2
79
80
1
2
Output each time one
piece of display data
is transferred.
CP
4bit transfer
VD<3:0>
LP
Output when display
data for a line is
comp-letely sent.
(2) Output signal per screen
239 240
239
240
1
1
LP
Output when display
data in the 1st line is
completely sent.
FLM
Output reverse period
of M signal can be set
with the MT register.
M
(3) LCDENB output signal
MAINCLK
LCDENB
(4) Reset to 1st screen/1st line
RESET
MAINCLK
LCDENB
LP
FLM
M
"L"
1
2
3
4
5
6
CP
1st screen/1st line
(5) 1st line to 2nd line
MAINCLK
LP
FLM
M
76
77
78
79
80
1
2
3
4
5
6
7
8
CP
1st line
2nd line
(6) 1st screen/240th line to 2nd screen/1st line
MAINCLK
LP
FLM
M
"L"
76
77
78
79
80
1
2
3
4
5
6
7
8
CP
2nd screen/1st line
1st screen/240th line
17
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Description of cycle Steal
Basic timing
The basic timing for internal operation of the M66273 adopts 2 clocks of
MAINCLK as a basic cycle to assign the 1st clock and 2nd clock to access
from MPU to VRAM and transfer of display data from VRAM to the LCD
side, respectively.
Access
to VRAM transfer from
from MPU VRAM to LCD
Display data
MPU
LCD
MAINCLK
MAINCLK is reference clock for internal operation inputting division of
MPUCLK and reference with rising edge of MPUCLK.
Basic
cycle
Basic timing
MPU access execution cycle (WAIT output period)
Writing/reading to/from VRAM in the display section takes,
Best case = 0.5tc(MAINCLK) + 1tc(CLK),
In this case, tc(CLK) = MPUCLK cycle time,
tc(MAINCLK) = MAINCLK cycle time.
Worst case = 2.5tc(MAINCLK) + 1tc(CLK),
depending on the internal cycle steal status when access request from
MPU starts.
LCD access cycle
MPU access cycle
LCD access cycle
MPU access cycle
LCD access cycle
MAINCLK
Ex.1 ) Assuming set to WAITCNT = "0" and MCS input is faster than RD or LWR/HWR input.(1/4 division)
Best case (When access start in LCD access cycle.)
MCS
MPU access
execution cycle
LWR
0.5tc (MAINCLK
1tc (CLK)
WAIT
Release of WAIT in synchro-
nization with rising edge of
MPUCLK.
Start of WAIT in synchro-
nization with falling edge of
LWR.
MPUCLK
Worst case (When access start in MPU access cycle.)
MCS
MPU access
execution cycle
LWR
1tc (CLK)
1.5tc (MAINCLK)
WAIT
Release of WAIT in synchro-
nization with rising edge of
MPUCLK.
Start of WAIT in synchro-
nization with falling edge of
LWR.
MPUCLK
Ex.2 ) Assuming set to WAITC = "1".(1/4 division)
Best case (When access start in LCD access cycle.)
MCS
WAITCNT
MPU access
LWR
execution cycle
1tc (CLK)
0.5tc (MAINCLK
WAIT
Release of WAIT in synchro-
nization with rising edge of
MPUCLK.
Start of WAIT in synchro-
nization with falling edge of
WAITCNT.
MPUCLK
Worst case (When access start in MPU access cycle.)
MCS
WAITCNT
LWR
MPU access
execution cycle
1.5tc (MAINCLK)
1tc (CLK)
Release of WAIT in synchro-
nization with rising edge of
MPUCLK.
Start of WAIT in synchro-
nization with falling edge of
WAITCNT.
WAIT
MPUCLK
MPU access execution cycle
18
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Description of cycle steal control function
The M66273 provides the cycle steal control function to efficiently carry
out one-line data processing.
require to be transferred from VRAM to the LCD side, this function does
not output WAIT in the section to avoid reducing the MPU throughput.
However, since malfunction is restrained near the termination of
horizontal synchronous section, the CSW register should be surely set
to provide a period of access by the cycle steal system.
In the display section where display data requires to be transferred from
built-in VRAM to the LCD side, this function adopts a cycle steal system
to gain access to the MPU while putting the MPU in WAIT.
In a horizontal synchronous section where display data does not
(It need to set at least 1 cycle of MPU bus timing.)
1
Example) Assuming 320 x 240 dot LCD in display mode
1 horizontal line
Output when 1-line
display data is
LP
comp-letely sent.
1
2
3
78
79
80
1
Output each time
one piece of display
CP
data is transferred.
4bit transfer
VD<3:0>
Set with the CR register
Section where data requires to be
transferred from display section = VRAM to
Set with the LPW register
Section where data does not require to be
transferred from horizontal section =
VRAM to the LCD side
the LCD side (cycle steal system)
CSE
Set with the CSW register
Putting MPU in WAIT according
to cycle steal access.
Gains access at the
MPU bus timing without
putting MPU in WAIT.
Provides a timing for
setting CSE to ÒHÓ
to put MPU in WAIT.
Without putting
MPU in WAIT
WAIT
19
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Set the same pattern for each 4 or 8 frames period in 16 frames.
So enable to decrease frame numbers of gray scale period.
Description of gray scale function
Set gray scale mode by register (GRAY="1").
Gray scale assign 2bits of VRAM to 1dot of LCD and displaying
4density.
Still more, set the same gray scale pattern table in frame unit, so enable
to display thinned-out frame method.
When thinned-out 1frame from continuous 4frames, the following are
example of setting pattern table.
ex.) for 8bit-MPU
1 Address
VRAM data D7 D6 D5 D4 D3 D2 D1 D0
1st frame
2nd frame
3rd frame
4th frame
Pack
C1 C0 C1 C0 C1 C0 C1 C0
Contents of display
C1 C0
Display OFF
0
0
1
1
0
1
0
1
Followed gray scale pattern table 0
Followed gray scale pattern table 1
Display ON
4 Frames
Thinned-out
frame
n Address
n+1 Address
D7
1
D0 D7
D0
0
t
1
0 0 1
0
VRAM data
1
0
1
1
1
1
0
0
0
Turn on frame
2
1
0
3
0
1
2
3
Gray scale
When use thinned-out frame, distribute thinned-out equally, and avoid
thinned-out continuous frame together.
Image of LCD
Upper figure are image of gray scale display of LCD and VRAM data,
actually controlling pseudo medium gray scale.
Gray scale function use the features of liquid crystal changed
brightness by practical voltage.
Setting of gray scale pattern table
The following are gray scale patterns for each frame, and the relation
between brightness and practical voltage.
Gray scale pattern table 0, 1 a used for controlling display density. It set
to control register R17-R80 (SRAM configuration).
Gray scale pattern set 16 patterns for 1 medium gray scale (1 pattern =
4dots x 4lines matrix).
It need to set 32 patterns (64 byte) because 2 medium gray scale.
Medium gray scale period is a maximum of 16 frames.
White
~
(0,0)
Example of gray scale pattern
The following are example of gray scale pattern. (Select 4dots from
1matrix, and each dot set equally in 1 period.)
V0
Light gray
~
1st frame
5th frame
9th frame
13th frame
2nd frame
6th frame
10th frame
14th frame
3rd frame
7th frame
11th frame
15th frame
4th frame
8th frame
12th frame
16th frame
(0,1)
1st line
2nd line
3rd line
4th line
V1
Gray
~
(1,0)
V2
Black
~
(1,1)
V3
Practical voltage
Brightness
White
Light gray
Gray
When VRAM data are following, VD output 1 for only
dot.
Pack C1 C0 C1 C0 C1 C0 C1 C0
VRAM data
0
1
0
1
0
1
0
1
Gray scale pattern of
1st line in 1st frame
Black
Displaying data VD
1
0
0
0
0
1
0
0
Gray scale pattern of
1st line in 2nd frame
V0
V1
V2
V3 Practical voltage
Displaying data VD
20
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
Additional function for LCD module built-in system
(When use this function,recommend using ICOS to control I/O registers.)
As all of the VRAM address in the M66273 are externally opened
for addressing VRAM from MPU directly.
·
Interface pins with MPU and I/O register for access to VRAM.
When consider the LCD module built-in system, connect pins are
increased.
8bit MPU
16bit MPU
A<7:1>
D<7:0>
IOCS
LWR
RD
A<7:1>
D<15:0>
IOCS
LWR
RD
But the M66273 has an additional function for the LCD module built-in
system by lessening connect pins.
Access the internal VRAM through the VRAM address index register in
this function.
Interface pins
I/O register
MPUCLK
(19 pins)
MPUCLK
(27 pins)
When use this function, need to set to IDXON = "0".
When use this function and access to VRAM, it need to set to DISP = "0".
IDX8H, IDX8L
DP8
IDX16
DP16
·
Method of accessing the internal VRAM
The following show the process of accessing VRAM.
·
No use pins set the following.
·HWR, MCS = "H",
Set fixed pins
·BHE, A<0>, A<14:8> = "L" , D<15:8> = "L" (only for 8bit MPU),
·MPUSEL, WAITCNT = "L" or "H",
·WAIT, CSE = open,
RESET = Power on reset or software reset.
(In case of software reset RESET = "H" : set)
·
·
Set control register
Access the DP after writing the mode register DISP = "0".
Always enable to access, because the display signal fixed "H" or "L"
in DISP = "0" and a term is no wait access.
set to DISP = "0"
Discontinuous address
Access to
·
Select IDX8L, IDX8H (or IDX16), and write address (15bit) of VRAM as data.
Enable to change IDXL and IDXH, even if either.
VRAM address
index register
Continuous address
Access to Data Port
register
· Select DP8 (or DP16), and read or write data to address of VRAM.
Access DP and IDX without WAIT function.
VRAM address is
increased of +1.
VRAM address is automatically increased of +1, when finished access to DP.
It doesn't need to set IDX, when access to continuous address.
After setting data of VRAM
Set to DISP = "1"
Set to DISP = "1", and displaying LCD.
·
·
Example of access to VRAM (In case of 8bit MPU)
Increase to
Addr=0001
Increase to
Addr=1001
Increase to
Addr=1002
IOCS
LWR
R1
R1
R12
16H
R13
18H
R14
R12
R13
18H
R14
1AH
R14
R14
1AH
R14
1AH
R1
00H
00H
1AH
16H
1AH
00H
44H
A<7:0>
D<7:0>
80H
40H
00H
00H
AAH
00H
10H
BBH
CCH
DDH
Write
EEH
Write
Data=CC Data=DD
to to
Write
Data=EE
to
Software IDXON=1
reset
(initialize)
IDXON=1
DISP=1
Write Data=AA
to Addr=0000
Write Data=BB
to Addr=1000
DISP=0
Addr=1001 Addr=1002 Addr=1003
Discontinuous address
Continuous address
21
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
ABSOLUTE MAXIMUM RATINGS (Ta=-20 to +75 unless otherwise noted)
C
Symbol
VDD
Parameter
Condition
Ratings
Unit
V
V
Supply voltage
Input voltage
-0.3 to +6.5
-0.3 to VDD+0.3
VI
Output voltage
Output current
V
-0.3 to VDD+0.3
VO
IO
mA
±20
Power dissipation
Storage temperature
mW
Pd
600
Tstg
-55 to +150
C
RECOMMENDED OPERATING CONDITIONS (Ta=-20 to +75
unless otherwise noted)
C
Limits
Min. Typ. Max.
Parameter
Condition
Symbol
Unit
4.5
2.7
5.0
3.0
5.5
3.3
5.0V support
3.0V support
VDD
VSS
Supply voltage
V
V
Supply voltage
0
Input voltage
V
V
0
0
VDD
VDD
VI
VO
Output voltage
Operating temperature
Topr
-20 +25 +75
C
ns
Normal input
500
5
tr, tf
Input rise, down time
Schmidt trigger input
ms
ELECTRICAL CHARACTERISTICS (5V version support specifications, Ta=-20 to +75 unless otherwise noted)
C
Limits
Symbol
Parameter
"H" input voltage
Condition
Unit
V
Min. Typ. Max.
3.85
0
VDD = 5.5V
5.5
1.35
3.7
2.3
VIH
VIL
Note 1
Note 2
VDD = 4.5V
VDD = 5.0V
"L" input voltage
Threshold voltage in positive direction
Threshold voltage in negative direction
"H" output voltage
2.3
1.25
4.1
VT+
VT-
V
VOH
VOL
IIH
IOH = -4mA
IOL = 4mA
VDD = 4.5V
VDD = 5.5V
VDD = 5.5V
V
"L" output voltage
0.4
10
"H" input current
VI = VDD
VI = VSS
uA
uA
"L" input current
-10
10
IIL
"H" output current in off status
"L" output current in off status
IOZH
IOZL
VO = VDD
VO = VSS
D<15:0>
-10
VDD = 5.5V, VI = VDD or VSS
fMAINCLK = 15MHz(MAX),
Output =open
Display mode 1,2,3,4
Display mode 5,6
60
80
Average supply current in operation
mode
IDD(A)
IDD(S)
mA
uA
VDD = 5.5V, IOCS, MCS = VDD
Other VI = VDD or VSS fixed
Supply current in static mode
200
Notes 1: Normal input terminal
--- A<14:0>, D<15:0>
2: Schmidt trigger input terminal --- All input pins except for A<14:0>, D<15:0>
22
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
ELECTRICAL CHARACTERISTICS (3V version support specification, Ta=-20~+75C unless otherwise noted)
Limits
Min. Typ. Max.
Condition
Parameter
Symbol
Unit
"H" input voltage
"L" input voltage
2.31
0
3.3
0.81
2.18
1.5
VIH
VIL
VDD = 3.3V
VDD = 2.7V
Note 1
Note 2
V
Threshold voltage in positive direction
Threshold voltage in negative direction
"H" output voltage
1.27
0.45
2.3
VT+
VT-
VOH
VOL
IIH
VDD = 3.0V
VDD = 2.7V
VDD = 3.3V
VDD = 3.3V
V
V
IOH = -4mA
IOL = 4mA
"L" output voltage
0.4
10
"H" input current
VI = VDD
VI = VSS
uA
uA
"L" input current
-10
10
IIL
"H" output current in off status
"L" output current in off status
IOZH
IOZL
VO = VDD
VO = VSS
D<15:0>
-10
VDD = 3.3V, VI = VDD or VSS
fMAINCLK = 10MHz(MAX),
Output = open
Display mode 1 to 4
Display mode 5 and 6
25
35
Average supply current in operation
mode
IDD(A)
mA
uA
VDD = 3.3V, IOCS, MCS = VDD
Other VI = VDD or VSS fixed
IDD(S)
Supply current in static mode
200
Notes 1: Normal input terminal
--- A<14:0>, D<15:0>
2: Schmidt trigger input terminal --- All input pins except for A<14:0>, D<15:0>
STANDARD CHARACTERISTICS (Ta=25
)
C
SUPPLY CURRENT VS OPERATING FREQUENCY
(DISPLAY MODE 3)
SUPPLY CURRENT VS OPERATING FREQUENCY
(DISPLAY MODE 1)
50
50
VDD=5.5V
VDD=3.3V
VDD=5.5V
VDD=3.3V
40
30
40
30
20
10
20
10
0
0
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
16
OPERATING FREQUENCY f (MHz)
OPERATING FREQUENCY f (MHz)
SUPPLY CURRENT VS OPERATING FREQUENCY
(DISPLAY MODE 6)
50
VDD=5.5V
VDD=3.3V
40
30
20
10
0
2
4
6
8
10
12
14
16
OPERATING FREQUENCY
f
(MHz)
23
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
5V version support spcification
SWITCHING CHARACTERISTICS (VDD=5V±10%, Ta=-20~+75
)
C
Limits
Ty p.
Test
condition
Symbol
Parameter
IOCS data access time
MCS data access time
RD data access time
Unit
ns
Max.
70
Min.
ta(IOCS-D)
ta(MCS-D)
ta(RD-D)
Output disable time after IOCS
Output disable time after MCS
Output disable time after RD
tdis(IOCS-D)
tdis(MCS-D)
tdis(RD-D)
20
15
ns
ns
tpHL(MCS-WAIT) WAIT output propagation time after MCS
WAIT output propagation time after WR
tpHL(WR-WAIT)
tpHL(RD-WAIT)
tpHL(WC-WAIT)
WAIT output propagation time after RD
WAIT output propagation time after WAITCNT
WAIT output propagation time after MPUCLK
tpLH(CLK-WAIT)
tpd(CLK-CP)
15
30
30
ns
ns
ns
CP output propagation time after MPUCLK
LP output propagation time after MPUCLK
CL=50pF
tpLH(CLK-LP)
tpHL(CLK-LP)
ta(VD)
30
VD access time
ns
tpLH(CLK-FLM)
tpHL(CLK-FLM)
FLM output propagation time after MPUCLK
30
30
ns
ns
ns
ns
ns
tpd(CLK-M)
M output propagation time after MPUCLK
tpLH(CLK-LE)
tpHL(CLK-LE)
LCDENB output propagation time after MPUCLK
30
30
tpLH(CLK-CSE)
tpHL(CLK-CSE)
CSE output propagation time after MPUCLK
Data definite time before cancelling WAIT
tpd(D-WAIT)
0
TIMING REQUIREMENTS (VDD=5V±10%, Ta=-20~+75C)
(1) Accessing to control register
Limits
Ty p.
Test
condition
Symbol
Parameter
Unit
ns
Min.
35
Max.
tW(CS)
tW(LWR)
IOCS/MCSpulse width
LWR pulse width
Data set up time before rising edge of IOCS/MCS
Data set up time before rising edge of LWR
tsu(D-CS)
ns
20
2
tsu(D-LWR)
th(CS-D)
th(LWR-D)
Data hold time after rising edge of IOCS/MCS
Data hold time after rising edge of LWR
ns
ns
tsu(A-CS)
tsu(A-LWR)
tsu(A-RD)
Address set up time before falling edge of IOCS/MCS
Address set up time before falling edge of LWR
Address set up time before falling edge of RD
10
0
th(CS-A)
th(LWR-A)
th(RD-A)
Address hold time after rising edge of IOCS/MCS
Address hold time after rising edge of LWR
Address hold time after rising edge of RD
ns
(2) Accessing to VRAM
Symbol
Limits
Ty p.
Test
condition
Parameter
Unit
Min.
35
Max.
tW(MCS)
tW(WR)
MCS pulse width
WR pulse width
ns
ns
ns
Data set up time before rising edge of MCS
Data set up time before rising edge of WR
tsu(D-MCS)
tsu(D-WR)
20
2
th(MCS-D)
th(WR-D)
Data hold time after rising edge of MCS
Data hold time after rising edge of WR
tsu(A-MCS)
tsu(A-WR)
tsu(A-RD)
Address set up time before falling edge of MCS
Address set up time before falling edge of WR
Address set up time before falling edge of RD
10
0
ns
ns
Address hold time after rising edge of MCS
Address hold time after rising edge of WR
Address hold time after rising edge of RD
th(MCS-A)
th(WR-A)
th(RD-A)
tsu(D-CLKD)
tsu(MCS-WC)
tsu(CLK)+10
ns
ns
Data set up time before rising edge of WAIT
5
MCS set up time before falling edge of WAITCNT
* tc(CLK)=MPUCLK cycle time
24
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
(3) Clock and accessing to LCD display
Limits
Test
condition
Symbol
Parameter
MPUCLK cycle time
Unit
ns
Min.
50
Ty p.
Max.
tc(CLK)
MPUCLK "H" pulse width
MPUCLK "L" pulse width
tWH(CLK)
tWL(CLK)
tC(CLK)
ns
2
tC(CLK)
(1/n)
Display mode 1,2,3,5,6
Display mode 4
ns
ns
CP syscle time
tC(CP)
2 · tC(CLK)
(1/n)
CP "H" pulse width
CP "L" pulse width
tWH(CP)
tWL(CP)
tC(CLK)
2 · (1/n)
Display mode 1,2,3,5,6
Display mode 4
ns
ns
CP "H" pulse width
CP "L" pulse width
tWH(CP)
tWL(CP)
tC(CLK)
(1/n)
tC(CLK) · LPW
Display mode 1,2,3,5,6
Display mode 4
ns
ns
(1/n)
FLM pluse width
tW(FLM)
2 · tC(CLK) · LPW
(1/n)
1/n =Division of MPUCLK
LPW =Setting value of LPW register
Note : Clock frequency of MPUCLK input is less than fmax = 20MHz.
Limit of clock for the internal operation is fmax = 15MHz.
When MPUCLK is more than 15MHz from extemal input,set clock for the internal operation
up to 15MHz by using division of DIV register.
Division is set with rising dege of MPUCLK input.
25
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
3V version support spcification
SWITCHING CHARACTERISTICS (VDD=3V±10%, Ta=-20~+75C)
Limits
Ty p.
Test
condition
Symbol
Parameter
Unit
ns
Min.
Max.
100
IOCS data access time
MCS data access time
RD data access time
ta(IOCS-D)
ta(MCS-D)
ta(RD-D)
Output disable time after IOCS
Output disable time after MCS
Output disable time after RD
WAIT output propagation time after MCS
WAIT output propagation time after WR
WAIT output propagation time after RD
WAIT output propagation time after WAITCNT
tdis(IOCS-D)
tdis(MCS-D)
tdis(RD-D)
30
25
ns
ns
tpHL(MCS-WAIT)
tpHL(WR-WAIT)
tpHL(RD-WAIT)
tpHL(WC-WAIT)
tpLH(CLK-WAIT)
tpd(CLK-CP)
25
40
40
40
ns
ns
ns
ns
WAIT output propagation time after MPUCLK
CP output propagation time after MPUCLK
CL=50pF
tpLH(CLK-LP)
tpHL(CLK-LP)
LP output propagation time after MPUCLK
VD access time
ta(VD)
tpLH(CLK-FLM)
tpHL(CLK-FLM)
40
40
40
40
ns
ns
ns
FLM output propagation time after MPUCLK
M output propagation time after MPUCLK
LCDENB output propagation time after MPUCLK
tpd(CLK-M)
tpLH(CLK-LE)
tpHL(CLK-LE)
tpLH(CLK-CSE)
tpHL(CLK-CSE)
CSE output propagation time after MPUCLK
Data definite time before cancelling WAIT
ns
ns
tpd(D-WAIT)
0
TIMING REQUIREMENTS (VDD=3V±10%, Ta=-20~+75 C)
(1) Accessing to control register
Limits
Ty p.
Test
condition
Symbol
Parameter
IOCS/MCS pulse width
Unit
ns
Min.
50
Max.
tW(CS)
tW(LWR)
LWR pulse width
tsu(D-CS)
Data set up time before rising edge of IOCS/MCS
Data set up time before rising edge of LWR
ns
30
2
tsu(D-LWR)
th(CS-D)
th(LWR-D)
Data hold time after rising edge of IOCS/MCS
Data hold time after rising edge of LWR
ns
ns
Address set up time before falling edge of IOCS/MCS
Address set up time before falling edge of LWR
Address set up time before falling edge of RD
tsu(A-CS)
tsu(A-LWR)
tsu(A-RD)
15
0
th(CS-A)
th(LWR-A)
th(RD-A)
Address hold time after rising edge of IOCS/MCS
Address hold time after rising edge of LWR
Address hold time after rising edge of RD
ns
(2) Accessing to VRAM
Symbol
Limits
Ty p.
Test
condition
Parameter
Unit
ns
Max.
Min.
50
MCS pulse width
WR pulse width
tW(MCS)
tW(WR)
tsu(D-MCS)
tsu(D-WR)
Data set up time before rising edge of MCS
Data set up time before rising edge of WR
30
2
ns
ns
Data hold time after rising edge of MCS
Data hold time after rising edge of WR
th(MCS-D)
th(WR-D)
tsu(A-MCS)
tsu(A-WR)
tsu(A-RD)
th(MCS-A)
th(WR-A)
th(RD-A)
Address set up time before falling edge of MCS
Address set up time before falling edge of WR
Address set up time before falling edge of RD
15
ns
ns
Address hold time after rising edge of MCS
Address hold time after rising edge of WR
Address hold time after rising edge of RD
0
tsu(D-CLK)
tc(CLK)+15
ns
ns
Data set up time before rising edge of WAIT
tsu(MCS-WC)
7
MCS set up time before falling edge of WAITCNT
* tc(CLK)=MPUCLK cycle time
26
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
(3) Clock and accessing to LCD display
Limits
Unit
Test
condition
Symbol
Parameter
MPUCLK cycle time
Min.
50
Ty p.
Max.
tc(CLK)
ns
ns
tWH(CLK)
tWL(CLK)
MPUCLK "H" pulse width
MPUCLK "L" pulse width
tC(CLK)
2
tC(CLK)
(1/n)
Display mode 1,2,3,5,6
Display mode 4
ns
ns
tC(CP)
CP syscle time
2 · tC(CLK)
(1/n)
tWH(CP)
tWL(CP)
CP "H" pulse width
CP "L" pulse width
tC(CLK)
Display mode 1,2,3,5,6
Display mode 4
ns
ns
2 · (1/n)
tWH(CP)
tWL(CP)
CP "H" pulse width
CP "L" pulse width
tC(CLK)
(1/n)
tC(CLK) · LPW
Display mode 1,2,3,5,6
Display mode 4
ns
ns
(1/n)
tW(FLM)
FLM pluse width
2 · tC(CLK) · LPW
(1/n)
1/n =Division of MPUCLK
LPW =Setting value of LPW register
Note : Clock frequency of MPUCLK input is less than fmax = 20MHz.
Limit of clock for the internal operation is fmax = 10MHz.
When MPUCLK is more than 10MHz from extemal input,set clock for the internal operation
up to 10MHz by using division of DIV register.
Division is set with rising dege of MPUCLK input.
Test circuit
VDD
Parameter
tdis(LZ)
SW1
Closed
Open
SW2
Open
Closed
Open
Input
VDD
RL=1KOhm
SW1
tdis(HZ)
ta(ZL)
Closed
D<15:0>
SW2
Closed
ta(ZH)
Open
CL
CL
(1) Input pulse level: 0 to 3V
DUT
P.G
RL=1KOhm
Input pulse rise/fall time: tr,tf=3ns
Input decision voltage: 1.5V
Output decision voltage: VDD/2
(However,tdis(LZ) is 10% of output amplitude and
50Ohm
Outputs
tdis(HZ) is 90% of that for dezision.)
except for
D<15:0>
VSS
(2)
Load capacity CL include float capacity of
connection and input capacity of probe.
27
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
TIMING DIAGRAM
(1) Write to control register ( RD = "H")
No WAIT
tw(CS)
IOCS
(or MCS)
tw(LWR)
LWR
"H"
th(CS-D)
tsu(D-CS)
WAIT
th(LWR-D)
tsu(D-LWR)
Note 1
D<7:0>
Data input is established
tsu(A-CS)
th(CS-A)
th(LWR-A)
tsu(A-LWR)
A<7:0>
Address is established
(or A<14:0>)
(2) Read from control register (LWR= "H")
No WAIT
IOCS
(or MCS)
RD
"H"
WAIT
tdis(CS-D)
tdis(RD-D)
ta(CS-D)
ta(RD-D)
Note 1
D<7:0>
Data output is established
tsu(A-CS)
tsu(A-RD)
th(CS-A)
th(RD-A)
A<7:0>
(orA<14:0>)
Address is established
Note 1 : D<15:0> is used only when 16bit MPU controls the LCD module built-in type support function.
2 : Writing/reading operation for the control register is performed during "L" overlapping of IOCS or MCS and LWR or RD input signal.
Limits of IOCS,MCS, LWR and RD are prescribed by the input signal of last change to "L" in starting access, and by the input
signal of first change to "H" in ending access.
28
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
(3) Write to VRAM ( RD = "H" )
Term of non cycle steal access
tw(MCS)
tw(WR)
MCS
LWR
(+HWR)
"H"
th(MCS-D)
tsu(D-MCS)
tsu(D-WR)
WAIT
th(WR-D)
D<7:0>
Data input is established
(D<15:0>)
tsu(A-MCS)
tsu(A-WR)
th(MCS-A)
th(WR-A)
A<14:0>
(+BHE)
Address is established
(4) Read from VRAM (LWR, HWR = "H")
Term of non cycle steal access
MCS
RD
"H"
WAIT
tdis(MCS-D)
tdis(RD-D)
ta(MCS-D)
ta(RD-D)
D<7:0>
Data output is established
(D<15:0>)
tsu(A-MCS)
tsu(A-RD)
th(MCS-A)
th(RD-A)
A<14:0>
Address is established
Note 3 : Writing/reading operation for VRAM during non cycle steal access is performed during "L" overlapping of MCS and LWR
(+HWR) or RD input signal.
Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the
input signal of first change to "H" in ending access.
29
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
( RD = "H",WAITCNT= "L" or "H" fixed )
(5) Write to VRAM
Term of cycle steal access (and When setting register WAITC to "0")
tC(CLK)
tWH(CLK) tWL(CLK)
MPUCLK
tw(MCS)
MCS
tw(WR)
LWR
(+HWR)
tpLH(CLK-WAIT)
tpHL(MCS-WAIT)
WAIT
th(MCS-D)
th(WR-D)
tsu(D-CLK)
tpHL(WR-WAIT)
D<7:0>
Data input is established
(D<15:0>)
tsu(A-MCS)
tsu(A-WR)
th(MCS-A)
th(WR-A)
A<14:0>
(+BHE)
Address is established
(6) Read from VRAM( LWR, HWR = "H",WAITCNT = "L" or "H" fiexed)
Term of cycle steal access (and when setting segester WAITC to "0")
tC(CLK)
tWH(CLK) tWL(CLK)
MPUCLK
MCS
RD
tpLH(CLK-WAIT)
tpd(D-WAIT)
tpHL(MCS-WAIT)
WAIT
tpHL(RD-WAIT)
tdis(MCS-D)
tdis(RD-D)
ta(MCS-D)
ta(RD-D)
D<7:0>
Data output is established
tsu(A-MCS)
tsu(A-RD)
(D<15:0>)
th(MCS-A)
th(RD-A)
Address is established
A<14:0>
Note 4 :Writing/reading operation for VRAM during cycle steal access needs 0.5tc(MAINCLK) + 1tc(CLK) in best case or 2.5tc(MAINCLK)+1tc(CLK) in
worst case, according to the condition of the internal cycle steal at starting access requested from MPU.
Data output D is established before changing WAIT output.
tc(MAINCLK ) = Reference clock cycle time for internal operation after setting division of MPUCLK.
5 : Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of
first change to "H" in ending access.
6 : Always once return MCS, LWR (+HWR) or RD to "H" after canceling WAIT output. In case of latching "L", as next WAIT does not output, this
causes malfunction to occur.
30
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
(7) Write to VRAM ( RD = "H" )
Term of cycle steal access (and When setting register WAITC to "1")
tC(CLK)
tWH(CLK) tWL(CLK)
MPUCLK
tw(MCS)
MCS
WAITCNT
tsu(MCS-WC)
LWR
(+HWR)
tpLH(CLK-WAIT)
WAIT
th(MCS-D)
th(WR-D)
tsu(D-CLK)
tpHL(WC-WAIT)
D<7:0>
Data input is established
(D<15:0>)
th(MCS-A)
th(WR-A)
tsu(A-WR)
A<14:0>
(+BHE)
Address is established
(8) Read from VRAM ( LWR, HWR = "H")
Term of cycle steal access (and when setting register WAITC to "1")
tC(CLK)
tWH(CLK) tWL(CLK)
MPUCLK
MCS
tsu(MCS-WC)
WAITCNT
RD
tpHL(WC-WAIT)
tpLH(CLK-WAIT)
tpd(D-WAIT)
WAIT
tdis(MCS-D)
tdis(RD-D)
ta(RD-D)
D<7:0>
Data output is established
(D<15:0>)
th(MCS-A)
th(RD-A)
tsu(A-RD)
Address is established
A<14:0>
Note 7 : Writing/reading operation for VRAM during cycle steal access needs 0.5tc(MAINCLK) + 1tc(CLK) in best case or 2.5tc(MAINCLK)+1tc(CLK) in
worst case, according to the condition of the internal cycle steal at starting access requested from MPU.
Data output D is established before changing WAIT output.
tc(MAINCLK ) = Reference clock cycle time for internal operation after setting division of MPUCLK.
8 : When setting WAITC to "1" , MCS is necessary to change "L" earier than LWR (+HWR) ,RD.
Limits of MCS, LWR (+HWR) and RD are prescribed by the input signal of last change to "L" in starting access, and by the input signal of first
change to "H" in ending access.
9 : Always once return MCS, LWR (+HWR) or RD to "H" after canceling WAIT output. In case of latching "L", as next WAIT does not output, this
causes malfunction to occur.
31
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
(9) Interface timing with LCD (DIV = 1 division : set )
(9-1) LCD display data transfer
When DIV = 1 division, MAINCLK for internal operation = MPUCLK input.
tC(CLK)
*
tWH(CLK)
tWL(CLK)
MPUCLK
tpd(CLK-CP)
tWH(CP)
tC(CP)
tWL(CP)
CP
LP
tpLH(CLK-LP)
tpHL(CLK-LP)
ta(VD)
Data is indefinite
VD<n:0>
(9-2) Control signal
MPUCLK
CP
LP
tpLH(CLK-FLM)
tpHL(CLK-FLM)
FLM
M
tW(FLM)
tpd(CLK-M)
tpHL(CLK-LE)
tpLH(CLK-LE)
LCDENB
Note 10 : Output signal to LCD side is synchronized with MAINCLK (reference clock for internal operation).
When division is set to 1/2 to 1/16 by DIV register, switching characteristics is defined by rising edge of MPUCLK.
(10) CSE output timing (DIV=1 divison : set)
MPUCLK
tpLH(CLK-CSE)
tpHL(CLK-CSE)
CSE
32
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
FLOWCHART
EXAMPLE OF INITIALIZE ON DISPLAY MODE 3 (STANDARD ACCESS)
Example
Start
of setting
Note ) When use software reset, surely return to reset off
after reset on.
System reset
RESET input ="L" or use R1-D7(RESET)bit
And then, can't set another bits (D6 to D0) at the
same time.
R1:Basic operation mode register
(RESET,IDXON,DIV,DISP,REV,LCDE)
Set IDXON=OFF,DISP=OFF.
#
(00H)
(02H)
(Set RESET,IDXON,DIV when register is initialized.)
Set display mode, only when register is initialized.
R2:MPU/LCD mode register
(WAITC,SWAP,DUAL,GRAY,4/8)
Note ) Set R1-D6(IDXON) and R2 register at the beginning
of initializing register after system reset.
R3:Number of horizontal display characters
register(CR)
(50H)
(04H)
R4:Horizontal synchronous pulse width
register(LPW)
Set suitable value for LCD.
(Set these value only when register is
initialized.)
R5:Cycle steal enable width register(CSW)
R6:Number of vertical lines register(SLT)
(04H)
(78H)
(00H)
R7:1st screen display start address
register(SA1L)
#
#
Set lower address of 1st screen display start address.
Set upper address of 1st screen display start address.
R8:2nd screen display start address
register(SA1H)
(00H)
(07H)
Set suitable value for LCD.
R11:M output frequency variable register(MT)
R17 to R80:Gray scale pattern register
(Set MT only when register is initialized.)
Set gray scale pattern.
Note ) When access to R17 to R80, must be set DISP=OFF.
Can't access to R17 to R80 on DISP=ON.
Write display data to VRAM
Set display data to VRAM.
N
Complete?
Y
R1:Basic operation mode register
(RESET,IDXON,DIV,DISP,REV,LCDE)
#
Set DISP=ON.
(05H)
Display start
Setting example suppose LCD size = 320x240dots and display mode 3 (Single scan,Gray scale, 4bit transfer).
# Can change R1(DISP,REV,LCDE),R7(SA1L),R6(SA1h) registers value during display on.
33
MITSUBISHI <DIGITAL ASSP>
M66273FP
LCD CONTROLLER with VRAM
Ver.3.1 Dec,1999
EXAMPLE OF INITIALIZE ON DISPLAY MODE 3 (LCD MODULE BUILT-IN ACCESS)
Example
Start
of setting
Note ) When use software reset, surely return to reset off
System reset
RESET input ="L" or use R1-D7(RESET)bit
after reset on.
And then, can't set another bits (D6 to D0) at the
same time.
Set IDXON=ON,DISP=OFF.
R1:Basic operation mode register
(RESET,IDXON,DIV,DISP,REV,LCDE)
#
(40H)
(Set RESET,IDXON,DIV when register is initialized.)
Set display mode, only when register is initialized.
R2:MPU/LCD MODE REGISTER
(WAITC,SWAP,DUAL,GRAY,4/8)
(02H) Note ) Set R1-D6(IDXON) and R2 register at the beginning
of initializing register after system reset.
R3:Number of horizontal display characters
register(CR)
(50H)
R4:Horizontal synchronous pulse width register(LPW)
R5:Cycle steal enable width register(CSW)
R6:Number of vertical lines register(SLT)
(04H)
Set suitable value for LCD.
(Set these value only when register is initialized.)
(04H)
(78H)
R7:1st screen display start address register(SA1L)
#
#
Set lower address of 1st screen display start address.
(00H)
R8:2nd screen display start address register(SA1H)
R11:M output frequency variable register(MT)
Set upper address of 1st screen display start address.
(00H)
Set suitable value for LCD.
(07H)
(Set MT only when register is initialized.)
Set gray scale pattern.
R17 to R80:Gray scale patternregister
Note ) When access to R17 to R80, must be set DISP=OFF.
Can't access to R17 to R80 on DISP=ON.
Discontinuous address
R12,R13 or R15:VRAM address indexregister
Continuous address
Set display data to VRAM.
R14 or R16:Data port register
N
Complete?
Y
R1:Basic operation mode register
(RESET,IDXON,DIV,DISP,REV,LCDE)
#
(45H)
Set DISP=ON.
Display start
Setting example suppose LCD size = 320x240dots and display mode 3 (Single scan,Gray scale, 4bit transfer).
# Can change R1(DISP,REV,LCDE),R7(SA1L),R6(SA1h) registers value during display on.
34
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