M66280FP [RENESAS]
5120 × 8-Bit Line Memory; 5120 × 8位直插式内存型号: | M66280FP |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | 5120 × 8-Bit Line Memory |
文件: | 总14页 (文件大小:160K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
M66280FP
5120 × 8-Bit Line Memory
REJ03F0253-0200
Rev.2.00
Sep 14, 2007
Description
The M66280FP is high speed line memory that uses high performance silicon gate CMOS process technology and
adopts the FIFO (First In First Out) structure consisting of 5120 words × 8 bits.
The M66280FP, performing reading and writing operations at different cycles independently and asynchronously, is
optimal for buffer memory to be used between equipment of different data processing speeds.
Features
•
•
•
•
•
•
•
•
Memory configuration:
High speed cycle:
High speed access:
Output hold:
5120 words × 8 bits (dynamic memory)
25 ns (Min)
18 ns (Max)
3 ns (Min)
Reading and writing operations can be completely carried out independently and asynchronously
Variable length delay bit
Input/output:
Output:
TTL direct connection allowable
3 states
Application
Digital copying machine, laser beam printer, high speed facsimile, etc.
Block Diagram
Data inputs
D0 to D7
Data outputs
Q0 to Q7
13 14 15 16 21 22 23 24
1 2 3 4 9 10 11 12
Input buffer
Output buffer
REB
20
19
5
6
WEB
Read
Write
enable input
enable input
Memory array
RRESB
Read
reset input
WRESB
Write
reset input
5120 × 8 bits
17
18
8
7
RCK
WCK
Write
clock input
Read
clock input
GND
VCC
REJ03F0253-0200 Rev.2.00 Sep 14, 2007
Page 1 of 13
M66280FP
Pin Arrangement
M66280FP
1
2
24
23
22
21
20
19
18
17
16
15
14
13
Q0
Q1
D0
D1
Data output
Data input
3
Q2
D2
4
Q3
D3
5
Read enable input
Read reset input
Write enable input
Write reset input
REB
RRESB
GND
RCK
Q4
WEB
WRESB
VCC
WCK
D4
6
7
8
Read clock input
Data output
Write clock input
Data input
9
10
11
12
Q5
D5
Q6
D6
Q7
D7
(Top view)
Outline: PRSP0024GA-A (24P2Q-A)
REJ03F0253-0200 Rev.2.00 Sep 14, 2007
Page 2 of 13
M66280FP
Absolute Maximum Ratings
(Ta = 0 to 70°C, unless otherwise noted)
Item
Symbol
Ratings
−0.3 to +4.6
−0.3 to VCC + 0.3
−0.3 to VCC + 0.3
300
Unit
V
Conditions
Supply voltage
Input voltage
Output voltage
VCC
VI
Value based on the GND pin
V
VO
V
Power dissipation
Pd
mW
°C
Ta = 25°C
Storage temperature
Tstg
−55 to 150
Recommended Operating Conditions
Item
Symbol
VCC
Min
2.7
Typ
3.15
0
Max
3.6
Unit
V
Supply voltage
Supply voltage
GND
V
Operating temperature
Topr
0
70
°C
Electrical Characteristics
(Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item
Symbol
VIH
Min
2.0
Typ Max
Unit
V
Test Conditions
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
High-level input current
0.8
VIL
V
VOH
VOL
V
CC − 0.8
V
IOH = −4 mA
0.55
1.0
V
IOL = 4 mA
VI = VCC
IIH
µA
WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 to D7
Low-level input current
IIL
−1.0
µA
VI = GND WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 to D7
Off-state high-level output current
Off-state low-level output current
IOZH
IOZL
ICC
5.0
−5.0
70
µA
µA
VO = VCC
VO = GND
Average supply current during
operation
mA
VI = VCC, GND, Output open
t
WCK, tRCK = 25 ns
Input capacitance
CI
10
15
pF
pF
f = 1 MHz
f = 1 MHz
Off-time output capacitance
CO
Function
When write enable input WEB is set to "L", the contents of data inputs D0 to D7 are read in synchronization with a
rising edge of write clock input WCK to perform writing operation. When this is the case, the write address counter is
also incremented simultaneously.
When WEB is set to "H", the writing operation is inhibited and the write address counter stops.
When write reset input WRESB is set to "L", the write address counter is initialized.
When read enable input REB is set to "L", the contents of memory are output to data outputs Q0 to Q7 in
synchronization with a rising edge of read clock input RCK to perform reading operation. When this is the case, the
read address counter is incremented simultaneously.
When REB is set to "H", the reading operation is inhibited and the read address counter stops. The outputs are placed
in a high impedance state.
When read reset input RRESB is set to "L", the read address counter is initialized.
REJ03F0253-0200 Rev.2.00 Sep 14, 2007
Page 3 of 13
M66280FP
Switching Characteristics
(Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item
Access time
Symbol
tAC
Min
3
Typ
Max
18
Unit
ns
Output hold time
tOH
ns
Output enable time
Output disable time
tOEN
tODIS
3
18
ns
3
18
ns
Timing Requirements
(Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item
Symbol
tWCK
Min
25
11
11
25
11
11
7
Typ
Max
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Write clock (WCK) cycle
Write clock (WCK) "H" pulse width
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
tWCKH
tWCKL
tRCK
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
Input data setup time for WCK
Input data hold time for WCK
Reset setup time for WCK/RCK
Reset hold time for WCK/RCK
Reset non-selection setup time for WCK/RCK
Reset non-selection hold time for WCK/RCK
WEB setup time for WCK
tRCKH
tRCKL
tDS
tDH
3
tRESS
tRESH
tNRESS
tNRESH
tWES
tWEH
tNWES
tNWEH
tRES
7
3
7
3
7
WEB hold time for WCK
3
WEB non-selection setup time for WCK
WEB non-selection hold time for WCK
REB setup time for RCK
7
3
7
REB hold time for RCK
tREH
3
REB non-selection setup time for RCK
REB non-selection hold time for RCK
Input pulse up/down time
tNRES
tNREH
tr, tf
7
3
Data hold time*
tH
Notes: Perform reset operation after turning on power supply.
For 1 line access, the following conditions must be satisfied:
*
WEB high-level period ≤ 20 ms − 5120 • tWCK − WRESB low-level period
REB high-level period ≤ 20 ms − 5120 • tRCK − RRESB low-level period
REJ03F0253-0200 Rev.2.00 Sep 14, 2007
Page 4 of 13
M66280FP
Switching Characteristics Measurement Circuit
VCC
RL = 1 kΩ
Qn
SW1
CL = 30 pF: tAC, tOH
Qn
SW2
CL = 5 pF: tOEN, tODIS
RL = 1 kΩ
Input pulse level:
0 to 3 V
Input pulse up/down time: 3 ns
Judging voltage Input: 1.3 V
Output: 1.3 V (However, tODIS (LZ) is judged with 10% of the output amplitude, while tODIS (HZ) is
judged with 90% of the output amplitude)
Load capacitance CL includes the floating capacity of connected lines and input capacitance of probe.
Item
SW1
Close
Open
Close
Open
SW2
Open
Close
Open
Close
tODIS (LZ)
tODIS (HZ)
tOEN (ZL)
tOEN (ZH)
tODIS and tOEN Measurement Condition
3 V
RCK
1.3 V
1.3 V
GND
3 V
REB
GND
tODIS (HZ)
tOEN (ZH)
VOH
90%
1.3 V
Qn
tODIS (LZ)
tOEN (ZL)
Qn
1.3 V
VOL
10%
REJ03F0253-0200 Rev.2.00 Sep 14, 2007
Page 5 of 13
M66280FP
Operation Timing
Write Cycle
n cycle
n + 1 cycle
n + 2 cycle
Disable cycle
n + 3 cycle n + 4 cycle
WCK
tWCK
tWCKH tWCKL tWEH tNWES
tNWEH tWES
WEB
Dn
tDS tDH
(n)
(n + 1)
(n + 2)
(n + 3)
(n + 4)
WRESB = "H"
Write Reset Cycle
n − 1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
2 cycle
WCK
tWCK
tNRESH tRESS
tRESH tNRESS
WRESB
tDS tDH
(n − 1)
(n)
(0)
(1)
(2)
Dn
WEB = "L"
REJ03F0253-0200 Rev.2.00 Sep 14, 2007
Page 6 of 13
M66280FP
Matters that Needs Attention when WCK Stops
n cycle
n + 1 cycle
n cycle
Disable cycle
WCK
WEB
tWCK
tNWES
tDS tDH
tDS tDH
Dn
(n)
(n)
Period for writing data (n)
into memory
Period for writing data (n)
into memory
WRESB = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level
period of n + 1 cycle. The writing operation is complete at the falling edge after n + 1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n + 1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
REJ03F0253-0200 Rev.2.00 Sep 14, 2007
Page 7 of 13
M66280FP
Read Cycle
n cycle
n + 1 cycle
n + 2 cycle
Disable cycle
n + 3 cycle n + 4 cycle
RCK
REB
tRCK
tRCKH tRCKL tREH tNRES
tNREH tRES
tAC
tODIS
tOEN
HIGH-Z
(n)
(n + 1)
(n + 2)
(n + 3)
tOH
(n + 4)
Qn
RRESB = "H"
Read Reset Cycle
n − 1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
2 cycle
RCK
tRCK
tNRESH tRESS
tRESH tNRESS
RRESB
tAC
(n − 1)
(n)
(0)
(0)
(0)
tOH
(1)
(2)
Qn
REB = "L"
REJ03F0253-0200 Rev.2.00 Sep 14, 2007
Page 8 of 13
M66280FP
Variable Length Delay Bit
1 Line (5120 Bits) Delay
Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK
before read cycle to easily make 1 line delay.
5120 cycle 5121 cycle 5122 cycle
0 cycle
1 cycle
2 cycle
5118 cycle 5119 cycle
(0')
(1')
(2')
WCK
RCK
tRESS tRESH
WRESB
RRESB
tDS tDH
tDS tDH
(0)
(1)
(2)
(5117)
(5118)
(5119)
(0')
(1')
(1)
(2')
(2)
(3')
(3)
Dn
Qn
tAC
tOH
5120 cycle
(0)
WEB, REB = "L"
n-bit Delay Bit
(Reset at cycles according to the delay length)
n cycle n + 1 cycle n + 2 cycle n + 3 cycle
(0') (1') (2') (3')
0 cycle
1 cycle
2 cycle
n − 2 cycle n − 1 cycle
WCK
RCK
tRESS tRESH
tRESS tRESH
WRESB
RRESB
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 3)
(n − 2)
(n − 1)
(0')
(1')
(1)
(2')
(2)
(3')
(3)
Dn
Qn
tAC
tOH
m cycle
(0)
WEB, REB = "L"
m ≥ 3
REJ03F0253-0200 Rev.2.00 Sep 14, 2007
Page 9 of 13
M66280FP
n-bit Delay 2
(Slides input timings of WRESB and RRESB at cycles according to the delay length)
0 cycle
1 cycle
2 cycle n − 2 cycle n − 1 cycle
n cycle
n + 1 cycle n + 2 cycle n + 3 cycle
WCK
RCK
tRESS tRESH
WRESB
RRESB
tRESS tRESH
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 2)
(n − 1)
(n)
(n + 1)
(n + 2)
(n + 3)
Dn
Qn
tAC
tOH
m cycle
(0)
(1)
(2)
(3)
WEB, REB = "L"
m ≥ 3
n-bit Delay 3
(Slides address by disabling REB in the period according to the delay length)
0 cycle
1 cycle
2 cycle
n − 1 cycle
n cycle
n + 1 cycle n + 2 cycle n + 3 cycle
WCK
RCK
tRESS tRESH
WRESB
RRESB
tNREH tRES
REB
Dn
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 2)
(n − 1)
(n)
(n + 1)
(n + 2)
(n + 3)
tAC
tOH
m cycle
HIGH-Z
(0)
(1)
(2)
(3)
Qn
WEB = "L"
m ≥ 3
REJ03F0253-0200 Rev.2.00 Sep 14, 2007
Page 10 of 13
M66280FP
Reading Shortest n-cycle Write Data "n"
(Reading side n − 1 cycle starts after the end of writing side n − 1 cycle)
When the reading side n − 1 cycle starts before the end of the writing side n + 1 cycle, output Qn of n cycle is made
invalid. In the following diagram, reading operation of n − 1 cycle is invalid.
n cycle
n + 1 cycle
n + 2 cycle
n + 3 cycle
WCK
Dn
(n)
(n +1)
(n +2)
(n +3)
n − 2 cycle
n − 1 cycle
n cycle
RCK
Qn
Invalid
(n)
Reading Longest n-cycle Write Data "n": 1 Line Delay
(When writing side n-cycle <2>* starts, reading side n cycle <1>* then starts)
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle
<2>* overlap each other.
n cycle <1>*
0 cycle <2>*
n cycle <2>*
WCK
Dn
(n − 1) <1>*
(n) <1>*
(0) <2>*
(n − 1) <2>*
(n) <2>*
n cycle <0>*
0 cycle <1>*
n cycle <1>*
RCK
Qn
(n − 1) <0>*
(n) <0>*
(0) <1>*
(n − 1) <1>*
(n) <1>*
Note: <0>*, <1>* and <2>* indicate value of lines.
REJ03F0253-0200 Rev.2.00 Sep 14, 2007
Page 11 of 13
M66280FP
Application Example
Sub Scan Resolution Compensation Circuit with Laplacian Filter
N
M66280
n line image data
D0 Q0
to
to
B
D7 Q7
(n + 1) line
image data
Compensated
image data
× 2
1 line
delay
× K
M66280
D0 Q0
A
(n − 1) line
image data
to
to
D7 Q7
1 line
delay
Main scan direction
A
N
B
(n − 1) line
n line
N' = N + K { (N − A) + (N − B) }
= N + K {2N − (A + B)}
K: Laplacian coefficient
(n + 1) line
REJ03F0253-0200 Rev.2.00 Sep 14, 2007
Page 12 of 13
M66280FP
Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
24P2Q-A
MASS[Typ.]
0.2g
P-SSOP24-5.3x10.1-0.80
PRSP0024GA-A
24
13
NOTE)
1. DIMENSIONS "*1" AND "*2"
F
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
1
12
Index mark
Dimension in Millimeters
Reference
c
A2
A1
*2
Symbol
D
Min Nom Max
D
E
10.0 10.1 10.2
5.2 5.3 5.4
A2
A
1.8
2.1
A1
bp
c
0.1 0.2
0.35 0.45
0
0.3
0.18
0°
*3
0.25
0.2
bp
e
y
8°
HE
e
y
7.5 7.8 8.1
Detail F
0.65
0.95
0.10
0.8
L
0.4 0.6 0.8
REJ03F0253-0200 Rev.2.00 Sep 14, 2007
Page 13 of 13
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.0
相关型号:
©2020 ICPDF网 联系我们和版权申明