M66281FP [MITSUBISHI]
5120 x 8-BIT x 2 LINE MEMORY; 5120 ×8位× 2行存储
| 型号： | M66281FP |
| 厂家： | 
Mitsubishi Group |
| 描述： | 5120 x 8-BIT x 2 LINE MEMORY |
| 文件： | 总13页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
When write reset input WRESB is set to "L", the write address
counter of memory only for 1 line delay data is initialized.
When read enable input REB is set to "L", the contents of memory
only for 1 line delay data are output to data outputs Q00 to Q07
and the contents of memory only for 2 line delay data are output to
Q10 to Q17 in synchronization with a rising edge of read clock
input RCK to perform reading operation.
When this is the case, the read address counters of memory only
for 1 line delay data and memory only for 2 line delay data are
incremented simultaneously.
In addition, data of Q00 to Q07 is written into memory only for 2
line delay data in synchronization with a rising edge of RCK. When
this is the case, the write address counter of memory only for 2 line
delay data is then incremented.
When REB is set to "H", operation for reading data from memory
only for 1 line delay and from memory only for 2 line delay data is
inhibited and the read address counter of each memory stops.
Outputs Q00 to Q07 and Q10 to Q17 are placed in a high
impedance state. In addition, the write address counter of memory
only for 2 line delay data then stops.
DESCRIPTION
The M66281FP is high speed line memory that uses high
performance silicon gate CMOS process technology and adopts the
FIFO (First In First Out) structure consisting of 5120 words x 8 bits
x 2.
Since memory is available to simultaneously output 1 line delay and
2 line delay data, the M66281FP is optimal for the compensation of
data of multiple lines.
FEATURES
• Memory configuration 5120 words x 8 bits x 2 (dynamic memory)
• High speed cycle
• High speed access
• Output hold
• Reading and writing operations can be completely carried out
independently and asynchronously.
• Variable length delay bit
• Input/output
• Output
25 ns (Min.)
18 ns (Max.)
3 ns (Min.)
TTL direct connection allowable
3 states
1 line delay
• Q00 – Q07
• Q10 – Q17
When read reset input RRESB is set to "L", the read address
counters of memory only for 1 line delay data as well as the write
address counter and read address counter of memory only for 2
line delay data are then initialized.
2 line delay
APPLICATION
• Digital copying machine
, laser beam printer, high speed facsimile,
etc.
FUNCTION
When write enable input WEB is set to "L", the contents of data
inputs D0 to D7 are written into memory only for 1 line delay data in
synchronization with a rising edge of write clock input WCK to
perform writing operation. When this is the case, the write address
counter of memory only for 1 line delay data is incremented
simultaneously.
When WEB is set to "H", the writing operation is inhibited and the
write address counter of memory only for 1 line delay data stops.
PIN CONFIGURATION (TOP VIEW)
24
23
22
21
20
19
18
17
16
15
NC
D5
39
40
41
42
43
NC
RCK
D6
RRESB
REB
D7
GND
VCC
Q17
Q16
Q15
NC
GND
M66281FP
VCC 44
Q00
45
Q01 46
47
48
Q02
NC
Outline 48P6S-A(QFP)
NC : No connection
1
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
Read control circuit
Read address counter
Write address counter
Write control circuit
2
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
ABSOLUTE MAXIMUM RATINGS (Ta=0 – 70 °C unless otherwise noted)
Symbol
Parameter
Conditions
Unit
Ratings
Vcc
Supply voltage
-0.3 – +4.6
-0.3 – VCC+0.3
-0.3 – VCC+0.3
540
V
V
VI
Input voltage
Value based on the GND pin
Note
VO
Pd
Tstg
Output voltage
V
mW
Power dispersion
Storage temperature
-55 – 150
°C
Note : Ta=0 – 63˚C. Ta > 63˚C are derated at -9mW/˚C
RECOMMENDED OPERATING CONDITIONS
Limits
Typ.
3.15
0
Symbol
Parameter
Unit
Min.
2.7
Max.
3.6
Vcc
Supply voltage
Supply voltage
V
V
GND
Topr
0
70
Operating temperature
°C
ELECTRICAL CHARACTERISTICS (Ta=0 – 70 °C, Vcc=2.7 – 3.6V, GND=0V unless otherwise noted)
Limits
Symbol
Parameter
Conditions
Unit
Min.
2.0
Typ.
Max.
0.8
VIH
VIL
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
V
V
V
V
VOH
VOL
IOH = -4mA
IOL = 4mA
VCC-0.4
0.4
WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 – D7
µ A
High-level input current
IIH
IIL
VI = VCC
1.0
WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 – D7
µ A
-1.0
VI = GND
Low-level input current
µ A
µ A
IOZH
IOZL
Off-state high-level output current
Off-state low-level output current
VO = VCC
5.0
VO = GND
-5.0
VI = VCC, GND, output open
tWCK, tRCK = 25ns
mA
ICC
Average supply current during operation
150
10
15
pF
pF
CI
Input capacitance
f = 1MHz
f = 1MHz
CO
Off-time output capacitance
3
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
SWITCHING CHARACTERISTICS (Ta=0 – 70 °C, Vcc=2.7 – 3.6V, GND=0V unless otherwise noted)
Limits
Parameter
Symbol
Unit
Min.
Typ.
Max.
18
ns
ns
ns
ns
tAC
Access time
tOH
Output hold time
Output enable time
Output disable time
3
3
3
tOEN
tODIS
18
18
TIMING REQUIREMENTS (Ta=0 – 70 °C, Vcc=2.7 – 3.6V, GND=0V unless otherwise noted)
Limits
Typ.
Parameter
Symbol
Unit
Min.
25
11
11
25
11
11
7
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tWCK
tWCKH
tWCKL
tRCK
Write clock (WCK) cycle
Write clock (WCK) "H" pulse width
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
tRCKH
tRCKL
tDS
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
Input data set up time for WCK
Input data hold time for WCK
Reset set up time for WCK/RCK
Reset hold time for WCK/RCK
tDH
3
tRESS
tRESH
tNRESS
tNRESH
tWES
tWEH
tNWES
tNWEH
tRES
7
3
Reset non-selection set up time for WCK/RCK
Reset non-selection hold time for WCK/RCK
WEB set up time for WCK
7
3
7
WEB hold time for WCK
3
WEB non-selection set up time for WCK
WEB non-selection hold time for WCK
REB set up time for RCK
7
3
7
tREH
REB hold time for RCK
3
tNRES
tNREH
tr, tf
REB non-selection set up time for RCK
REB non-selection hold time for RCK
Input pulse up/down time
7
3
20
20
tH
Data hold time (Note 1)
Note 1: For 1 line access, the following conditions must be satisfied:
WEB high-level period ≤ 20 ms - 5120 • tWCK - WRESB low-level period
REB high-level period ≤ 20 ms - 5120 • tRCK - RRESB low-level period
2: Perform reset operation after turning on power supply.
4
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT
VCC
RL=1KΩ
SW1
SW2
Qn
Qn
CL = 5pF : tOEN, tODIS
CL = 30pF : tAC, tOH
RL=1KΩ
Input pulse level
Input pulse up/down time
Judging voltage Input
Output
: 0 – 3V
: 3 ns
: 1.3V
Item
SW1
SW2
Open
Close
Open
Close
tODIS(LZ)
tODIS(HZ)
tOEN(ZL)
tOEN(ZH)
Close
Open
Close
Open
: 1.3V(However, tODIS(LZ) is judged with 10% of the
output amplitude, while tODIS(HZ) is judged with
90% of the output amplitude.)
Load capacitance CL includes the floating capacity of connected lines and input
capacitance of probe.
tODIS and tOEN measurement condition
3V
1.3V
1.3V
RCK
GND
3V
REB
GND
tOEN(ZH)
tOEN(ZL)
tODIS(HZ)
VOH
90%
Qn
Qn
1.3V
tODIS(LZ)
1.3V
10%
VOL
5
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
OPERATION TIMING
• Write cycle
n cycle
n+1 cycle
n+2 cycle
Disable cycle
n+3 cycle
n+4 cycle
WCK
WEB
tWCKH tWCKL
tWEH tNWES
tNWEH
tWES
tWCK
tDS tDH
(n)
(n+1)
(n+2)
(n+3)
(n+4)
Dn
WRESB = "H"
• Write reset cycle
n cycle
0 cycle
1 cycle
2 cycle
n-1 cycle
Reset cycle
WCK
tWCK
tNRESH tRESS
tRESH tNRESS
WRESB
tDS tDH
(n-1)
(n)
(0)
(1)
(2)
Dn
WEB = "L"
6
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
• Matters that needs attetion when WCK stops
n+1 cycle
n cycle
tWCK
n cycle
Disable cycle
WCK
WEB
tNWES
tDS tDH
tDS tDH
(n)
(n)
Dn
Period for writing data
(n) into memory
Period for writing data
(n) into memory
WRESB = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period of n+1
cycle. The writing operation is complete at the falling edge after n+1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n+1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
7
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
• Read cycle
n+1 cycle
n+2 cycle
n+3 cycle
n+4 cycle
n cycle
tRCK
Disable cycle
RCK
REB
tNREH
tRES
tRCKH tRCKL tREH tNRES
tAC
tOEN
tODIS
Q0n
HIGH-Z
(n)
(n+1)
(n+2)
(n+3)
tOH
(n+4)
(Q1n)
RRESB = "H"
• Read reset cycle
n-1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
2 cycle
RCK
tRCK
tNRESH tRESS
tRESH
tNRESS
RRESB
tAC
Q0n
(0)
(n)
(0)
(0)
(1)
(2)
(n-1)
(Q1n)
tOH
REB = "L"
8
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
• Notes on reading of written data in read disable
When writing operation is performed at n cycle and n+1 cycle on the writing side in the read disable period after n-1 cycle on
the reading side, output at n cycle and n+1 cycle after read enable is invalid. For output at n+2 cycle and after, however, data
written in the read disable period is to be output.
n-1 cycle
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
n+4 cycle
n+5 cycle
n+6 cycle
n+7 cycle
WCK
tDS tDH
Dn
(n-1)
(n)
(n+1)
(n+2)
(n+3)
(n+4)
(n+5)
(n+6)
(n+7)
n-1 cycle
Disable cycle
n cycle
n+1 cycle
n+2 cycle
RCK
REB
tAC
tODIS
tOEN
HIGH-Z
Q0n
invalid
invalid
(n+2)
(n-1)
(Q1n)
WEB = "L"
WRESB = "H"
RRESB = "H"
9
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
VARIABLE LENGTH DELAY BIT
• 1 line (5120 bits) delay
Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK before read
cycle to easily make 1 line delay.
5120 cycle 5121 cycle 5122 cycle
0 cycle
1 cycle
2 cycle
5118 cycle 5119 cycle
(0')
(1')
(2')
WCK
RCK
tRESH
tRESS
WRESB
RRESB
tDS tDH
tDS tDH
(0')
(1')
(2')
(3')
Dn
(0)
(1)
(2)
(5117)
(5118)
(5119)
5120 cycle
tAC
tOH
(0)
Q0n
(1)
(2)
(3)
(Q1n)
WEB, REB = "L"
• n-bit delay bit
(Reset at cycles according to the delay length)
n cycle
(0')
n+1 cycle n+2 cycle n+3 cycle
(1') (2') (3')
n-2 cycle
n-1 cycle
0 cycle
1 cycle
2 cycle
WCK
RCK
tRESS tRESH
tRESS tRESH
WRESB
RRESB
tDS tDH
tDS tDH
(0')
(n-3)
(n-2)
(n-1)
(1')
(2')
(3')
Dn
(0)
(1)
(2)
m cycle
tAC
tOH
(0)
Q0n
(1)
(2)
(3)
(Q1n)
WEB, REB = "L"
m≥3
10
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
• n-bit delay 2
(Slides input timings of WRESB and RRESB at cycles according to the delay length.)
0 cycle
1 cycle
2 cycle
n-2 cycle
n-1 cycle
n cycle
n+1 cycle n+2 cycle
n+3 cycle
WCK
RCK
tRESS tRESH
WRESB
tRESS tRESH
RRESB
Dn
tDS tDH
tDS tDH
(n+1)
(0)
(1)
(2)
(n-2)
(n-1)
(n)
(n+2)
(n+3)
m cycle
tAC
tOH
Q0n
(Q1n)
(0)
(1)
(2)
(3)
WEB, REB = "L"
m≥3
• n-bit delay 3
(Slides address by disabling REB in the period according to the delay length.)
0 cycle
1 cycle
2 cycle
n-1 cycle
n cycle
n+1 cycle n+2 cycle n+3 cycle
WCK
RCK
tRESS tRESH
WRESB
RRESB
tNREH tRES
REB
Dn
tDS tDH
(n)
tDS tDH
(0)
(1)
(2)
(n-2)
(n-1)
(n+1)
(n+2)
(n+3)
m cycle
tAC
tOH
Q0n
(Q1n)
HIGH-Z
invalid
(1)
(2)
(3)
WEB = "L"
m≥3
11
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
• Reading shortest n-cycle write data "n"
(Reading side n-2 cycle ends after the end of writing side n+1 cycle.)
When the reading side n-2 cycle ends before the end of the writing side n+1 cycle, output Qn of n cycle is made invalid.
In the following diagram, end of reading side n-2 cycle and end of writing side n+1 cycle overlap each other. This example can read n cycle
data in the shortest time. When this is the case, reading operation at n-1 cycle is invalid.
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
WCK
Dn
(n)
(n+1)
(n+2)
(n+3)
n-2 cycle
n-1 cycle
n cycle
RCK
Q0n
(n)
invalid
(Q1n)
• Reading longest n-cycle write data "n": 1 line delay
(When writing side n-cycle <2> starts, reading side n cycle <1> then starts.)
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each
other.
n cycle <2>*
n cycle <1>*
0 cycle <2>*
WCK
(n-1)<1>*
(n)<1>*
(0)<2>*
(n-1)<2>*
(n)<2>*
Dn
n cycle <0>*
0 cycle <1>*
n cycle <1>*
RCK
Q0n
(0)<1>*
(n-1)<1>*
(n)<1>*
(n-1)<0>*
(n)<0>*
(Q1n)
<0>*, <1>* and <2>* indicate value of lines.
12
MITSUBISHI <DIGITAL ASSP>
M66281FP
5120 x 8-BIT x 2 LINE MEMORY
APPLICATION EXAMPLE
Sub Scan Resolution Compensation Circuit with Laplacean Filter
N
M66281
n line image data
D0 Q00
D7 Q07
B
(n+1) line
image data
X2
1 line
delay
Compensated
image data
XK
Q10
Q17
A
(n-1) line
image data
2 line
delay
Main scan direction
(n-1) line
n line
A
N
B
(n+1) line
N'=N+K { (N-A) + (N-B) }
=N+K { (2N - (A+B) }
K: Laplacean coefficient
13
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