M66288FP [RENESAS]
262144-word x 8-bit x 3-FIFO MEMORY; 262144字×8位x 3 - FIFO存储器
| 型号： | M66288FP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 262144-word x 8-bit x 3-FIFO MEMORY |
| 文件： | 总24页 (文件大小：511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REJ03F0156-0310
Rev. 03.10
M66288FP
262144-word x 8-bit x 3-FIFO MEMORY
Apr.4.2008
Description
The M66288FP is a high-speed field memory with three FIFO (First In First Out) memories of 262144-word x 8-bit
configuration (2M-bit), which uses high-performance silicon gate CMOS process technology. One of three FIFO memories
consists of two FIFO memories of 262144-word x 4-bit (1M-bit). Eight types of operation can be performed by mode
settings.
Features
z Memory configuration
Total memory capacity is 6M-bit (static memory).
Eight types of memory configurations can be selected.
12.5 ns (Min.) fmax 80MHz
9.0 ns (Max.)
2.0 ns (Min.)
z High - speed cycle
z High - speed access
z Output hold
z Supply voltage
Internal = 1.8 V ± 0.18 V, I/O = 3.3 V ± 0.3 V
z Variable length delay bit
z Eight modes can be selected
z Write and Read function can be operated completely independently and asynchronously
z Output type
z Package
3 state output
100pin 14x14mm body LQFP (PLQP0100KB-A, 100P6Q-A)
Application
W-CDMA base station, Digital PPC, Digital television, VTR and so on.
Pin Configuration (Top view)
76
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VccIO
GND
Vcc18
GND
VccIO
QC7
QC6
QC5
QC4
QC3
QC2
QC1
QC0
GND
VccIO
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
GND
Vcc18
GND
77
GND
78
Vcc18
79
QA0
80
QA1
81
QA2
82
QA3
83
QA4
84
QA5
85
QA6
86
QA7
87
GND
88
VccIO
89
90
91
92
93
94
95
96
97
98
99
100
M66288FP
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
GND
Vcc18
TEST1
TEST2
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 1 of 23
M66288FP
Mode Descriptions Drawing
1K-word = 1024-word
256K-word
MODE 3
8-bit bus I/F
MODE 2
12-bit bus I/F
MODE 5
MODE 1
MODE 4
12
12
8
8
8
8
8
8
8
8
12
12
DA<7:0>
WCKA
WRESA
WEA
DA<7:0>
WCKA
QA<7:0>
RCKA
QA<7:0>
RCKA
DA<11:0>
QA<11:0>
DA<7:0>
WCKA
WRESA
WEA
QA<7:0>
RCKA
DA<11:0>
WCKA
QA<11:0>
RCKA
256K-w
x
8-bit
FIFO
256K-w
x
8-bit
FIFO
256K-w
x
256K-w
x
12-bit
FIFO
256K-w
x
12-bit
FIFO
WCKA
WRESA
WEA
RCKA
RRESA
REA
WRESA
RRESA
8-bit
FIFO
RRESA
REA
RRESA
REA
WRESA
WEA
RRESA
REA
WEA
REA
8
DB<7:0>
WCKB
WRESB
WEB
QB<7:0>
RCKB
256K-w
256K-w
x
8-bit
FIFO
256K-w
x
8-bit
FIFO
8
8
8
8
x
QB<7:0>
QB<7:0>
8-bit
FIFO
RRESB
REB
12
12
DB<11:0>
WCKB
QB<11:0>
RCKB
12 256K-w 12
256K-w
x
12-bit
FIFO
x
QB<11:0>
12-bit
FIFO
8
8
8
WRESB
WEB
RRESB
REB
DC<7:0>
WCKC
WRESC
WEC
QC<7:0>
RCKC
DC<7:0>
WCKC
WRESC
WEC
QC<7:0>
RCKC
256K-w
x
8-bit
FIFO
256K-w
x
8-bit
FIFO
256K-w
x
8-bit
FIFO
8
8
QC<7:0>
RRESC
REC
RRESC
REC
The three pieces of 256K-word x
8-bit FIFO can be operated
completely independently.
The three pieces of 256K-word x
8-bit FIFO are cascade-connected.
(Note 1)
The two pieces of 256K-word x
8-bit FIFO are cascade-connected
and, a piece of 256K-word x 8-bit
FIFO can be operated completely
independently. (Note 1)
The two pieces of 256K-word x
12-bit FIFO can be operated
completely independently.
(Note 2)
The two pieces of 256K-word x
12-bit FIFO are cascade-connected
(Note 1, Note 2)
3-system individual input
3-system individual output
1-system input
(1) 1-system input
(2) 1-system input
(1) The simultaneous output of the
1, 2 line delay data.
2-system individual input.
2-system individual output.
1-system input
The simultaneous output of the
1, 2, 3 line delay data.
The simultaneous output of the
1, 2 line delay data.
(2) 1-system output
768K-word
512K-word & 256K-word
MODE 7
512K-word
12-bit bus I/F
MODE 8
8-bit bus I/F
MODE 6
8
8
8
8
12
12
DA<7:0>
QA<7:0>
DA<7:0>
QA<7:0>
DA<11:0>
QA<11:0>
768K-w
x
8-bit
FIFO
512K-w
x
8-bit
FIFO
512K-w
x
12-bit
FIFO
WCKA
WRESA
WEA
RCKA
RRESA
REA
WCKA
WRESA
WEA
RCKA
RRESA
REA
WCKA
WRESA
WEA
RCKA
RRESA
REA
8
8
DC<7:0>
QC<7:0>
256K-w
x
8-bit
FIFO
WCKC
WRESC
WEC
RCKC
RRESC
REC
A piece of 768K-word x 8-bit
FIFO can be operated completely
independently.
A piece of 512K-word x 8-bit FIFO
and a piece of 256K-word x 8-bit
FIFO can be operated completely
independently.
A piece of 512K-word x 12-bit
FIFO can be operated completely
independently. (Note 2)
1-system input
1-system output
2-system individual input
2-system individual output
1-system input
1-system output
Note1: Write and read operation of FIFO after the 2nd line is controlled by the read system pin of the 1st line FIFO.
Maximum number of words on this mode is 256K-word. Line delay is achieved without outer connection.
Note2: Please refer to pin assignment tables in “Operation Description” of Mode 4, Mode 5, and Mode 8 for assignment of external pins,
Dx<11:0> and Qx<11:0> when used in 12-bit bus interface.
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 2 of 23
M66288FP
Block Diagram
Data input
DC<7:0>
DA<7:0>
DB<7:0>
INPUT BUFFER
Mode setting
Mode setting input
MODE<3:1>
MODE CONTROL CIRCUIT
Read control inputs
for A-system
Write control inputs
for A-system
RCKA
RRESA
REA
WCKA
WRESA
WEA
MEMORY ARRAY
Read control inputs
for B-system
Write control inputs
for B-system
256K-word x 8bit
RCKB
RRESB
REB
WCKB
WRESB
WEB
256K-word x 4bit
256K-word x 4bit
Read control inputs
for C-system
Write control inputs
for C-system
256K-word x 8bit
RCKC
RRESC
REC
WCKC
WRESC
WEC
MODE CONTROL CIRCUIT
Test setting input
TEST<3:1>
OUTPUT BUFFER
VccIO
Vcc18
GND
GND
Data output
QC<7:0>
QB<7:0>
QA<7:0>
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 3 of 23
M66288FP
Pin Function Descriptions
Pin name
Name
Input /
Output
Input
Number
of pins
3
Function
They are write clock inputs.
WCK x
Write clock input
WE x
Write enable input
Write reset input
Read clock input
Read enable input
Read reset input
Data input
Input
Input
Input
Input
Input
Input
Output
Input
Input
3
3
They are write enable control inputs.
When they are "L", a write enable status is provided.
WRES x
RCK x
They are write reset inputs to initialize a write address
counter of internal FIFO.
When they are "L", a write reset status is provided.
They are read clock inputs.
3
RE x
3
They are read enable control inputs.
When they are "L", a read enable status is provided.
RRES x
Dx <7:0>
Qx <7:0>
3
They are read reset inputs to initialize a read address
counter of internal FIFO.
When they are "L", a read reset status is provided.
They are 8-bit input data bus.
24
24
3
Data output
They are 8-bit output data bus.
MODE<3:1> Mode setting input
They are operation mode setting inputs.
For setting, refer to Mode setting table of Page5.
TEST<3:1>
Test setting input
3
They are test setting inputs.
Setting of TEST1 depends on the rising time of the 1.8 V
system power supply. For further details, refer to page 12.
TEST2 and TEST3 should be fixed at "L".
This is a 3.3 V power supply pin for I/O.
VccIO
Vcc18
GND
Power supply pin for
I/O
-
-
-
9
5
Power supply pin for
internal circuit
Ground pin
This is a 1.8 V power supply pin for internal circuit.
This is a ground pin.
14
Note: X of the pin name shows A, B and C.
A = A-system, B = B-system, C = C-system.
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 4 of 23
M66288FP
Mode Setting
MODE<3:1> should be set to “L” or “H” as shown below to select the 8 operation modes.
MODE 3
MODE 2
MODE 1
Operation mode
MODE 1
L
L
L
L
L
H
L
MODE 2
L
H
H
L
MODE 3
L
H
L
MODE 4
H
H
H
H
MODE 5
L
H
L
MODE 6
H
H
MODE 7
H
MODE 8
Mode1 Operation Description
<Mode 1>
8
8
8
8
8
8
DA<7:0>
WCKA
WRESA
WEA
QA<7:0>
RCKA
RRESA
REA
In mode 1, three pieces of 256K-word x 8-bit FIFO can be controlled completely
independently. Taking FIFO (A) as an example, the operation of FIFO memory is
described below. The operation of FIFO (B) and FIFO (C) are the same as that of
FIFO (A).
256K-w
x
8-bit
FIFO(A)
DB<7:0>
WCKB
WRESB
WEB
QB<7:0>
RCKB
RRESB
REB
256K-w
x
When write enable input WEA is "L", the contents of data input DA<7:0> are
written into FIFO (A) in synchronization with the rising of write clock input WCKA.
At this time, the write address counter of FIFO (A) is incremented.
When WEA is "H", this IC disable to write data into FIFO (A) and the write address
counter of FIFO (A) is not incremented.
8-bit
FIFO(B)
DC<7:0>
WCKC
WRESC
WEC
QC<7:0>
RCKC
RRESC
REC
256K-w
x
8-bit
When write reset input WRESA is "L", the write address counter of FIFO (A) is
initialized.
FIFO(C)
When read enable input REA is "L", the contents of FIFO (A) are outputted to data
output QA<7:0> in synchronization with the rising of read clock input RCKA.
At this time, the read address counter of FIFO (A) is incremented.
When REA is "H", this IC disable to read data from FIFO (A) and the read address
counter of FIFO (A) is not incremented. Also QA<7:0> become high impedance
state.
When read reset input RRESA is "L", the read address counter of FIFO (A) is
initialized.
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 5 of 23
M66288FP
Mode2 Operation Description
<Mode 2>
In mode 2, three pieces of 256K-word x 8-bit FIFO are cascade-connected
and it is possible to generate delay data for 3-lines without external wiring.
When write enable input WEA is "L", the contents of data input DA<7:0> are
written into FIFO (A) in synchronization with the rising of write clock input
WCKA. At this time, the write address counter of FIFO (A) is incremented.
When WEA is "H", this IC disable to write data into FIFO (A) and the write
address counter of FIFO (A) is not incremented.
When write reset input WRESA is "L", the write address counter of FIFO (A)
is initialized.
When read enable input REA is "L", the contents of FIFO (A), FIFO (B) and
FIFO (C) are outputted to each QA<7:0>, QB<7:0>, QC<7:0> in synchroni-
zation with the rising of read clock input RCKA. At this time, the read address
counters of all FIFOs are incremented.
Also the data of the upper FIFO is written into the lower FIFO in synchroniz-
ation with the rising of RCKA. At this time, the write address counters of
FIFO (B) and FIFO (C) are incremented simultaneously.
When REA is "H", this IC disable to read data from FIFO (A), FIFO (B) and
FIFO (C) and the read address counter of each FIFO is not incremented.
All data outputs become high impedance state. And this IC also disable to
write data into FIFO (B) and FIFO (C) and the write address counter of
FIFO (B) and FIFO (C) is not incremented.
When read reset input RRESA is "L", the read address counter of FIFO (A)
and the write/read address counters of FIFO (B) and FIFO (C) are initialized.
In mode 2, only all pins for the A-system, QB<7:0> and QC<7:0> are used.
Therefore, the write/read control pins for the B/C-system, DB<7:0> and
DC<7:0> should be fixed at "L" or "H".
Note: Write and read operation of FIFO (B) and FIFO (C) after the 2nd line is controlled by the read system pin of
the 1st line FIFO (A).
Maximum number of words on this mode is 256K-word.
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 6 of 23
M66288FP
Mode3 Operation Description
<Mode 3>
8
8
In mode 3, two pieces of 256K-word x 8-bit FIFO are cascade-connected and
the other FIFO is configured completely independently.
This makes it possible to generate delay data for 2-lines without external
wiring and to control the other independent one FIFO memory.
DA<7:0>
WCKA
WRESA
WEA
QA<7:0>
RCKA
RRESA
REA
256K-w
x
8-bit
FIFO(A)
8
8
When write enable input WEA is "L", the contents of data input DA<7:0> are
written into FIFO (A) in synchronization with the rising of write clock input
WCKA. At this time, the write address counter of FIFO (A) is incremented.
When WEA is "H", this IC disable to write data into FIFO (A) and the write
address counter of FIFO (A) is not incremented.
QB<7:0>
256K-w
x
8-bit
FIFO(B)
When write reset input WRESA is "L", the write address counter of FIFO (A) is
initialized.
8
8
QC<7:0>
RCKC
RRESC
REC
DC<7:0>
WCKC
WRESC
WEC
256K-w
x
8-bit
FIFO(C)
When read enable input REA is "L", the contents of FIFO (A) and FIFO (B) are
outputted to each QA<7:0> and QB<7:0> in synchronization with the rising of
read clock input RCKA. At this time, the read address counters of FIFO (A)
and FIFO (B) are incremented.
Also the data of FIFO (A) is written into FIFO (B) in synchronization with the
rising of RCKA. At this time, the write address counter of FIFO (B) is incre-
mented simultaneously.
When REA is "H", this IC disable to read data from FIFO (A) and FIFO (B)
and the read address counter of each FIFO is not incremented. QA<7:0>
and QB<7:0> become high impedance state. And this IC also disable to write
data into FIFO (B) and the write address counter of FIFO (B) is not incremen-
ted.
When read reset input RRESA is "L", the read address counter of FIFO (A)
and the write/read address counter of FIFO (B) are initialized.
The operation of FIFO (C) is the same as that of mode 1.
In mode 3, only all pins for the A/C-system and QB<7:0> are used. Therefore
the write/read control pins for the B-system and DB<7:0> should be fixed at
"L" or "H".
Note: Write and read operation of FIFO (B) at the 2nd line is controlled by the read system pin of the 1st line
FIFO (A).
Maximum number of words on this mode is 256K-word.
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 7 of 23
M66288FP
Mode4 Operation Description
<Mode 4>
12
12
DA<7:0>
DB<3:0>
QA<7:0>
QB<3:0>
In mode 4, two pieces of 256K-word x 12-bit FIFO can be controlled completely
independently. Taking FIFO (A) as an example, the operation of FIFO memory is
described below. The operation of FIFO (B) is the same as that of FIFO (A).
256K-w
x
12-bit
FIFO(A)
WCKA
WRESA
WEA
RCKA
RRESA
REA
When write enable input WEA is "L", the contents of data input DA<7:0> and
DB<3:0> are written into FIFO (A) in synchronization with the rising of write clock
input WCKA. At this time, the write address counter of FIFO (A) is incremented.
When WEA is "H", this IC disable to write data into FIFO(A) and the write address
counter of FIFO (A) is not incremented.
12
12
DC<7:0>
DB<7:4>
QC<7:0>
QB<7:4>
256K-w
x
12-bit
FIFO(B)
WCKB
WRESB
WEB
RCKB
RRESB
REB
When write reset input WRESA is "L", the write address counter of FIFO (A) is
initialized.
When read enable input REA is "L", the contents of FIFO (A) are outputted to data
output QA<7:0> and QB<3:0> in synchronization with the rising of read clock
input RCKA. At this time, the read address counter of FIFO (A) is incremented.
When REA is "H", this IC disable to read data from FIFO (A) and the read address
counter of FIFO (A) is not incremented. Also QA<7:0> and QB<3:0> become high
impedance state.
When read reset input RRESA is "L", the read address counter of FIFO (A) is
initialized.
Also, set the 12-bit I/O buses of FIFO (A) and FIFO (B) as shown in the table
below. In mode 4, only all pins for the A/B-system, DC<7:0> and QC<7:0> are
used. Therefore the write/read control pins for the C-system should be fixed at "L"
or "H".
External pin Data input
External pin Data output
External pin Data input
External pin Data output
name
bus of FIFO name
(A)
bus of FIFO
(A)
name
bus of FIFO Name
(B)
bus of FIFO
(B)
DA<7>
DA<6>
DA<5>
DA<4>
DA<3>
DA<2>
DA<1>
DA<0>
DB<3>
DB<2>
DB<1>
DB<0>
11th-bit
10th-bit
9th-bit
8th-bit
7th-bit
6th-bit
5th-bit
4th-bit
3rd-bit
2nd-bit
1st-bit
0th-bit
QA<7>
QA<6>
QA<5>
QA<4>
QA<3>
QA<2>
QA<1>
QA<0>
QB<3>
QB<2>
QB<1>
QB<0>
11th-bit
10th-bit
9th-bit
8th-bit
7th-bit
6th-bit
5th-bit
4th-bit
3rd-bit
2nd-bit
1st-bit
0th-bit
DC<7>
DC<6>
DC<5>
DC<4>
DC<3>
DC<2>
DC<1>
DC<0>
DB<7>
DB<6>
DB<5>
DB<4>
11th-bit
10th-bit
9th-bit
8th-bit
7th-bit
6th-bit
5th-bit
4th-bit
3rd-bit
2nd-bit
1st-bit
0th-bit
QC<7>
QC<6>
QC<5>
QC<4>
QC<3>
QC<2>
QC<1>
QC<0>
QB<7>
QB<6>
QB<5>
QB<4>
11th-bit
10th-bit
9th-bit
8th-bit
7th-bit
6th-bit
5th-bit
4th-bit
3rd-bit
2nd-bit
1st-bit
0th-bit
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 8 of 23
M66288FP
Mode5 Operation Description
<Mode 5>
12
12
DA<7:0>
DB<3:0>
QA<7:0>
QB<3:0>
In mode 5, two pieces of 256K-word x 12-bit FIFO are cascade-connected
and it is possible to generate delay data for 2-lines without external wiring.
256K-w
x
12-bit
FIFO(A)
WCKA
WRESA
WEA
RCKA
RRESA
REA
When write enable input WEA is "L", the contents of data input DA<7:0> and
DB<3:0> are written into FIFO (A) in synchronization with the rising of write
clock input WCKA. At this time, the write address counter of FIFO (A) is
incremented.
12
12
QC<7:0>
QB<7:4>
When WEA is "H", this IC disable to write data into FIFO (A) and the write
address counter of FIFO (A) is not incremented.
256K-w
x
12-bit
FIFO(B)
When write reset input WRESA is "L", the write address counter of FIFO (A) is
initialized.
When read enable input REA is "L", the contents of FIFO (A) and FIFO (B) are
outputted to each QA<7:0>, QB<3:0> and QC<7:0>,QB<7:4> in synchroniza-
tion with the rising of read clock input RCKA. At this time, the read address
counters of FIFO (A) and FIFO (B) are incremented.
Also the data of FIFO (A) is written into FIFO (B) in synchronization with the
rising of RCKA. At this time, the write address counter of FIFO (B) is
incremented simultaneously.
When REA is "H", this IC disable to read data from FIFO (A) and FIFO (B) and
the read address counter of each FIFO is not incremented.
Also all data outputs become high impedance state. And this IC also disable to
write data into FIFO (B) and the write address counter of FIFO (B) is not incre-
mented.
When read reset input RRESA is "L", the read address counter of FIFO (A)
and the write /read address counter of FIFO (B) are initialized.
Also, set the 12-bit I/O buses of FIFO (A) and FIFO (B) as shown in the table
below. In mode 5, only all pins for the A-system, DB<3:0>, QB<7:0> and
QC<7:0> are used. Therefore the write/read control pins for the B/C-system,
DB<7:4> and DC<7:0> should be fixed at "L" or "H".
External pin Data input
External pin Data output
External pin Data output
Name
bus of FIFO name
(A)
bus of FIFO
(A)
Name
bus of FIFO
(B)
DA<7>
DA<6>
DA<5>
DA<4>
DA<3>
DA<2>
DA<1>
DA<0>
DB<3>
DB<2>
DB<1>
DB<0>
11th-bit
10th-bit
9th-bit
8th-bit
7th-bit
6th-bit
5th-bit
4th-bit
3rd-bit
2nd-bit
1st-bit
0th-bit
QA<7>
QA<6>
QA<5>
QA<4>
QA<3>
QA<2>
QA<1>
QA<0>
QB<3>
QB<2>
QB<1>
QB<0>
11th-bit
10th-bit
9th-bit
8th-bit
7th-bit
6th-bit
5th-bit
4th-bit
3rd-bit
2nd-bit
1st-bit
0th-bit
QC<7>
QC<6>
QC<5>
QC<4>
QC<3>
QC<2>
QC<1>
QC<0>
QB<7>
QB<6>
QB<5>
QB<4>
11th-bit
10th-bit
9th-bit
8th-bit
7th-bit
6th-bit
5th-bit
4th-bit
3rd-bit
2nd-bit
1st-bit
0th-bit
Note: Write and read operation of FIFO(B) at the 2nd line is controlled by the read system pin of the 1st line FIFO(A).
Maximum number of words on this mode is 256K-word.
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 9 of 23
M66288FP
Mode6 Operation Description
<Mode 6>
In mode 6, one FIFO memory of the 768K-word x 8-bit composition can be
controlled.
8
8
DA<7:0>
WCKA
WRESA
WEA
QA<7:0>
RCKA
RRESA
REA
768K-w
x
The operation of FIFO (A) is the same as that of mode 1.
In mode 6, only all pins for the A-system are used. Therefore, the all input pins for
8-bit
FIFO(A)
the B/C-system should be fixed at "L" or "H".
Also QB<7:0> and QC<7:0> become high impedance state.
Mode7 Operation Description
<Mode 7>
8
8
In mode 7, one of 512K-word x 8-bit FIFO and one of 256K-word x 8-bit FIFO
memory can be controlled completely independently.
DA<7:0>
QA<7:0>
512K-w
x
WCKA
WRESA
WEA
RCKA
RRESA
REA
8-bit
The operation of FIFO (A) and FIFO (B) are the same as that of mode 1.
In mode 7, only all pins for the A/C-system are used. Therefore, the all input pins
FIFO(A)
for the B-system should be fixed at "L" or "H".
Also QB<7:0> become high impedance state.
8
8
DC<7:0>
WCKC
WRESC
WEC
QC<7:0>
RCKC
RRESC
REC
256K-w
x
8-bit
FIFO(B)
Mode8 Operation Description
<Mode 8>
12
12
DA<7:0>
DB<3:0>
QA<7:0>
QB<3:0>
In mode 8, one FIFO memory of the 512K-word x 12-bit composition can be
controlled.
512K-w
x
12-bit
FIFO(A)
WCKA
WRESA
WEA
RCKA
RRESA
REA
The operation of FIFO (A) is the same as that of mode 4.
Also, please set the 12-bit I/O buses of FIFO (A) as mentioned in the table of mode
4 FIFO (A).
In mode 8, only all pins for the A-system, DB<3:0> and QB<3:0> are used.
Therefore, the write/read control pins for the B/C-system, DB<7:4> and DC<7:0>
should be fixed at "L" or "H".
Also QB<7:4> and QC<7:0> become high impedance state.
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 10 of 23
M66288FP
Electrical Characteristics
Absolute Maximum Ratings (Ta = 0 ~ 70°C, unless otherwise noted)
Symbol
Parameter
Supply voltage
Conditions
Ratings
-0.3~+2.5
Unit
VCC18
A value based on GND
V
(1.8 V power supply )
Supply voltage
VCCIO
-0.3~+3.8
V
(3.3 V power supply )
Input voltage
VI
-0.3~VCCIO+0.3
-0.3~VCCIO+0.3
800
V
VO
Pd
Output voltage
V
Maximum power dissipation
Storage temperature
Ta = 70 °C
mW
°C
Tstg
-55~150
Recommended Operating Conditions
Symbol
Parameter
Test conditions
Limits
Unit
V
Min.
1.62
Typ.
1.8
Max.
VCC18
Supply voltage for internal circuit
(1.8 V power supply )
A value based on GND
1.98
VCCIO
Topr
Supply voltage for I/O
(3.3 V power supply )
3.0
0
3.3
3.6
70
V
Operating ambient temperature
°C
DC Characteristics (Ta = 0 ~ 70°C, Vcc18 = 1.8 ± 0.18 V, VccIO = 3.3 ± 0.3 V, GND = 0 V, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Typ.
Unit
V
Min.
0.8 x
Max.
VIH
"H" input voltage
A value based on GND
VccIO
VIL
"L" input voltage
0.2
x
V
VccIO
VOH
"H" output voltage
IOH = -4mA
VccIO
- 0.4
V
VOL
IIH
"L" output voltage
IOL = 4mA
0.4
10
V
"H" input current
VI = VCCIO
µA
µA
µA
µA
mA
IIL
"L" input current
VI = GND
-10
10
IOZH
IOZL
ICC18
Off state "H" output current
Off state "L" output current
Average operating supply current
(1.8 V)
VO = VCCIO
VO = GND
-10
180
VCC18 = 1.8 V ± 0.18 V
VCCIO = 3.3 V ± 0.3 V
VI = repeat "H" and "L"
VO= Output open
tWCK = tRCK = 12.5 ns
f = 1 MHz
ICCIO
Average operating supply current
(3.3 V)
120
mA
CI
Input capacitance
10
15
pF
pF
CO
Off state output capacitance
f = 1 MHz
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 11 of 23
M66288FP
Power - on
After power-on, this IC initializes some circuits of internal FIFO (1.8 V), using the built-in power-on reset circuit.
This power-on reset is performed by using the VCC18 = 1.8 V system power supply.
Either of the following conditions (1) or (2) should be met according to the power-on time of the VCC18.
(1) When the power-on time of the VCC18 is 1 msec or less:
Some circuits of internal FIFO are initialized by the built-in power-on reset circuit. No restriction is imposed on the
power-on sequence between VCC18 and VCCIO = 3.3 V system power supply. When powering on again after power-on,
provide an interval of 100 ms or more for the VCC18. At this time, the TEST1 (pin 99) pin should be fixed at "L".
1ms(max)
100ms(min)
Vcc18
Vcc18
Vcc18 X 10%
Vcc18 X 10%
GND
(2) When the power-on time of the VCC18 is more than 1 msec:
Some circuits of internal FIFO should be initialized by the TEST1 (pin 99) pin.
Input an initialize reset pulse of 200 ns or more after the power supplies (VCCIO, VCC18) reach to the VCC level.
There is no problem even if reaching to the VCC level on which power supply.
3.0V~3.6V
VccIO
3.0V~3.6V
VccIO
GND
GND
GND
1ms or more
1.62V~1.98V
Vcc18
Vcc18
VccIO
200ns(min)
200ns(min)
TEST1
Note: Some circuits of internal FIFO can be initialized by the TEST1 pin even if the power-on time of the Vcc18 is
1 msec or less.
Note: Important matter;
Provide write reset cycles and read reset cycles of 100 cycles or more, respectively after the Vcc reaches
to the specified voltage after power-on.
When inputting a reset pulse using the TEST1 (pin 99) pin, provide write reset cycles and read reset cycles
of 100 cycles or more, respectively after inputting a reset pulse at power-on.
There is no problem in this reset operation if a total of 100 cycles or more is achieved, even if
discontinuous reset input is made.
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 12 of 23
M66288FP
Timing Requirements
(Ta = 0 ~ 70°C, Vcc18 = 1.8 ± 0.18 V, VccIO = 3.3 ± 0.3 V, GND = 0 V, unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min. Typ. Max.
t WCK
Write clock (WCK) cycle
12.5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t WCKH
t WCKL
t RCK
Write clock (WCK) "H" pulse width
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
5
12.5
5
t RCKH
t RCKL
t DS
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
Input data setup time to WCK
5
3.5
1
t DH
Input data hold time to WCK
t RESS
t RESH
t NRESS
t NRESH
t WES
t WEH
t NWES
t NWEH
t RES
Reset setup time to WCK or RCK
Reset hold time to WCK or RCK
Reset non-select setup time to WCK or RCK
Reset non-select hold time to WCK or RCK
Write enable setup time to WCK
Write enable hold time to WCK
Write enable non-select setup time to WCK
Write enable non-select hold time to WCK
Read enable setup time to RCK
Read enable hold time to RCK
Read enable non-select setup time to RCK
Read enable non-select hold time to RCK
Input pulse rise / fall time
3.5
1
3.5
1
3.5
1
3.5
1
3.5
1
t REH
t NRES
t NREH
t r, t f
3.5
1
3
Switching Characteristics
(Ta = 0 ~ 70°C, Vcc18 = 1.8 ± 0.18 V, VccIO = 3.3 ± 0.3 V, GND = 0 V, unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min. Typ. Max.
t AC
Output access time to RCK
Output hold time to RCK
Output enable time to RCK
Output disable time to RCK
9
ns
ns
ns
ns
t OH
2
t OEN
t ODIS
2
2
9
9
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 13 of 23
M66288FP
Switching Characteristics Measurement Circuit
Vcc IO
RL = 1 KΩ
SW1
SW2
Qn
Qn
CL = 10 pF: tAC, tOH
CL = 3 pF: tOEN, tODIS
RL = 1 KΩ
Parameter
tODIS (LZ)
SW1
SW2
Close
Open
Close
Open
Open
tODIS (HZ)
tOEN (ZL)
Close
Open
Close
tOEN (ZH)
Input pulse level
: 0 ~ VCCIO
Input pulse rise/fall time : 1 ns
Decision voltage input : 1/2 VCCIO
Decision voltage output : 1/2 VCCIO (However, tODIS (LZ) is 10% of output amplitude and tODIS (HZ) is 90%
of that for decision).
The load capacitance CL includes the floating capacitance of connection and the input capacitance of probe.
tODIS and tOEN Measurement Condition
VIH
1/2 VccIO
1/2 VccIO
RCK
VIL
VIH
VIL
RE
Qn
tODIS(HZ)
tODIS(LZ)
tOEN(ZH)
tOEN(ZL)
VOH
90%
1/2 VccIO
1/2 VccIO
Qn
10%
VOL
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 14 of 23
M66288FP
Operating Timing
z Write Cycle
n+4 cycle
n+3 cycle
n cycle
n+1 cycle
n+2 cycle
Disable cycle
WCK
tWCK
tWCKH tWCKL tWEH tNWES
tNWEH tWES
WE
tDS tDH
tDS tDH
Dn
(n)
(n+1)
(n+2)
(n+3)
(n+4)
WRES = "H"
z Write Reset Cycle
n-1 cycle
n cycle
0 cycle
1 cycle
Reset cycle
WCK
tWCK
tNRESH tRESS
tRESH tNRESS
WRES
tDS tDH
tDS tDH
Dn
(n-1)
(n)
(0)
(1)
In case of WE = "L"
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 15 of 23
M66288FP
z Combination Cycle of Write Reset and Write Enable
n+1 cycle
n+2 cycle
Disable cycle
0 cycle
1 cycle
n cycle
tWCK
WCK
tWCKH tWCKL tWEH tNWES
tNWEH tWES
WE
tNRESH tRESS tRESH tNRESS
WRES
tDS tDH
tDS tDH
Dn
(n)
(n+1)
(n+2)
(0)
(1)
Note: There are no restrictions of WE to WRES.
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 16 of 23
M66288FP
z Read Cycle
n cycle
tRCK
n+1 cycle
n+2 cycle
n+3 cycle
n+4 cycle
Disable cycle
RCK
tNREH tRES
tRCKH tRCKL tREH tNRES
RE
Qn
tODIS
tOEN
tAC
HIGH-Z
(n)
(n+1)
(n+2)
(n+3)
(n+4)
tOH
tOH
RRES = "H"
z Read Reset Cycle
n cycle
n-1 cycle
Reset cycle
0 cycle
1 cycle
RCK
tRCK
tNRESH tRESS
tRESH tNRESS
RRES
tAC
tAC
tAC
Qn
(n-1)
(n)
(0)
(1)
tOH
tOH
tOH
In case of RE = "L"
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 17 of 23
M66288FP
z Combination Cycle of Read Reset and Read Enable
n cycle
tRCK
n+1 cycle
n+2 cycle
0 cycle
1 cycle
Disable cycle
RCK
RE
tRCKH tRCKL tREH tNRES
tNREH tRES
tNRESH tRESS tRESH tNRESS
RRES
Qn
tOEN
tAC
tAC
tAC
tODIS
HIGH-Z
(n)
(n+1)
(n+2)
(0)
(1)
tOH
tOH
tOH
Note: There are no restrictions of RE to RRES.
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 18 of 23
M66288FP
Attentions when Write Cycle and Read Cycle Approach Each Other
The interval m of 16 cycles or more between a write cycle and a read cycle should be secured, when the write cycle goes
ahead of the read cycle on the following conditions, that is to say the interval less than 15 cycles is forbidden.
WRES, RRES="H"; WE, RE="L", and
●Both write side and read side are activated continuously
●Either write side or read side is temporarily stopped owing to the stop of WCK or RCK
When this restriction to the interval is broken on these conditions, writing data is guaranteed, but reading data isn’t
guaranteed not only during breaking it but also during the following 16 cycles after it is applied. In this 16 cycles, read
disable and read reset cycles are not counted.
But the following condition is an exception to restrict to forbid the intervals less than 15 cycles.
●Either write side or read side is temporarily stopped owing to reset cycles (WRES or RRES="L") or disable cycles
(WE or RE ="H")
Note: Also, when the address counter is incremented up to the last cycle of 1-line and then returned to 0 cycle, the
interval m of 16 cycles or more between a write and read cycles should be secured, taking account that
they are cyclic and serial lines.
Write disable cycle
n+18 cycle n+19 cycle n+20 cycle n+21 cycle
n+23 cycle
n+22 cycle
n+17 cycle
n+16 cycle
WCK
WE
Dn
( n+17 )
( n+18 )
( n+19 )
( n+21 )
( n+23 )
( n+16 )
( n+20 )
( n+22 )
m≦15; WRES,RRES=H;
WE,RE=L
"m", the interval
between
a write cycle
⑯
⑯
⑮
⑭
⑭
⑭
⑮
⑯
⑯
⑯
and a read cycle
n cycle
n+1 cycle
n+2 cycle n+3 cycle
n+5 cycle
Read disable cycle
n+7 cycle
n+4 cycle
n+6 cycle
RCK
RE
HIGH-Z
( n+2 )
invalid
( n )
( n+1 )
( n+3 )
invalid
Qn
read data of 16 cycles
after forbidden cycles
are undefined.
read data of
forbidden cycles
are undefined.
read data are defined
owing to write disable
cycle.
The conditions that the read cycle goes ahead of the write cycle or that write cycle and read cycle are accordant, are
exceptions to the restriction to forbid the intervals less than 15cycles.
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 19 of 23
M66288FP
Variable Length Delay Bits
The 1-line length (cycle number) of each mode is shown in the table.
Operation MODE
MODE 1 - MODE 5
MODE 6
1-line length
262144-cycle
786432-cycle
MODE 7
MODE 8
524288-cycle (A-system), 262144-cycle (C-system)
524288-cycle
The following, the case of the MODE 1 - MODE 5 (1-line length = 262144-cycle) is explained to an example.
1-line (262144-bit) Delay
In read cycles, an output data is read at the (first) rising edge of RCK (i.e. the start of the cycle ) . In write cycles, an input
data is written at the (second) rising edge of WCK (i.e. the end of the cycle ) . So 1-line delay can be made easily according
to the control method of the following figure.
262144
cycle
(0’)
262142
cycle
262143
cycle
262145
cycle
(1’)
262146
cycle
0 cycle
1 cycle
2 cycle
Reset cycle
(2’)
WCK
RCK
tRESS tRESH
WRES
RRES
tDS tDH
tDS tDH
(262141)
(262142)
(262143)
(0)
(1)
(2)
(0’)
(1’)
(2’)
Dn
Qn
tOH
tAC
262144 cycle
(0)
(1)
(2)
WE, RE = "L"
N-bit Delay 1
(Reset at a cycle corresponding to delay length)
Reset cycle
0 cycle
1 cycle
2 cycle
n cycle
Reset cycle
0 cycle
(0’)
1 cycle
(1’)
2 cycle
(2’)
WCK
RCK
tRESS tRESH
tRESS tRESH
WRES
RRES
tDS tDH
tDS tDH
(0)
(1)
(2)
(n-1)
(n)
(0’)
(1’)
(1)
(2’)
Dn
Qn
tAC
tOH
Delay length n
(0)
(2)
262144 ≥ n ≥ 16
WE, RE = "L"
Note: The interval of 16 cycles or more between a write cycle and a read cycle should be secured to read data
written in a certain cycle.
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 20 of 23
M66288FP
N-bit Delay 2
(Sliding timings of WRES and RRES at a cycle corresponding to delay length)
n+1 cycle
1 cycle
n-1 cycle
Reset cycle 0 cycle
n cycle
n+2 cycle
2 cycle
n+3 cycle
3 cycle
·····Write side
·····Read side
0 cycle
1 cycle
2 cycle
Reset cycle
WCK
RCK
tRESS tRESH
WRES
tRESS tRESH
tDS tDH
tDS tDH
RRES
Dn
(0)
(1)
(2)
(n-2)
(n-1)
(n)
(n+1)
(n+2)
(n+3)
tAC
tOH
Delay length n
(0)
(1)
(2)
(3)
Qn
262144 ≥ n ≥ 16
WE, RE = "L"
N-bit Delay 3
(Sliding address by disabling RE at a cycle corresponding to delay length)
n+1 cycle
1 cycle
n-1 cycle
n cycle
0 cycle
n+2 cycle
2 cycle
n+3 cycle
3 cycle
·····Write side
·····Read side
0 cycle
1 cycle
2 cycle
Reset cycle
WCK
RCK
tRESS tRESH
WRES
RRES
tNREH tRES
RE
tDS tDH
tDS tDH
(0)
(1)
(2)
(n-2)
(n-1)
(n)
(n+1)
(n+2)
(n+3)
Dn
tAC
tOH
Delay length n
HIGH-Z
(0)
(1)
(2)
(3)
Qn
262144 ≥ n ≥ 16
WE = "L"
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 21 of 23
M66288FP
Shortest Reading of Written Data in N Cycle when Write and Read Operated
Asynchronously
The interval of 16 cycles or more between a write cycle and a read cycle should be secured and WCK and RCK should be
inputted for 16 cycles or more based on beginning of write n cycle at any timing to read written data (data fetched at the
rising edge of WCK shown *1 in the following figure) with n cycles on write side.
On read side, n cycles should be started after the completion of n+15 cycles on write side (Δt ≥ 0 in the following figure).
Output data becomes undefined when these restrictions are not filled.
Reference
16 cycles or more are required in WCK.
n-1 cycle
n cycle
n+1 cycle
n+14 cycle
n+15 cycle n+16 cycle
n+17 cycle
n+18 cycle
n+19 cycle
WCK
Dn
*1
(n-1)
(n)
(n+1)
(n+14)
(n+15)
(n+16)
(n+17)
(n+18)
(n+19)
16 cycles or more are required in RCK.
n-1 cycle
Δ t ≥ 0
n cycle
n+1 cycle
RCK
Qn
invalid
(n)
(n+1)
Longest Reading of Written Data in N Cycle: 1-line Delay
Data output Qn of n cycle <1>* can be read immediately before until the start of n cycle <1>* on read side and the start of n
cycle <2>* on write side over lap each other.
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 22 of 23
M66288FP
PACKAGE OUTLINE
All trademarks and registered trademarks are the property of their respective owners.
REJ03F0156-0310 Rev.3.10 Apr.04.2008
Page 23 of 23
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