M66291GP_技术文档

M66291GP/HP

REJ03F0125-0101Z

Rev1.01

ASSP (USB2.0 Device Controller)

2004.11.01

1

Overview

The M66291 is a general purpose USB (Universal Serial Bus) device controller compliant with the USB

Specification Revision 2.0 and supports full speed transfer. The USB transceiver circuit is included, and the M66291

meets all transfer types which are defined in the USB specification. The M66291 has FIFO of 3 Kbytes for data

transfer and can set 7 endpoints (maximum). Each endpoint can be set programmable of its transfer condition, so can

correspond to each device class transfer system of USB.

1.1 Features

z USB Specification Revision 2.0 compliant

z Supports Full Speed (12 Mbps) transfer

z Built-in USB transceiver circuit

z Built-in oscillation buffer (Supports 6M/12M/24 MHz of oscillator) and PLL at 48 MHz

z Supports Vbus direct connection (5 V withstand voltage input), D+ pin pullup output

z Supports all transfer type which is defined in the USB specification.(Control transfer / Bulk transfer / Interrupt

transfer / Isochronous transfer)

z Low power consumption operation (Average 15 mA at operation)

z Robust against signal distortion on USB transfer line due to SIE/DPLL(Digital Phase Lock Loop) of the original

design

z Easy making enumeration program and timing design because hardware manages the device state / control

transfer state (transition timing)

z Reduction of CPU load due to continuous transmit/receive mode (the mode for buffering several transaction data

into FIFO) This enables high performance and throughput improvement.

z Up to 7 endpoints (EP0 to EP6) selectable

z Data transfer condition selectable for each endpoint (EP1 to EP6)

Compatible to various applications (device class)

• Data transfer type

• Transfer direction

• Packet size

(Bulk transfer / Isochronous transfer / Interrupt transfer)

(IN, OUT)

z Built-in FIFO buffer (3 Kbytes) for endpoints

z Buffering conditions of FIFO memory settable per endpoint (EP1 to EP6)

• FIFO buffer size (up to 1Kbyte)

• Presence/Absence of double buffer configuration (setting of buffer size x 2)

z Four pieces of configurable FIFO ports

• Endpoint number allocation

• Access method switching (CPU, DMAC)

• Bit width (8-bit / 16-bit)

• Endian switching

z ”Interrupt queuing function” that eliminates the need of complicated factor analysis

z Connectable to various CPU/DMAC

• Bus width(8-bit / 16-bit)

• Interface voltage(2.7V to 5.5V)

• Interrupt signal and DMA control signal polarities settable

• Supports multi-word DMA (burst)

z FIFO access cycle of maximum 24 Mbytes/sec

Applications

Support all PC peripheral built-in USB

Rev1.01 2004.11.01 page 1 of 122

M66291GP/HP

PINCONFIGURATION

(TOPVIEW)

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

D1

D0

A6

A5

A4

A3

A2

A1

D12/P4

D13/P5

D14/P6

D15/A0

DATA BUS

DATA

BUS

HIGH-WRITE STROBE/BUS WIDTH SELECT HWR/BYTE

ADDRESS BUS

INTERRUPT 0

READ STROBE

INT0

RD

M66291GP

LOW-WRITE STROBE

CHIP SELECT

LWR

CS

CoreVcc

GND

CORE POWER SUPPLY

RESET

RST

Xin

OSCILLATION INPUT

DMA REQUEST 0

DMA ACKNOWLEDGE 0

Dreq0

Dack0

Xout

OSCILLATION OUTPUT

Outline

M66291GP: 48P6Q-

A(LQFP)

Figure 1.1-1 M66291GP Pin Configuration

Rev1.01 2004.11.01 page 2 of 122

M66291GP/HP

PINCONFIGURATION

(TOPVIEW)

D12/P4

D13/P5

D14/P6

D15/A0

HWR/BYTE

INT0

40

41

42

43

44

45

46

47

48

49

50

51

52

26

25

24

23

22

21

20

19

18

17

16

15

14

D1

D0

A6

A5

A4

A3

M66291HP

RD

A2

LWR

A1

CS

CoreVcc

GND

Xin

Xout

NC

RST

Dreq0

Dack0

NC

Outline

M66291HP:52PJV(VQFN)

Figure1.1-2 M66291HP Pin Configuration

Rev1.01 2004.11.01 page 3 of 122

M66291GP/HP

1.2 Block Diagram

The M66291 contains an USB-IP block, an I/O block, a bus interface unit (BIU), and a FIFO memory.

I/O Block

USB-IP

Bus Interface Pins

•A1-6

Bus

Interface

Unit

(Oscillator)

CPU Interface Register

Interrupt Controller

•D0-7

•Xin

•Xout

Oscillation

Buffer

/48MHzPLL

•D8-15

•CS

(BIU)

•RD

•LWR

•HWR

(USB Power Supply)

•Vbus

(Pullup Resistance)

•TrON

Vbus

Input Circuit

D+ Pin Pullup

Circuit

Interrupt Pins

•INT0

•INT1/SOF

Endpoint

Controller

Transfer

Controller

(USB Data)

•D+

DMA Control Pins

•Dreq0

Serial Interface

Engine

USB

Transceiver

•D-

FIFO Memory Controller

•Dack0

•Dreq1

(SIE)

•Dack1

•TC1

Reset Pins

•RST

FIFO Memory

Test Pins

•TEST

Figure 1.2 M66291 Block Diagram

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M66291GP/HP

1.2.1 USB-IP

The USB-IP block contains a serial interface engine, a transfer controller, an endpoint controller, a FIFO

memory controller, an interrupt controller, and a CPU interface register.

(1) Serial Interface Engine (SIE)

The serial interface engine (SIE) executes low-order protocols processing of USB as follows:

•

Extracts receive data/clock and generates transmit clock

Serial - parallel conversion of transmit/receive data

NRZI (Non Return Zero Invert) encoding and decoding

Bit stuffing and destuffing

SYNC (Synchronization pattern) and EOP (End Of Packet) detection

USB address and endpoint detection

CRC (Cyclic Redundancy Check) generation and checking

(2) Transfer Controller

The transfer controller executes device state transition control and control transfer sequence control.

(3) Endpoint Controller

The endpoint controller executes status control per endpoint.

(4) FIFO Memory Controller

The FIFO memory controller controls the write/read of the transmit/receive data at SIE (USB bus) side and

internal bus (CPU bus) side under state control by the endpoint controller.

(5) Interrupt Controller

The interrupt controller outputs the status signals outputted by transfer controller and endpoint controller to

INT0, INT1/SOF interrupt pins according to the CPU interface register setting.

(6) CPU Interface Register

The CPU interface register block is composed of the registers for mode setting, command setting and status

reading.

1.2.2 Bus Interface Unit (BIU)

The bus interface unit (BIU) is a circuit to conform USB-IP to LSI external bus.

1.2.3 FIFO Memory

The FIFO memory is a FIFO for endpoint transmit/receive. It is possible to set 6 endpoints EP1 to EP6 in

addition to EP0, the endpoint for control transfer.

1.2.4 I/O Block

The I/O block is composed of USB transceiver, oscillation buffer, 48 MHz PLL, Vbus input circuit and D+ pin

pullup control circuit.

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M66291GP/HP

(1) USB Transceiver

The USB transceiver, conforming to the USB Specification Revision 2.0, is composed of a pair of 2 pieces of

drivers D+/D- complying with full speed transfer mode, a pair of 2 pieces of single end receivers and a

differential input receiver. A serial resistance for impedance matching is needed external to the chip.

(2) Oscillation Buffer, 48 MHz PLL

The 48 MHz clock with accuracy ± 0.25% is needed at the USB-IP block. The M66291 has a built-in oscillation

buffer and a 48 MHz PLL. The PLL is capable of setting the multiplication number depending on the program

and can therefore be connected with an external oscillation of 6, 12 or 24 MHz. Further, it can also be operated

by the external 48 MHz clock without using the PLL function.

(3) Vbus Input Circuit, D+ Pin Pullup Control Circuit

The M66291 is capable of learning the connection status with host/hub by means of Vbus pin, and can inform

the state of preparation at device side to host/hub by turning on/off the 1.5 KΩ D+ pin pullup.

The Vbus input buffer which is 5 V tolerant can be directly connected to the Vbus pin on the USB bus.

The current from TrON pin is supplied by Vbus input. Since the D+/D- pins of USB bus are operated at 0 V to

3.3 V, the TrON pin reduces the voltage to 3.3 V before output.

Since the USB is constantly pulled down by 15 KΩ at host/hub side when connected electrically, a current of 0.2

mA continuously flows into the D+ pin through the pullup resistance.

Rev1.01 2004.11.01 page 6 of 122

M66291GP/HP

1.3 Pin Functions

Item

Pin name

Input/

Output

Input/

Function

Count

8

Bus

D7~D0

Data Bus

interface

Output This is a data bus to access the register from the system bus.

Input/ Data Bus / Port Signal

D14/P6~

D8/P0

7

1

Output P6 to P0 are used as port signals when selected to 8-bit bus interface.

D14 to D8 are used as data signals when selected to 16-bit bus interface.

D15/A0

Input/

D15 Signal / A0 Signal

Output A0 (LSB) is used as an address signal when selected to 8-bit bus interface.

D15 (MSB) is used as an data signal when selected to 16-bit bus interface.

A6~A1

*CS

Input

Address Bus

6

1

This is an address bus to access the register from the system bus.

Chip Select

"L" level enables communication with the M66291.

Low-write Strobe

*LWR

The lower data (D7 to D0) is written to the register at “L” level.

High-write Strobe / Bus Width Select

*HWR/*BYTE Input

With the reset signal set to “H” level, the 8-bit bus interface is selected if this

pin is at “L” level. Further, if this pin is at “H” level, the 16-bit bus interface is

selected. When the 16-bit bus interface is selected, the upper data (D15 to

D8) is written to the register at “L” level.

Fix to “L” level when set to 8-bit bus interface.

Read Strobe

*RD

Input

1

Data are read from registers at "L" level

Interrupt

interface

*INT0

Output Interrupt 0

Interrupts are requested to the system at "L" level.

Output Interrupt 1 / SOF Output

This pin is used as an interrupt 1 or as a SOF output pin to transmit USB SOF

signal according to register setting.

Output DMA Request 0

(Note 1)

*INT1/*SOF

(Note 1)

DMA

*Dreq0

(Note 1)

*Dack0

(Note 1)

*Dreq1

(Note 1)

1

interface

This pin is used to request DMA transfer to endpoint FIFO for DMA channel 0.

DMA Acknowledge 0

Input

This pin enables access of FIFO by DMA transfer for DMA channel 0.

Output DMA Request 1

This pin is used to request DMA transfer to endpoint FIFO for DMA channel 1.

Rev1.01 2004.11.01 page 7 of 122

M66291GP/HP

Item

Pin Name

Input/

Output

Input

Function

Count

1

DMA

*Dack1

(Note1)

*TC1

DMA Acknowledge 1

interface

This pin enables access of FIFO by DMA transfer for DMA channel 1.

Terminal Count 1

Input

1

This pin indicates the final transfer cycle at “L” level for DMA channel 1.

This is valid only in write cycle. Set to “H” level when not used.

USB Data (+)

USB

D+

Input/

1

interface

Output D+ of USB. Connect an external resistance in series.

Input/ USB Data (-)

Output D- of USB. Connect an external resistance in series.

D-

Vbus

Input

Vbus Input (with built-in pulldown resistance)

Connect to the Vbus of USB bus or to the 5V power supply.

Connection or shutdown of the Vbus can be detected.

TrON

*RST

Xin

Output TrON Output

This pin is connected to the D+ pullup resistance of 1.5 KΩ.

1

This pin is used to control ON/OFF of the pullup resistance.

Others

Input

Reset

This pin is used to initialize the values of the internal register or the counter at

"L" level.

Oscillator

Input

These pins are used to input/output the signals of internal clock

oscillation circuits. Connect a crystal unit between Xin and Xout

pins.

If an external clock signal is used, connect it to the Xin pin and

leave the Xout pin open.

Xout

Output Oscillator

1

2

Output

TEST

Input

TEST Input (with built-in pulldown resistance)

This pin is input for the test. Set to "L" level or keep open.

Core Power Supply

CoreVcc

(Note 2)

⎯

These pins are used as the power source for internal logic, FIFO memory, PLL

circuit, USB transceiver and oscillation buffer.

I/O Power Supply

IOVcc

(Note 3)

GND

⎯

2

3

Ground

A pin preceded by an asterisk "*" is an active low pin.

(Example: *CS pin is an active low, CS)

Note 1: The polarities of *Dreq, *Dack, *INT, and *SOF pins can be changed by the internal registers.

Note 2: The Xin, Xout, Vbus, D+ and D- pins are all driven by CoreVcc.

Note 3: The pins for bus interface, interrupt, DMA control, reset and test are all driven by IOVcc. See Figure 1.2.

Rev1.01 2004.11.01 page 8 of 122

M66291GP/HP

2

Registers

How to Read Register Tables

c

d

Bit Numbers :

Each register is connected with an internal bus of 16-bit wide, so the bit numbers of the

registers located at odd addresses are b15-b8, and those at even addresses are b7-b0.

State of Register at Reset :

Represents the initial state of each register immediately after reset with hexadecimal numbers.

The "H/W reset" is the reset by an external reset signal; the "S/W reset" is the reset by the

USBE bit of the USB Operation Enable Register.

e

f

At Read:

At Write:

{ ... Read enabled

? ... Read disabled (Read value invalid)

0 ... Read always as 0

1 ... Read always as 1

{ ... Write enabled

∆ ... Write enable conditionally (includes some conditions at write)

— ... Write disabled (Don’t care “0” and “1” at write)

X ··· Write disabled

Not implemented in the shaded portion.

b15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

b0

c

Abit Bbit Cbit

d H/W reset

S/W reset

USB bus reset

0

d

b

Bit name

Reserved.

A bit

Function

R

0

W

-

15

14

0: ------------------------

1: ------------------------

0: ------------------------

1: ------------------------

0: ------------------------

1: ------------------------

0

------------------------

(

)

13

12

B bit

------------------------

0

(

C bit

------------------------

(

e

f

Rev1.01 2004.11.01 page 9 of 122

M66291GP/HP

The M66291 register mapping is shown in Figure 2.1 and Figure 2.2, and each register is described below.

Address

+1 address

+0 address

Reset state

S/W

b15

b8 b7

b0

H/W

USB bus

H’00

H’02

H’04

H’06

H’08

H’0A

H’0C

H’0E

H’10

H’12

H’14

H’16

H’18

H’1A

H’1C

H’1E

H’20

H’22

H’24

H’26

H’28

H’2A

H’2C

H’2E

H’30

H’32

H’34

USB Operation Enable Register

Remote Wakeup Register

Sequence Bit Clear Register

(Reserved)

H'0000

-

H'0000

USB_Address Register

Isochronous Status Register

SOF Control Register

H'0000

H'0008

H'0000

-

H'0000

-

Polarity Set Register

-

Interrupt Enable Register 0

Interrupt Enable Register 1

Interrupt Enable Register 2

Interrupt Enable Register 3

Interrupt Status Register 0

Interrupt Status Register 1

Interrupt Status Register 2

Interrupt Status Register 3

Request Register

-

Note

-

Value Register

Index Register

Length Register

Control Transfer Control Register

EP0 Packet Size Register

Automatic Response Control Register

(Reserved)

-

EP0_FIFO Select Register

EP0_FIFO Control Register

EP0_FIFO Data Register

H'0000

H'0800

????

-

H’36 EP0_FIFO Continuous Transmit Data Length Register H'0000

Note : Refer to each register described below.

Figure 2.1 Register Mapping (1)

Rev1.01 2004.11.01 page 10 of 122

M66291GP/HP

Address

+1 address

+0 address

Reset state

S/W

b15

b8 b7

b0

H/W

USB bus

H’38

H’3A

H’3C

H’3E

H’40

H’42

H’44

H’46

H’48

H’4A

H’4C

H’4E

H’50

H’52

H’54

H’56

H’58

H’5A

H’5C

H’5E

H’60

H’62

H’64

H’66

H’68

H’6A

H’6C

H’6E

H’70

H’72

H’74

H’76

(Reserved)

CPU_FIFO Select Register

CPU_FIFO Control Register

CPU_FIFO Data Register

SIE_FIFO Status Register

D0_FIFO Select Register

D0_FIFO Control Register

D0_FIFO Data Register

H'0000

H'0800

????

-

H'0000

H'0800

????

-

DMA0_Transaction Count Register

D1_FIFO Select Register

D1_FIFO Control Register

D1_FIFO Data Register

H'0000

H'0800

????

-

DMA1_Transaction Count Register

FIFO Status Register

H'0000

H'0040

H'0000

H'0040

H'0000

H'0040

H'0000

H'0040

H'0000

H'0040

H'0000

H'0040

-

H'0000

Port Control Register

-

Port Data Register

Drive Current Adjust Register

EP1 Configuration Register 0

EP1 Configuration Register 1

EP2 Configuration Register 0

EP2 Configuration Register 1

EP3 Configuration Register 0

EP3 Configuration Register 1

EP4 Configuration Register 0

EP4 Configuration Register 1

EP5 Configuration Register 0

EP5 Configuration Register 1

EP6 Configuration Register 0

EP6 Configuration Register 1

Figure 2.2 Register Mapping (2)

Rev1.01 2004.11.01 page 11 of 122

M66291GP/HP

2.1 USB Operation Enable Register

Q USB Operation Enable Register (USB_ENABLE)

b15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

b0

XCKE PLLC

Xtal

SCKE USBPC

Tr_on

USBE

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

b

Bit name

Function

R

W

15

XCKE

0 : Disable oscillation buffer (Disable clock supply to inside

PLL)

{

Oscillation Buffer Enable

1 : Enable oscillation buffer (Enable clock supply to inside

PLL)

14

PLLC

0 : Disable PLL (PLL through)

1 : Enable PLL

{

PLL Operation Enable

13~12 Xtal

Clock Select

00 : External clock frequency : 48 MHz (PLL through)

10 : External clock frequency : 24 MHz

01 : External clock frequency : 12 MHz

11 : External clock frequency : 6 MHz

0 : Disable Internal clock

11

10

SCKE

{

Internal Clock Enable

USBPC

1 : Enable Internal clock

0 : Disable USB transceiver

1 : Enable USB transceiver

00 : TrON output ="Hi-Z" (SIE operate stop)

01 : TrON output ="L"

USB Transceiver Power Control

Tr_on

9~8

Tr_on Output Control

10 : Reserved

11 : TrON output ="H"

7~1

0

Reserved. Set it to “0”.

USBE

0

0 : S/W reset state

{

USB Module Operation Enable

1 : S/W reset state release

.

(1) XCKE (Oscillation Buffer Enable) Bit (b15)

This bit sets enable/disable of the oscillation buffer.

The output clock from the oscillation buffer is supplied to the PLL.

Refer to Figure 2.3.

(2) PLLC (PLL Operation Enable) Bit (b14)

This bit sets enable/disable of PLL.

When this bit is set to “1”, the external clock into the PLL is multiplied according to the value set in the Xtal

bits before being output to the core block. Set the XCKE bit to “1” and wait until the oscillation circuit starts

and becomes stable before setting this bit to “1”.

When this bit is set to “0”, PLL stops operation and the external clock into the PLL is output to the core block

without being multiplied. Hence, be sure to supply the 48 MHz clock to the oscillation buffer when setting this

bit to “0”.

Refer to Figure 2.3.

Rev1.01 2004.11.01 page 12 of 122

M66291GP/HP

(3) Xtal (Clock Select) Bits (b13~b12)

These bits set the multiplication factor of the external clock into PLL.

Since it is necessary to supply 48 MHz to the core block, the setting values of these bits are determined by the

clock frequency to be input into the PLL.

Refer to Figure 2.3.

(4) SCKE (Internal Clock Enable) Bit (b11)

This bit sets the clock supply into the core block.

Set the PLLC bit to “1” and wait until the oscillation of the PLL stabilizes before setting this bit to “1”.

Refer to Figure 2.3.

I/O block

Core block

Xtal bits

Multiplying

factor

Oscillation

buffer

External clock

PLL

Enable/Disable

XCKE bit

Enable/Disable

PLLC bit

SCKE bit

Figure 2.3 Clock Control

(5) USBPC (USB Transceiver Power Control) Bit (b10)

This bit sets the enable/disable of the USB transceiver block of I/O block.

Even if this bit is set to “0”, it is possible to receive the resume signal during the Suspended state (DVSQ bits

= “1xx”). It is necessary that the Tr_on bits be set to “x1” (during operation of SIE block).

(6) Tr_on (Tr_on Output Control) Bits (b9~b8)

These bits set the TrON signal output from I/O block and the enable/disable of SIE block in core block.

(7) USBE (USB Module Operation Enable) Bit (b0)

This bit sets S/W reset.

When this bit is set to “0”, the M66291 enters the S/W reset state and the registers are set to their S/W reset

state.

.

Rev1.01 2004.11.01 page 13 of 122

M66291GP/HP

2.2 Remote Wakeup Register

Q Remote Wakeup Register (REMOTE_WAKEUP)

b15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

b0

WKUP

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

b

15~1

0

Bit name

Function

R

0

W

0

Reserved. Set it to “0”.

WKUP

Q Read

{

Remote Wakeup

0 : Do not output the remote wakeup signal

1 : Output the remote wakeup signal

Q Write

0 : Invalid (Ignored when written)

1 : Output the remote wakeup signal

(1) WKUP (Remote Wakeup) Bit (b0)

This bit controls the output of the remote wakeup signal (K state output).

This bit is valid only when the device state is “suspend” (DVSQ bits = “1xx”). The writing of “1” to this bit is

ignored when the device state is not suspend.

When “1” is written to this bit, the K state is output for 10 ms. The bit is automatically cleared to “0” after K

state output.

The bus idle state continues (this WKUP bit = “1”) for 2 ms after the Suspend state is detected when “1” is

written to this bit before outputting the K state for 10 ms.

The 2 ms and 10 ms time intervals are counted using a clock. Make sure that the counting stops if the clock is

not supplied (Note).

Note : SCKE bit = “0” when XCKE bit = “1 ”, or XCKE bit = “0”.

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M66291GP/HP

2.3 Sequence Bit Clear Register

Q Sequence Bit Clear Register (SEQUENCE_BIT)

b15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

b0

SQCLR

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

b

Bit name

Function

R

0

W

0

15~7

6~0

Reserved. Set it to “0”.

SQCLR

Q Write

{

Sequence Bit Clear

0 : Invalid (Ignored when written)

1 : Clear Sequence bit

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

(1) SQCLR (Sequence Bit Clear) Bits (b6~b0)

These bits clear the sequence bit (the bit controlled by H/W) and turns the data PID into DATA 0 PID.

This bit immediately returns to “0” after writing “1”.

In the transfers after the sequence bit is cleared, the sequence bit is toggled through H/W control.

At S/W reset (USBE bit = “1”) and USB bus reset, the sequence bit of each endpoint is not cleared.

Note : Be sure to set the response PID of the endpoint whose sequence bit is desired to be cleared to NAK (EP0_PID

bits = “00”/EPi_PID bits = “00”) before writing “1” to this bit.

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M66291GP/HP

2.4 USB_Address Register

Q USB_Address Register (USB_ADDRESS)

b15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

b0

USB_Addr

0

b

Bit name

Function

R

0

W

0

15~7

6~0

Reserved. Set it to “0”.

USB_Addr

Q Read

{

×

USB_Address

USB address assigned by the host

(1) USB_Addr (USB_Address) Bits (b6~b0)

These bits store the USB address assigned by the host.

On receiving SET_ADDRESS request from the host at default state (DVSQ bits = “001”), the requested device

address value is set to this register when the response is made through zero-length packet in status stage.

The device address value is set to these bits at the time of zero-length packet transmit even if the ASAD bit is

set to “0” (automatic response is invalid).

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2.5 Isochronous Status Register

Q Isochronous Status Register (ISOCHRONOUS_STATUS)

b15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

b0

FMOD

FRNM

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

b

Bit name

Function

R

?

W

0

15~12 Reserved. Set it to “0”.

11

FMOD

0 : At SOF receive

{

Frame Number Mode

FRNM

1 : At Isochronous transfer complete

Stores the frame number

10~0

{

×

Frame Number

This register is valid only for isochronous transfer. In other words, the register is valid status for the endpoint

that is set EPi_TYP bits to “11”.

(1) FMOD (Frame Number Mode) Bit (b11)

This bit sets the storage timing of the frame number to be stored to the FRNM bits.

When this bit is set to “0”, when the SOF packet is properly received, the frame number of the received SOF

packet gets stored.

When this bit is set to “1”, when the isochronous packet transfer completes, the frame number of the properly

received SOF packet gets stored.

(2) FRNM (Frame Number) Bits (b10~b0)

The frame number is stored in the FRNM with the timing set by the FMOD bit of this register. Here, the

SOFR bit is set to “1”.

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2.6 SOF Control Register

Q SOF Control Register (SOF_CNT)

b15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

b0

SOFOE SOFA

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

b

Bit name

Function

R

W

15

SOFOE

0 : Disable SOF signal output

1 : Enable SOF signal output

0 : "L" active

{

SOF Output Enable

SOFA

14

{

SOF Polarity

1 : "H" active

13~0

Reserved. Set it to “0”.

0

(1) SOFOE (SOF Output Enable) Bit (b15)

This bit sets the enable/disable of SOF signal output.

When this bit is set to “1”, if SOF packet is received, the INT1/SOF pin outputs SOF signal. The output polarity is

set by SOFA bit.

The SOF signal outputs the pulse (approx. 0.67 us) equivalent to 32 clocks of the 48 MHz clock after receiving

the PID field. Refer to Figure 2.4.

Since the INT1 pin is double-function pin, do not allocate the interrupt signal to this pin when using the SOF

signal (Set by the Polarity Set Register).

SOF packet

USB bus signal

SYNC

PID

FLAME

CRC5

SOF signal

("L" active)

Fixed length

Approx. 0.67us

Figure 2.4 SOF Signal Output Timing

(2) SOFA (SOF Polarity) Bit (b14)

This bit sets the output polarity of SOF signal.

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2.7 Polarity Set Register

Q Polarity Set Register (POLARITY_CNT)

b15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

b0

VB01 RM01 SF01 DS01 CT01 BE01 NR01 RD01

RDYM INTL

INTA

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

b

Bit name

Function

R

W

15

14

13

12

11

10

9

VB01

0 : Assigns to INT0 pin

{

Vbus Interrupt Assign

RM01

1 : Assigns to INT1 pin (Note)

0 : Assigns to INT0 pin

{

Resume Interrupt Assign

SF01

1 : Assigns to INT1 pin (Note)

0 : Assigns to INT0 pin

SOF Detect Interrupt Assign

DS01

1 : Assigns to INT1 pin (Note)

0 : Assigns to INT0 pin

Device State Transition Interrupt Assign

1 : Assigns to INT1 pin (Note)

0 : Assigns to INT0 pin

CT01

Control Transfer Transition Interrupt Assign

BE01

1 : Assigns to INT1 pin (Note)

0 : Assigns to INT0 pin

Buffer Empty/Size Over Error Interrupt Assign 1 : Assigns to INT1 pin (Note)

NR01

0 : Assigns to INT0 pin

Buffer Not Ready Interrupt Assign

RD01

1 : Assigns to INT1 pin (Note)

0 : Assigns to INT0 pin

8

Buffer Ready Interrupt Assign

Reserved. Set it to “0”.

RDYM

1 : Assigns to INT1 pin (Note)

7~3

2

0

0 : Clears the EPB_RDY bits by reading/writing all data of

buffer

{

Buffer Ready Mode

1 : Clears the EPB_RDY bits by writing "0" to EPB_RDY bit

0 : Edge sensitive output

1

0

INTL

{

Interrupt Output Sense

INTA

1 : Level sensitive output

0 : "L" active or change from “H” to “L”

1 : "H" active or change from "L" to "H"

Interrupt Polarity

Note : In order to allocate the interrupt output signal to the INT1/SOF pin, set the SOF signal output to “disable” (SOFOE bit =

“0”).

(1) VB01 (Vbus Interrupt Assign) Bit (b15)

This bit selects the pin to output the Vbus interrupt signal.

(2) RM01 (Resume Interrupt Assign) Bit (b14)

This bit selects the pin to output the resume interrupt signal.

(3) SF01 (SOF Detect Interrupt Assign) Bit (b13)

This bit selects the pin to output the SOF detect interrupt signal.

(4) DS01 (Device State Transition Interrupt Assign) Bit (b12)

This bit selects the pin to output device state transition interrupt signal.

(5) CT01 (Control Transfer Transition Interrupt Assign) Bit (b11)

This bit selects the pin to output the control transfer transition interrupt signal.

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(6) BE01 (Buffer Empty/Size Over Error Interrupt Assign) Bit (b10)

This bit selects the pin to output the buffer empty/size over error interrupt signal.

(7) NR01 (Buffer Not Ready Interrupt Assign) Bit (b9)

This bit selects the pin to output the buffer not ready interrupt signal.

(8) RD01 (Buffer Ready Interrupt Assign) Bit (b8)

This bit selects the pin to output the buffer ready interrupt signal.

(9) RDYM (Buffer Ready Mode) Bit (b2)

This bit selects the method of clearing the buffer ready interrupt.

When this bit is set to “0”, the EPB_RDY bit is cleared to “0” after the CPU side buffer data are all read out or

after the writing of transmit data completes.

When this bit is set to “1”, the EPB_RDY bit is cleared to “0” by writing “0” to the EPB_RDY bit.

For details, refer to “EPB_RDY bit”.

Note : Refer to “3.2 FIFO Buffer” for CPU/SIE side.

(10) INTL (Interrupt Output Sense) Bit (b1)

This bit sets the sense mode for interrupt output from INT0 or INT1 pin.

When this bit is set to “0”, the INT0 or INT1 pin notifies the occurrence of interrupt at the edge set by the

INTA bit.

During edge sensitive output, when “0” is written to each interrupt factor bit to clear the interrupt, the output

signal outputs the negate value one time. If the other interrupt factor bits are set to “1”, the occurrence of

interrupt again is notified at the edge. The negate period is equivalent to 32 clocks (approx. 667 ns) of the 48

MHz clock.

In case the clock is not supplied (Note), the negate period does not occur. Make sure not to miss the interrupt

when Vbus interrupt or resume interrupt occurs.

When this bit is set to “1”, the INT0 or INT1 pin notifies the occurrence of interrupt at the level set by the

INTA bit.

During level sensitive output, the negate fails to work unless all interrupt factor bits are cleared even if “0” is

written to clear the interrupt to the interrupt factor bits.

Refer to Figure 2.5 and “3.1 Interrupt Function”.

Note : SCKE bit = “0” when XCKE bit = “1 ” , or XCKE bit = “0”.

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Factor 1 occur Factor 2 occur Factor 1 clear

Factor 2 clear

Interrupt factor 1

("H" active)

Interrupt factor 2

("H" active)

Interrupt pin

("L" active)

Negate period

(Approx.667ns)

Factor 1 occur Factor 2 occur Factor 1 clear

Factor 2 clear

Interrupt factor 1

("H" active)

Interrupt factor 2

("H" active)

Interrupt pin

("L" active)

Figure 2.5 Interrupt Signal Output Timing

(11) INTA (Interrupt Polarity) Bit (b0)

This bit sets the interrupt signal output polarity.

When this bit is set to “0”, the occurrence of interrupt is notified when;

In case of edge sense (INTL bit = “0”) : Change from “H” to “L”

In case of level sense (INTL bit = “1”) : “L” level

When this bit is set to “1”, the occurrence of interrupt is notified when;

In case of edge sense (INTL bit = “0”) : Change from “L” to “H”

In case of level sense (INTL bit = “1”) : “H” level

Rev1.01 2004.11.01 page 21 of 122

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2.8 Interrupt Enable Register 0

Q Interrupt Enable Register 0 (INT_ENABLE0)

b0

b15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

VBSE RSME SOFE DVSE CTRE BEMPE INTNE INTRE URST SADR SCFG SUSP WDST RDST CMPL SERR

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

b

Bit name

Function

R

W

15

14

13

12

11

10

9

VBSE

0 : Disable interrupt

1 : Enable interrupt

{

Vbus Interrupt Enable

(Interrupt occurs when VBUS bit is set to “1”)

0 : Disable interrupt

RSME

{

Resume Interrupt Enable

1 : Enable interrupt

(Interrupt occurs when RESM bit is set to "1")

0 : Disable interrupt

SOFE

SOF Detect Interrupt Enable

1 : Enable interrupt

(Interrupt occurs when SOFR bit is set to "1")

0 : Disable interrupt

DVSE

Device State Transition Interrupt Enable

1 : Enable interrupt

(Interrupt occurs when DVST bit is set to "1")

0 : Disable interrupt

CTRE

Control Transfer Transition Interrupt Enable

BEMPE

1 : Enable interrupt

(Interrupt is occurs when CTRT bit is set to "1")

0 : Disable interrupt

Buffer Empty/Size Over Error Interrupt Enable 1 : Enable interrupt

(Interrupt is occurs when BEMP bit is set to "1")

0 : Disable interrupt

1 : Enable interrupt

(Interrupt occurs when INTN bit is set to "1")

INTNE

Buffer Not Ready Interrupt Enable

8

INTRE

0 : Disable interrupt

1 : Enable interrupt

Buffer Ready Interrupt Enable

(Interrupt occurs when INTR bit is set to "1")

7

6

5

4

3

2

1

0

URST

0 : Disable DVST bit set

1 : Enable DVST bit set

0 : Disable DVST bit set

1 : Enable DVST bit set

0 : Disable DVST bit set

1 : Enable DVST bit set

0 : Disable DVST bit set

1 : Enable DVST bit set

0 : Disable CTRT bit set

1 : Enable CTRT bit set

0 : Disable CTRT bit set

1 : Enable CTRT bit set

0 : Disable CTRT bit set

1 : Enable CTRT bit set

0 : Disable CTRT bit set

1 : Enable CTRT bit set

{

USB Reset Detect

SADR

SET_ADDRESS Execute

SCFG

SET_CONFIGURATION Execute

SUSP

Suspend Detect

WDST

Control Write Transfer Status Stage

RDST

Control Read Transfer Status Stage

CMPL

Control Transfer Complete

SERR

Control Transfer Sequence Error

This register sets enable of interrupt and enable/disable of setting DVST and CTRT bits to “1”.

Also refer to “3.1 Interrupt Function”.

Rev1.01 2004.11.01 page 22 of 122

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(1) VBSE (Vbus Interrupt Enable) Bit (b15)

This bit sets enable/disable of Vbus interrupt.

When this bit is set to “1”, the interrupt occurs if VBUS bit is set to “1”.

This bit is capable of writing/reading even if the clock is not supplied (Note).

Note : At SCKE bit = “0” when XCKE bit = “1 ” or XCKE bit = “0”.

(2) RSME (Resume Interrupt Enable) Bit (b14)

This bit sets enable/disable of resume interrupt.

When this bit is set to “1”, the interrupt occurs if RESM bit is set to “1”.

This bit is capable of writing/reading even if the clock is not supplied (Note).

Note : At SCKE bit = “0” when XCKE bit = “1 ” or XCKE bit = “0”.

(3) SOFE (SOF Detect Interrupt Enable) Bit (b13)

This bit sets enable/disable of SOF detect interrupt.

When this bit is set to “1”, the interrupt occurs if SOFR bit is set to “1”.

(4) DVSE (Device State Transition Interrupt Enable) Bit (b12)

This bit sets enable/disable of device state transition interrupt.

When this bit is set to “1”, the interrupt occurs if DVST bit is set to “1”.

The Conditions the DVST bit set are depend on the URST, SADR, SCFG or SUSP.

(5) CTRE (Control Transfer Transition Interrupt Enable) Bit (b11)

This bit sets enable/disable of control transfer transition interrupt.

When this bit is set to “1”, the interrupt occurs if CTRT bit is set to “1”.

The Conditions the DVST bit set are depend on the WDST, RDST, CMPL or SERR.

The complete of setup stage can not set enable/disable to set CTRT bit to “1”.

(6) BEMPE (Buffer Empty/Size Over Error Interrupt Enable) Bit (b10)

This bit sets enable/disable of buffer empty/size over error interrupt.

When this bit is set to “1”, the interrupt occurs if BEMP bit is set to “1”.

(7) INTNE (Buffer Not Ready Interrupt Enable) Bit (b9)

This bit sets enable/disable of buffer not ready interrupt.

When this bit is set to “1”, the interrupt occurs if INTN bit is set to “1”.

(8) INTRE (Buffer Ready Interrupt Enable) Bit (b8)

This bit sets enable/disable of buffer ready interrupt.

When this bit is set to “1”, the interrupt occurs if INTR bit is set to “1”.

(9) URST (USB Reset Detect) Bit (b7)

This bit selects whether to set the DVST bit to “1” or not at the USB bus reset detection.

The register is initialized by the USB reset detection, irrespective of the value of this bit.

(10) SADR (SET_ADDRESS Execute) Bit (b6)

This bit selects whether to set the DVST bit to “1” or not at the SET_ADDRESS execution.

For details, refer to “DVST bit”.

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(11) SCFG (SET_CONFIGURATION Execute) Bit (b5)

This bit selects whether to set the DVST bit to “1” or not at the SET_ CONFIGURATION execution.

For details, refer to “DVST bit”.

(12) SUSP (Suspend Detect) Bit (b4)

This bit selects whether to set the DVST bit to “1” or not at the suspend detection.

(13) WDST (Control Write Transfer Status Stage) Bit (b3)

This bit selects whether to set the CTRT bit to “1” or not when transited to status stage during control write

transfer.

(14) RDST (Control Read Transfer Status Stage) Bit (b2)

This bit selects whether to set the CTRT bit to “1” or not when transited to status stage during control read

transfer.

(15) CMPL (Control Transfer Complete) Bit (b1)

This bit selects whether to set the CTRT bit to “1” or not when the status stage completes during control

transfer.

(16) SERR (Control Transfer Sequence Error) Bit (b0)

This bit selects whether to set the CTRT bit to “1” or not when the sequence error is detected at control

transfer.

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2.9 Interrupt Enable Register 1

Q Interrupt Enable Register 1 (INT_ENABLE1)

b15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

b0

EPB_RE

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

b

Bit name

Function

R

0

W

0

15~7

6~0

Reserved. Set it to “0”.

EPB_RE

0 : Disable INTR bit set

1 : Enable INTR bit set

{

Buffer Ready Interrupt Enable

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

(1) EPB_RE (Buffer Ready Interrupt Enable) Bits (b6~b0)

These bits select whether to set the INTR bit to “1” or not when the EPB_RDY bit is set to “1”.

Also refer to “3.1 Interrupt Function”.

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2.10 Interrupt Enable Register 2

Q Interrupt Enable Register 2 (INT_ENABLE2)

b15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

b0

EPB_NRE

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

b

Bit name

Function

R

0

W

0

15~7

6~0

Reserved. Set it to “0”.

EPB_NRE

0 : Disable INTN bit set

1 : Enable INTN bit set

{

Buffer Not Ready Interrupt Enable

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

(1) EPB_NRE (Buffer Not Ready Interrupt Enable) Bits (b6~b0)

These bits select whether to set the INTN bit to “1” or not when the EPB_NRDY bit is set to “1”.

Also refer to “3.1 Interrupt Function”.

Note : Do not set the corresponding bit of this register to “1” when the endpoint is set to isochronous transfer (set by

EPi _TYP bits).

Rev1.01 2004.11.01 page 26 of 122

M66291GP/HP

2.11 Interrupt Enable Register 3

Q Interrupt Enable Register 3 (INT_ENABLE3)

b15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

b0

EPB_EMPE

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

b

Bit name

Function

R

0

W

0

15~7

6~0

Reserved. Set it to “0”.

EPB_EMPE

0 : Disable BEMP bit set

{

Buffer Empty/Size Over Error Interrupt Enable 1 : Enable BEMP bit set

b6 corresponds to EP6, ---b1 corresponds to EP1 and b0

corresponds to EP0.

(1) EPB_EMPE (Buffer Empty/Size Over Error Interrupt Enable) Bits (b6~b0)

These bits select whether to set the BEMP bit to “1” or not when the EPB_EMP_OVR bit is set to “1”.

Also refer to “3.1 Interrupt Function”.

Rev1.01 2004.11.01 page 27 of 122

M66291GP/HP

2.12 Interrupt Status Register 0

Q Interrupt Status Register 0 (INT_STATUS0)

b15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

b0

VBUS RESM SOFR DVST CTRT BEMP INTN

INTR

Vbus

DVSQ

VALID

CTSQ

0

-

0

-

0

-

0

1

0

-

0

-

0

-

0

-

0

1

0

-

0

-

0

-

0

-

b

Bit name

Function

R

W

15

14

13

12

11

VBUS

Q Read

{

Vbus Interrupt

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

0 : Clear Interrupt

1 : Invalid (Ignored when written)

Q Read

RESM

{

Resume Interrupt

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

0 : Clear Interrupt

1 : Invalid (Ignored when written)

Q Read

SOFR

SOF Detect Interrupt

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

0 : Clear Interrupt

1 : Invalid (Ignored when written)

Q Read

DVST

Device State Transition Interrupt

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

0 : Clear Interrupt

1 : Invalid (Ignored when written)

Q Read

CTRT

Control Transfer Stage Transition Interrupt

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

0 : Clear Interrupt

1 : Invalid (Ignored when written)

Q Read

×

10

BEMP

{

Buffer Empty/Size Over Error Interrupt

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

Invalid (Ignored when written)

Q Read

9

INTN

Buffer Not Ready Interrupt

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

Invalid (Ignored when written)

Q Read

8

INTR

Buffer Ready Interrupt

0 : No occurrence of interrupt

1 : Occurrence of interrupt

Q Write

Invalid (Ignored when written)

Rev1.01 2004.11.01 page 28 of 122

M66291GP/HP

b

Bit name

Function

R

W

×

7

Vbus

Q Read

0 : "L"

1 : "H"

Q Write

{

Vbus Level

Invalid (Ignored when written)

Q Read

×

6~4

DVSQ

{

Device State

000 : Powered state

001 : Default state

010 : Address state

011 : Configured state

1xx : Suspended state (Note)

Q Write

Invalid (Ignored when written)

Q Read

3

VALID

{

Setup Packet Detect

0 : No detection

1 : Receiving the setup packet

Q Write

0 : This VALID bit clear

1 : Invalid (Ignored when written)

Q Read

×

2~0

CTSQ

Control Transfer Stage

000 : Idle or setup stage

001 : Control read transfer data stage

010 : Control read transfer status stage

011 : Control write transfer data stage

100 : Control write transfer status stage

101 : Control write no data transfer status stage

110 : Control transfer sequence error

111 : Reserved

Q Write

Invalid (Ignored when written)

Note : x is a optional value.

The b15 to b8 of this register are interrupt status bits. When the bit of the Interrupt Enable Register

corresponding to these bits are set to “1” (interrupt enable), the interrupt occurs by setting these bits to “1”.

(1) VBUS (Vbus Interrupt) Bit (b15)

This bit indicates the change of Vbus input.

This bit is set to “1” (Vbus interrupt occurs) when the Vbus input changes (“L”->“H” or “H”->“L”).

This bit is cleared to “0” by writing “0” (interrupt is cleared).

This bit is set to “1” and can be read out even if the clock is not supplied (Note). This bit can also be cleared by

writing “0”. In case the clock is not supplied, make sure to write “1” after writing “0” (no further interrupt will

be accepted).

Note : SCKE bit = “0” when XCKE bit = “1 ”, or XCKE bit = “0”.

Rev1.01 2004.11.01 page 29 of 122

M66291GP/HP

(2) RESM (Resume Interrupt) Bit (b14)

This bit indicates the change of USB bus state.

This bit is set to “1” when the USB bus state is changed from suspended (DVST bits = “1xx”) to “J”->“K” or

“J”->“SE0” (resume interrupt occurs).

This bit is cleared to “0” by writing “0” (interrupt is cleared).

This bit is set to “1” and can be read out even if the clock is not supplied (Note). This bit can also be cleared by

writing “0”. In case the clock is not supplied, make sure to write “1” after writing “0” (no further interrupt will

be accepted).

Note : At SCKE bit = “0” when XCKE bit = “1 ” or XCKE bit = “0”.

(3) SOFR (SOF Detect Interrupt) Bit (b13)

This bit indicates that the SOF packet is received and the frame number is updated.

This bit is set to “1” when the SOF packet is received and the frame number is stored at the timing set by the

FMOD bit of the Isochronous Status Register (SOF detect interrupt occurs).

This bit is cleared to “0” by writing “0” (interrupt is cleared).

(4) DVST (Device State Transition Interrupt) Bit (b12)

This bit indicates the transition of the device state.

This bit is set to “1” when the transition of device states takes place as follows (device state transition

interrupt occurs):

(A) USB bus reset detect (Arbitrary state -> Default state):

When the SE0 state continues for 2.5 us or more in D+ and D- pins, the USB bus reset is detected,

causing this bit to be set to “1”.

(B) “SET_ADDRESS” execute (Default state -> Address state):

This bit is set to “1” when the SET_ADDRESS request is detected as (a) and the response is made

by zero-length packet in status stage.

(a) “SET_ADDRESS” request in case device address value in default state is not “0”:

In case the wValue in default state is “0”, this bit is not set to “1”. When this request is

received, the device address value is set to the USB_Address Register, irrespective of the

setting of this bit.

(C) “SET CONFIGURATION” execute (Address state -> Configured state):

This bit is set to “1” when the requests below are detected and ACK is received after the response

is made through zero-length packet in status stage.

(a) “SET_CONFIGURATION” request in case configuration value in address state is not “0”

(b) “SET_CONFIGURATION” request in case configuration value in configured state is “0”

(D)Suspend detect (Powered/Default/Address/Configured state -> Suspended state):

The suspended state is detected and this bit is set to“1” when the idle state continues for 3 ms or


型号：	M66291GP
厂家：	RENESAS TECHNOLOGY CORP
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M66291GP [RENESAS]

相关型号：

M66291HP

M66300FP

M66300P

M66305AFP

M66305AFP

M66305AP

M66305AP

M66305FP

M66305P

M66307FP

M66307FP

M66307SP