M66290AFP_技术文档

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

Ver.1.0 Oct. 27, 2000

USB DEVICE CONTROLLER

DESCRIPTION

· Data transf er condition selectable f or each

The M66290A is a general purpose USB (Univ ersal Serial

Bus) dev ice controller compatible with the USB

specification version 1.1 and corresponds to full speed

transf er. Built-in transceiver circuits meet all transf er type

which is defined in USB.

Endpoints (EP1 to EP5)

· Data transf er type

(Bulk, Isochronous and Interrupt)

· Transf er direction (IN/OUT)

· Buf f er size of FIFO (maximum 1024 Bytes)

· Double (Toggle) buf f er configuration

· Continuous transfer mode

(Buf f ering up to 1 KByteX2)

· Max packet size

M66290A has FIFO of 3k Bytes f or data transf er and can

set 6 endpoints (maximum).

Each endpoint can be set programmable of its transf er

condition, so can correspond to each device class transf er

system of USB.

· Supports 4 input clock f requencies

· Input clock : 6/12/24/48 MHz

· Built-in PLL which has an oscillation buf f er

and outputs at 48 MHz

FEATURES

· USB specif ication 1.1 compliant

· Built-in USB transceiv er circuit

· Supports Full Speed (12 Mbps) transmission

· Supports all four USB transf er type :

· Control transf er

· Supports both 8-bit and 16-bit DMA transf ers

· 16-bit CPU bus interface

· 3.3V single power source

· Built-in JTAG

· Bulk transf er

APPLICATION

· Isochronous transf er

· Printer , Scanner , DSC , DVC

· Interrupt transfer

· PC camera , Multimedia speaker , Terminal adapter etc.

· Support all PC peripheral using Full Speed USB

· Built-in FIFO (3 KBy tes) for Endpoint

· Up to 6 endpoint (EP0 to EP5) selectable

PIN CONFIGURATION

(TOP VIEW)

24

D1

37

D12

D13

DATA BUS

23

38

D0

A6

DATA BUS

22

D14

D15

39

21

40

A5

A4

20

M66290AGP

OR

TEST2 INPUT TEST2

41

42

43

44

45

46

47

48

ADDRESS BUS

19

INTERRUPT

READ STROBE

INT

RD

WR

CS

A3

A2

A1

VCC

18

17

16

15

14

13

WRITE STROBE

CHIP SELECT

M66290AFP

RESET

DMA REQUEST

GND

Xin

Xout

RST

Dreq

OSCILLATOR INPUT

DMA ACKNOWLEDGE

Dack

OSCILLATOR OUTPUT

Outline

M66290AGP:48P6Q-A(LQFP)

M66290AFP:48P6X-A(TQFP)

c MITSUBISHI ELECTRIC CORPORATION

1

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

VCC

BLOCK DIAGRAM

1

16 35

Clock

14

13

Xin

Control

(Oscillator/

PLL)

17

Xout

to

A6 to 1

22

23

to

Device

Control

Unit

USB

Peripheral

Circuit

Vbus

TrON

5

6

D15 to 0

40

45

CS

CPU

Register

44

WR

RD

Serial

Interface

Engine

43

68

42

INT

4

3

D+

D-

USB

Transceiver

47

Dreq

Dack

Endpoint

Buffer

(3KByteFIFO)

68

48

8

9

TRST

TCK

10

TMS

11

12

TDI

46

TDO

RST

7

TEST1

TEST2

41

2

15 36

GND

BLOCK DESCRIPTIONS

The M66290A contains USB transceiv er, oscillation

circuit, PLL, serial interface engine, endpoint buf f er,

device control unit, and CPU register.

Endpoint Buf f er

This is a FIFO buf f er f or transmit and receive

between endpoints.

Except f or EP0 for control transfer, f ive endpoints

(EP1 to EP5) can be set.

USB Transceiv er

USB Transceiv er is consisted of dif f erential driv er

and dif f erential receiver.

And is compatible with USB specif ication v ersion 1.1

and corresponds to Full Speed Transfer mode.

CPU Register

This is an interf ace block with CPU.

Serial Interf ace Engine (SIE)

SIE handles protocol layer as f ollows.

Oscillator/PLL

This block oscillates the internal operation clock

source of 48MHz.

Extract a USB 12MHz clock

Serial-Parallel data conversion

SYNC detection

NRZI encode and decode

Bit stuf f ing and destuf f ing

CRC generator and checker

External clock of 6/12/24/48MHz can be input.

USB peripheral circuit

Detect the connection and the shutdown of USB

by the Vbus input.

Connect the Vbus of USB bus to or the 5V power

supply to Vbus input.

Device Control Unit (DCU)

DCU controls the device state sequence, control

Connect the TrON output to D+ pull-up resistor of

1.5kohm. ON/OFF of the pull-up resistor is controlled

by the register.

transf er sequence, and so on.

2

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

PIN DESCRIPTIONS

Input/

Number of

Item

Pin name

Function

Input/ DATA BUS

D15 to D0

16

6

Output Data bus to access the register from the system

ADDRESS BUS

A6 to A1

CS

Input

Address bus to access the register from the system

CHIP SELECT

Input

1

"L" level enables to communicate with M66290A

CPU

interface

WRITE STROBE

WR

Input

1

Input data is written into the register by the positive edge

READ STROBE

Input

RD

1

Register data can be read when "L" level

INTERRUPT

Output

INT

1

"L" level requests interrupt to system

DMA REQUEST

Output

Dreq

Dack

D+

1

DMA transfer request to endpoint FIFO

DMA

interface

DMA ACKNOWLEDGE

Input

1

FIFO access by DMA transfer is available in "L" level

Input/ USB DATA(+)

1

Output D+ of USB. Connect the external resistor serially.

Input/ USB DATA(-)

D-

1

Output D- of USB. Connect the external resistor serially.

USB

Vbus INPUT (Built-in pull down resistor)

interface

Vbus

Input Connect to the Vbus of USB bus or to the 5V power supply.

Connection or shutdown of the Vbus can be detected.

1

TrON OUTPUT

Output

Connect to the D+ pull-up resistor of 1.5kohm.

TrON

TRST

ON/OFF control of the pull-up resistor is available.

TEST RESET INPUT (Built-in pull up resistor)

Input Reset input of JTAG. Even if the JTAG is not used, JTAG circuit must be

initialized. Input "L" level to initialize like the RST input.

TEST MODE INPUT (Built-in pull up resistor)

Input

TMS

TCK

TDI

1

Mode set input to JTAG. If JTAG is not used, keep "H" level or open.

JTAG

TEST CLOCK INPUT (Built-in pull down resistor)

Input

interface

Clock input to JTAG. If JTAG is not used, keep "L" level or open.

TEST DATA INPUT (Built-in pull up resistor)

Input

Data input to JTAG. If JTAG is not used, keep "H" level or open.

TEST DATA OUTPUT

TDO

RST

Output

1

Data output from JTAG. If the JTAG is not used, keep open.

RESET

Input

"L" level initializes the register or the counter of M66290A.

OSCILLATO

R INPUT

Generate an internal clock.

Xin

Input

Output

Input

1

Input or output of internal clock oscillator. When use as a crystal oscillator, connect a

crystal between Xin and Xout.

OSCILLATO

R OUTPUT

Xout

If an external clock is used, input it to Xin, and Xout must be opened.

Others

TEST1 INPUT (Built-in pull down resistor)

Input for the test. Keep "L" level or open.

TEST1

TEST2

TEST2 INPUT (Built-in pull down resistor)

Input for the test. Keep "L" level or open.

Input

1

VCC

-

Power supply pin

Ground

3

GND

3

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

USB DATA TRANSFER DESCRIPTIONS

Data transmit

M66290A is a USB device controller correspond to all

the f our types of transfer (control, bulk, isochronous,

and interrupt transf er), which is compatible to USB

specification 1.1.

When the data of endpoint FIFO, which corresponds to

transmit request by IN token packet, is ready , M66290A

transmit the corresponded data packet to USB bus.

If the ACK packet come f rom the host for the transmitted

data packet, a transaction completed and the endpoint

FIFO becomes empty and urge CPU to write the next

transmit data by buf f er ready interrupt.

M66290A acts USB functions as below automatically.

(1) Bit stuf f ing/destuf f ing

(2) CRC generate/check

(3) NRZI encode/decode

(4) Packet handling

If the transmit data, which correspond to transmit request

by IN token packet, is not exist in the endpoint FIFO,

M66290A transmit NAK packet to host when received

IN token packet from host and occurs interrupt and

request CPU to write transmit data.

(5) USB address check

(6) Bus error handling

Theref ore, when CPU transact the operations as

follows, USB transf er is realized.

(1) Response to the control transfer request

(2) Permission of store and transmission of the

transmit data into the endpoint buf f er.

(Or read of the receiv ed data f rom the endpoint

buf f er)

When M66290A receiv ed IN token packet again f rom host,

M66290A transmits the data which is written.

If error is not occurred in that transf er, host transmit ACK

packet and if M66290A receiv ed it normally , a transaction

completed.

If USB protocol error is occurred in the data which is

transmitted v ia USB bus, host does not transmit ACK

packet, so M66290A watch and wait until receive IN token

packet, with keeping the data to be transmitted.

(3) Stall handling

(4) Suspend/resume handling

Below are the descriptions about the data transfer.

Data receive

In data receiv e, there are dif f erences of its f unction

between setup transaction and out transaction.

In setup transaction, when receiv ed device request

from host, 8Byte request is always stored into f our

resistors.

When request data is receiv ed correctly ,sends back

ACK packet to host and at the same time, occurs

interrupt to CPU and urge CPU to read request.

In out transaction, after M66290A received OUT

token packet, host transmits data packet.

If packet of maximum packet size or short packet

is stored into the endpoint FIFO of M66290A, and

moreov er, error is not occurred in that transf er,

M66290A transmits ACK packet to host and inf orms

CPU that the data was received by occurring buf f er

ready interrupt.

If USB protocol error is occurred in the host data

which received via USB bus, or if the endpoint FIFO

is full, M66290A does not transmit ACK packet to

host. Host knows that the error occurred because the

ACK packet does not come, and take a step such as

data resend.

4

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

CONTROL REGISTER TABLE

Below is the table of registers of M66290A.

Bit width of all register is 16bits.

shows the reset status by receiving USB reset.

" - " shows that the prev ious status is kept.

Write into reserv ed address is inhibited.

In reset item, "H/W" shows the reset status

by external RST input, "S/W" shows reset

status by USBE register, and "USB"

Address

Name

R/W

H/W

S/W

-

USB

00h

02h

USB Operation Enable Register

Remote Wake-up Register

Sequence Bit Clear Register

Reserved

R/W

0000h

-

0000h

04h

06h

08h

USB_Address Register

IsochronousStatus Register

Reserved

R

0000h

-

0Ah

0Ch to 0Eh

10h

R/W (note 2)

Interrupt Enable Register0

Interrupt Enable Register1

Interrupt Enable Register2

Interrupt Enable Register3

Interrupt Status Register0

Interrupt Status Register1

Interrupt Status Register2

Interrupt Status Register3

Request Register

R/W

R/W (note 2)

R

0000h

0008h

0000h

-

12h

0000h

-

14h

0000h

-

16h

0000h

-

18h

0000h

Note 2

1Ah

1Ch

1Eh

20h

0000h

-

R/W

R

0000h

-

22h

Value Register

R

24h

Index Register

R

26h

Length Register

R

28h

Control Transfer Control Register

EP0 Packet Size Register

Auto-response Control Register

Reserved

R/W

2Ah

2Ch

2Eh

30h

EP0_FIFO Selection Register

EP0_FIFO Control Register

EP0_FIFO Data Register

EP0 Continuous transmit Data Length

Reserved

R/W

R/W (note 2)

R/W

0000h

0800h

xxxx

-

32h

34h

36h

R/W

0000h

38h to 3Eh

40h

CPU_FIFO Selection Register

CPU_FIFO Control Register

CPU_FIFO Data Register

Reserved

R/W

R/W (note 2)

R/W

0000h

0800h

xxxx

-

42h

44h

46h

48h

DMA_FIFO Selection Register

DMA_FIFO Control Register

DMA_FIFO Data Register

Reserved

R/W

R/W (note 2)

R/W

0000h

0800h

xxxx

-

4Ah

4Ch

4Eh to 5Eh

60h

EP1 Configuration Register0

EP1 Configuration Register1

EP2 Configuration Register0

EP2 Configuration Register1

EP3 Configuration Register0

EP3 Configuration Register1

EP4 Configuration Register0

EP4 Configuration Register1

EP5 Configuration Register0

R/W

0000h

0040h

0000h

0040h

0000h

0040h

0000h

0040h

0000h

-

62h

64h

66h

68h

6Ah

6Ch

6Eh

70h

note 1 : Detail description is mentioned later.

note 2 : Some are read only.

5

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

Functional and register descriptions

And when use this function, device state shif ts to Address

state after outputs remote wakeup signal, so it is needed

to set up again the device state to Conf igured state.

Change of set up of device state can be done in S/W

control mode.

We explain about Function and register constitution of

M66290A dividing into f our items as follows.

(1) Sy stem control

(2) Interrupts

(3) Control transf er/enumeration

(4) Endpoints and FIFO control

Remote wakeup signal is a signal to set USB bus to idle

state after output K-state of 10ms length.

(1) System control

If this remote wakeup f unction is set up immediately af ter

detected suspend, USB bus idle state is kept f or 2ms and

then shif ts to K state output. (Because USB bus idle state

must be kept for 5ms minimum until transmit of remote

wakeup signal, on the other hand af ter detect suspend,

USB idle state is continued f or 3ms)

CLOCK

Clock of 48MHz is needed for internal operations

of M66290A.

Built in PLL enables to input external clock of 6/12/

24/48MHz. Selection of it is realized by the XTAL

of "USB Operation Enable Register".

When use external clock of 48MHz, PLL is not

needed, so set to PLL operation disable.

Sequence toggle bit clear function

In each endpoint of EP0 to EP5, data PID can be reset

independently and also can appoint PID of DATA0.

By this f unction, management of sequence toggle bit

in transf er af ter reset PID, is done by H/W automatically .

Built in oscillation circuit enables to supply clock

by self oscillation.

To set the "USB Operation Enable Register", it can

be set the device to standby state. Oscillation is

halted (clock input halted) by XCKE, PLL operation

is halted by PLLC, and clock supply to USB block

is halted by SCKE.

Error inf ormation in isochronous transf er

In isochronous transf er there is not retry f unction of

transmit/receiv e, because the handshake f rom receiv er

to transmitter is not returned not to disturb the time

equivalent data transf er.

To prev ent unstable behavior by unstable clock,

clock supply to USB block must be obey ed the

process, that is, enables clock input by XCKE, wait

until oscillation stabilized, start PLL by PLLC, wait

until oscillation stabilized (less than 1ms), and start

clock supply to USB block by SCKE.

M66290A has enough inf ormation f unction which enables

firmware to manage incorrect transfer in case of transfer

error occurred in isochronous transf er.

Inf ormation which M66290A can inf orm is, over run

error, under run error, receiv ed data error (CRC error,

bit stuf f ing error), and f rame number.

RESET

S/W reset by the register set (USBE), dif f erent from

the hardware reset, keeps the value of register of

USB operation enable register, FIFO relational

register, control transfer relational register,endpoint

setting register, and so on.

Sof tware control mode

In sof tware control mode, it is av ailable to set up (write)

from CPU as f ollows, USB_Address register (USB_Addr),

device state register (DVSQ), control transf er stage

register (CTSQ).

And in USB reset (when more than 2.5us of SE0 state

is continued on D+, D- terminal), the v alue of register

is kept except f or "Interrupt Status Register 0" and

"USB_Address Register"

Normally, use this mode with OFF.

(1) In case of crystal oscillation

C1

As to details of reset state, see each item of register.

Xin

XTAL

D+ pull-up resistor control function

M66290A

Xout

Rf

To set the register, external TrON output is controlled

and can control the ON/OFF of pull-up resistor

(1.5kohm) on USB D+ line.

Rd

C2

Place the parts as near the terminal as possible

(2) In case of external clock input

Remote wakeup function

When dev ice is in suspended state, outputs remote

wakeup signal and can cancel suspended state to receive

resume from USB.

clock input

Xin

M66290A

Remote wakeup function is only ef f ectiv e in Suspended

state in which device state shifts f rom Configured state,

so don't use to other device state.

open

Xout

Figure 1. Xin and Xout connections

6

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(1-1) USB Operation Enable Register (Address : 00h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

USBPC

SCTR

XCKE PLLC

XTAL[1:0]

SCKE

Tr_on[1:0]

USBE

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

0 : Oscillator disable (clock input disable)

1 : Oscillator enable (clock input enable)

15

14

XCKE

PLLC

Oscillator enable

0

-

0 : PLL disable

1 : PLL enable

PLL control

W/R

0

-

When use external clock of 48MHz, set to PLL disable.

00 : 1/1 division (external 48MHz input)

10 : 1/2 division (external 24MHz input)

01 : 1/4 division (external 12MHz input)

11 : 1/8 division (external 6MHz input)

13, 12 XTAL[1:0]

Crystal select

W/R

00

0

-

Internal clock

enable

0 : Internal clock (sck) disable

1 : Internal clock (sck) enable

11

10

SCKE

0 : USB transceiver disable

1 : USB transceiver enable

USB transceiver

power control

USBPC

0

In suspend state, resume signal can be received even if USB

transceiver disabled.

X0 : TrON port ="Hi-Z"

01 : TrON port ="L"

Tr_on

[1:0]

Tr_on output

control

11 : TrON port ="H"

9, 8

W/R

00

-

This fields selects TrON output state, and it is effective when

external Vbus input is "H" level (5V). If external Vbus input is "L",

these bits can be set but TrON output does not operate.

7 to 2 Reserved

Write/Read "0"

Software control

mode

0 : Normal Operation

1 : Software Control Mode Operation

1

0

SCTR

USBE

W/R

0

-

USB module

enable

0 : USB module disable (S/W Reset)

1 : USB module enable

(1-2) Remote Wake-up Register (Address : 02h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

WKUP

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

15 to 1 Reserved

Write/Read "0"

When CPU write "1" to WKUP for remote wake-up, M66290A outputs

K-State for 10ms, and return to Bus Idle-State.

(Remote wake-up signal)

0

WKUP

Remote wake-up

W/R

0

-

This bit returns to "0" automatically after suspend is canceled.

If "1" is written into this bit after detected suspend, bus idle state is kept

for 2ms and after then shifts to K state output.

7

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(1-3) Sequence Bit Clear Register (Address : 04h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SQCLR[5:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

15 to 6 Reserved

Write/Read "0"

When write "1" into the bit which is correspond to the number

of endpoint, sequence toggle bit of that endpoint is cleared

and appoint the DATA0 by the data PID of next transmission.

Write "1" into the bit after set the response PID of the endpoint, which

5 to 0 SQCLR Sequence toggle bit clears sequence toggle bit, to NAK("00") .

[5:0] clear

Transfers After the transfer appointed, sequence toggle bit is controlled

W/R 00h 00h

-

by H/W.

In USB reset, Sequence toggle bit of each endpoint is not cleared.

If "0" is written into this bit, flag is not changed.

Read data of this bit is always "0".

(1-4)USB Address Register (Address : 08h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

USB_Addr[6:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

15 to 7 Reserved

Write/Read "0"

USB address which is assigned by host is stored.

USB_

6 to 0

USB_Address

register

After stored the address, transaction is done only to the token packet

which is transmitted to this address.

Addr

R

00h 00h 00h

[6:0]

(If S/W control mode is set, write operation is available)

8

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(1-5) Isochronous Status Register (Address : 0Ah)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

OVRN CRCE

FMOD

FRNM[10:0]

Reset

Bit

Name

Function

W/R

Name

H/W S/W USB

In isochronous transfers (OUT/IN), when over-run or under-run is

occurred to the endpoint buffer, this flag is set at the timing of the

receive end of the OUT/IN token packet.

Over run is occurred when delayed to read the received data from

the endpoint buffer, and means that could not received. Over run is

occurred when the direction of transmission is OUT.

Also the received data has CRC or bit stuffing error, this flag is set.

Under run is occurred when delayed to write the transmit data into the

endpoint buffer, and means that could not transmitted. Under-run is

occurred when the direction of transmission is IN.

15

OVRN

Over run error

W/R

0

-

When a state above is occurred, endpoint buffer notready interrupt is

occurred.

When "0" is written, status flag is cleared.

When "1" is written, flag is not changed.

In isochronous transfers(OUT), if the received data has CRC or

bit stuffing error, this flag is set at the timing of the end of transaction.

When a state above is occurred, endpoint buffer notready interrupt is

14

CRCE Receive data error occurred.

W/R

0

-

When "0" is written, status flag is cleared.

When "1" is written, flag is not changed.

Write/Read "0"

13 to 12 Reserved

Select the renewal timing of the flame number to be stored

to FRNM[10:0].

Frame number

mode

11

FMOD

W/R

0

-

0 : Renew the flame number when SOF is received .

1 : In isochronous transfer, renew the flame number at the

timing of the end of transaction.

Stores the flame number.

FRNM

[10:0]

10 to 0

Frame number

The timing to renew the stored flame number is selectable by set

FMOD.

R

000h 000h

9

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(2) Interrupts

Resume detect interrupt (RESM)

There are eight factors of interrupt to CPU.

When interrupt occurred, the factor can be known to

ref er to "Interrupt Status Register 0" and "Interrupt

Status Register 1".

If device state is in suspended state and resume interrupt

enable f lag is set, interrupt occurs when USB bus state

is changed ("J" to "K" or "SE0").

This interrupt can be occurred even if the internal

clock(sck) is halted. To clear the status f lag, set the

internal clock(sck) in operation and then write "0". If the

internal clock(sck) is halted, status f lag can not be

cleared.

These interrupts can be set of its enable/disable

independently to set "Interrupt Enable Register 0"

and "Interrupt Enable Register 1".

If disable is set, interrupt is not occurred but interrupt

status flag is set.

SOF detect interrupt (SOFR)

Interrupt occurs when detect SOF.

Each factor of interrupt is shown in the table below,

and also describes below the interrupt conditions and

how to deal with the interrupt.

Device state transition interrupt (DVST)

Vbus (connect/shut down) interrupt (VBUS)

M66290A manages the device state by H/W.

It manages Powered, Default, Address, Conf igured, and

Suspended state. Dev ice state can be known to ref er to

"Interrupt Status Register 0".

Interrupt occurs when Vbus input state is changed

(both "L" to "H" and "H" to "L").

To know Vbus input state, conf irm the Vbus bit of

interrupt status register 0. Conf irmation of Vbus bit

must be done after enabled internal clock operation.

This interrupt can be occurred even if the internal

clock(sck) is halted. To clear the status f lag, enables

the internal clock(sck) in operation and then write "0".

If the internal clock(sck) is halted, status flag can not

be cleared.

As to dev ice state shif t, see the item of "Device state

shift" in "(3) Control transf er/emulation" in the latter part.

Device state transition interrupt occurs when dev ice state

shifted. The number of f actors is f our, that is, USB bus

reset detect, suspend detect, execution of "Set Address",

and execution of "Set Configuration".

USB reset is detected when SE0 state over 2.5us is

continued on D+, D- terminal.

This interrupt is usef ul to detect connect/shut-down of

USB for prepareration/close of USB transf ers.

Suspend is detected when idle state over 3ms is

continued on D+, D- terminal.

Summary of interrupts

Status bit

VBUS

Name

Abstract of interrupt f actor

Relational status bit

Vbus

Vbus interrupt

Change of the Vbus input

(connec/shut-down detect) (both "L" to "H" and "H" to "L")

RESM

SOFR

Resume detect interrupt

SOF detect interrupt

Resume signal receiv ed in suspended

Received SOF

device state transition

interrupt

Shif t of dev ice state

DVSQ[2:0]

CTSQ[2:0]

DVST

CTRT

Control transf er

Stage shif t of control transfer

stage transition interrupt

In each endpoint, when data transmit of all buf f er

is ended and buf f er is empty , or in OUT transf er,

received packet which exceeds max packet size.

Endpoint buf f er

EPB_EMP_OVR[5:0]

BEMP

empty /size-ov er interrupt

Endpoint buf f er not ready When buf f er is in not ready state (SIE cannot read

EPB_NRDY[5:0]

EPB_RDY[5:0]

INTN

INTR

interrupt

and write) to IN/OUT token of each endpoint.

Endpoint buf f er ready

interrupt

When buf f er of each endpoint became ready

(read enable/write enable)

10

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

Each of "Set Address" and "Set Configuration" execution

detects the device state shif t by analyzing the dev ice

request in control transfer.

Endpoint buffer not ready interrupt (INTN)

When the buf f er is in not ready state to IN/OUT token

of each endpoint, interrupt occurs at the timing of token

packet receive end.

Each of these f our f actors can be set of its interrupt to

enable or disable by setting the corresponded bit of

interrupt enable register 0.

By ref er to EPB_NRDY[5:0] of interrupt status register 1,

it can be known which endpoint occurred the interrupt.

For example by using this interrupt, when USB bus reset

is detected, a step to USB bus is av ailable and when

suspend is detected, a step to shif t dev ice to low power

consumption.

If endpoint is set to isochronous transf er, when over-run/

under-run error is occurred, interrupt occurs at the timing

of token packet receive end.

And if it is set to isochronous (OUT), if receiv ed data

has

Control transfer stage transition interrupt (CTRT)

M66290A manages the sequence of control transf er

by H/W.

error such as CRC error, interrupt occurs at the timing of

transaction end.

Each stage of control transf er, such as setup stage,

data stage, and status stage can be known to ref er to

the "Interrupt Status Register 0".

The v ariety of error in isochronous transf er is known to

ref er "Isochronous Status Register".

Control transf er stage transition interrupt is occurred

when the control transf er stage is shif ted.

There are f ive f actors, that is, setup stage end,

control write transf er stage shift, control read transfer

stage shif t, control transfer end, and control transf er

sequence error.

Endpoint buffer ready interrupt (INTR)

Interrupt occurs when the buf f er of each endpoint

became ready (read/write is av ailable).

It can be known which endpoint occurred the interrupt

to ref er EPB_RDY[5:0] of interrupt status register 1.

According to the endpoint and its access mode, the

factor of interrupt is dif f erent as follows.

Except f or setup stage, Each of these f our factors can

be set of its interrupt to enable or disable by setting the

corresponded bit of interrupt enable register 0.

As to control transfer sequence error which can be

recognized by H/W, ref er to "Control transfer stage

shift" in the item of "(3) Control transf er/enumeration"

in the latter part.

1. In case of EP0

Interrupt occurs when receive (OUT) buf f er of endpoint

0 became ready .

If it is set to control write continuous receiv e mode,

when continuous receiv e of 255 bytes ended or when

received short packet, interrupt occurs.

Interrupt is not occurred even if the transmit buf f er

became ready .

Endpoint buffer empty/size-over interrupt (BEMP)

Interrupt f actor is dif f erent by transf er direction of

endpoint.

2. In case of EP1 to EP5, when CPU access

Interrupt occurs when the buf f er of each endpoint

became ready .

1. In case of transf er direction is IN

In each endpoint, interrupt occurs when transmission

ended of all data which is stored in the buf f er.

By this interrupt, when endpoint is set to double buf f er,

end of data transmission of all data of the buf f er can

be known.

3. In case of EP1 to EP5, when DMA access

If the transf er direction is set to OUT, interrupt occurs

when received short data packet and then ended DMA

transf er.

And also can know the end of data transmission of

control read transf er in endpoint 0 (EP0).

Interrupt is not occurred if the transf er direction is set

to IN.

2. In case of transf er direction is OUT

In each endpoint, interrupt occurs in data packet

receive when receiv ed packet which exceeds the

maximum packet size.

By ref er to EPB_EMP_OVR[5:0] of interrupt status

register, it can be known which endpoint occurred the

interrupt.

11

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

Figure 2. shows the examples of interrupt output timing

(1) Endpoint buf f er ready interrupt (ex.OUT transaction)

OUT token packet

Data packet

DATA

Hand shake packet (ACK)

SYNC

EOP

CRC

PID Addr Endp CRC

SYNC PID

PID EOP

USB

Buf f er becomes ready (read enable)

and interrupt occurs

INT output

(2) Endpoint buf f er not ready interrupt (ex.OUT transaction)

OUT token packet

Data packet

DATA

Hand shake packet (NAK)

SYNC

EOP

CRC

PID Addr Endp CRC

SYNC PID

PID EOP

USB

Buf f er is in not ready (receiv e disable)

and interrupt occurs

INT output

(3) Endpoint buf f er not ready interrupt (ex.IN transaction)

IN token packet

Hand shake packet (NAK)

SYNC

EOP

SYNC

PID EOP

PID Addr Endp CRC

USB

Buf f er is in not ready (transmit disable)

and interrupt occurs

INT output

Figure 2. Examples of interrupt output timing

12

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(2-1) Interrupt Enable Register 0 (Address : 10h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

BEMPE

VBSE RSME SOFE DVSE CTRE

INTNE INTRE URST SADR SCFG SUSP WDST RDST CMPL SERR

Reset

Bit

15

14

Name

Function

W/R

Name

VBSE

H/W S/W USB

Vbus interrupt

enable

0 : Disable

1 : Enable

0

-

Resume interrupt 0 : Disable

RSME

SOFE

DVSE

CTRE

enable

1 : Enable

SOF interrupt

enable

0 : Disable

1 : Enable

13

12

11

W/R

0

-

Device state

0 : Disable

1 : Enable

interrupt enable

Control transfer

interrupt enable

0 : Disable

1 : Enable

Endpoint5-0 buffer

empty/size error

interrupt enable

0 : Disable

1 : Enable

10

9

BEMPE

INTNE

W/R

0

-

Endpoint5-0 buffer

not ready

0 : Disable

1 : Enable

interrupt enable

Endpoint5-0 buffer

ready

0 : Disable

1 : Enable

8

7

INTRE

URST

W/R

0

-

interrupt enable

USB reset detect If this bit is "1", then the DVST flag is set when detected USB reset.

Set Address

6

5

4

SADR

SCFG

SUSP

If this bit is "1", then the DVST flag is set after executed SetAddress.

execute

W/R

0

-

Set Configration

If this bit is "1", then the DVST flag is set after executed SetConfigration.

execute

Suspend

If this bit is "1", then the DVST flag is set when detected suspend.

detect

Control write

If this bit is "1", then the CTRT flag is set when shifted to status stage

3

WDST

transfer status

in control write transfer.

stage

W/R

0

-

Control read

If this bit is "1", then the CTRT flag is set when shifted to status stage

2

1

0

RDST

CMPL

SERR

transfer status

in control read transfer.

stage

W/R

0

-

Control transfer

complete

If this bit is "1", then the CTRT flag is set when control transfer

completed (when the status stage completed normally).

Control transfer

sequence error

If this bit is "1" then the CTRT flag is set when error

occurred in the sequence of control transfer.

13

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(2-2) Interrupt Enable Register 1(Address : 12h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

EPB_RE[5:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

15 to 6 Reserved

Write/Read "0"

Endpoint5-0 buffer 0 : Disable

EPB_RE

5 to 0

[5:0]

ready

1 : Enable

The number of endpoint is correspond to each bit one by one.

W/R 00h 00h

-

interrupt enable

(2-3) Interrupt Enable Register 2 (Address : 14h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

EPB_NRE[5:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

15 to 6 Reserved

Write/Read "0"

Endpoint5-0 buffer 0 : Disable

EPB_NRE

5 to 0

[5:0]

not ready

1 : Enable

The number of endpoint is correspond to each bit one by one.

W/R 00h 00h

-

interrupt enable

(2-4) Interrupt Enable Register 3 (Address : 16h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

EPB_EMPE[5:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

15 to 6 Reserved

Write/Read "0"

Endpoint5-0 buffer 0 : Disable

EPB_

5 to 0

EMPE

[5:0]

empty/size error

interrupt enable

1 : Enable

The number of endpoint is correspond to each bit one by one.

W/R 00h 00h

-

14

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(2-5) Interrupt Status Register 0 (Address : 18h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

VBUS RESM SOFR DVST CTRT BEMP INTN INTR

Vbus

DVSQ[2:0]

VALID

CTSQ[2:0]

Reset

Bit

15

Name

Function

W/R

Name

VBUS

H/W S/W USB

This bit changes to "1" when Vbus input changed both "0" to "1" and

"1" to "0".

As to the Vbus input state, confirm to see the bit of Vbus input port.

This bit is set even if the internal clock (sck) is in halt state.

If "0" is written after enabled internal clock as operation, status flag is

cleared. But if internal clock is in halt state, flag is not cleared.

If "1" is written, flag is not changed.

Vbus interrupt

W/R

0

-

This bit changes to "1" when USB bus state changed("J" to "K" or "SE0")

under the condition that resume interrupt enable flag is set.

This bit is set even if the internal clock (sck) is in halt state.

If "0" is written after enabled internal clock as operation, status flag is

cleared. But if internal clock is in halt state, flag is not cleared.

If "1" is written, flag is not changed.

14

Resume detect

interrupt

RESM

SOFR

DVST

W/R

0

-

This bit changes to "1" when detected SOF.

If "0" is written, status flag is cleared.

If "1" is written, flag is not changed.

SOF detect

interrupt

13

12

This bit changes to "1" when device state shifted.

There are four factors, that is, USB reset detect, suspend detect,

"Set Address" execution, and "Set Configuration" execution.

These four factors can be masked by the corresponded bit of

"Interrupt Enable Register0" .

Device state

1

transition interrupt

If "0" is written, status flag is cleared.

If "1" is written, flag is not changed.

This bit changes to "1" when the stage of control transfer is shifted.

There are five factors, that is, setup stage end, control write transfer

status stage shift, control read transfer status stage shift, control transfer

end, and control transfer sequence error.

Control transfer

stage transition

interrupt

11

CTRT

W/R

0

-

Four factors, except for setup stage end, can be masked by the

corresponded bit of the "Interrupt Enable Register0".

If "0" is written, status flag is cleared.

If "1" is written, flag is not changed.

The factor is different by the direction of the transfer of each endpoint.

In each endpoint, this bit changes to "1" when the transmission of all

stored data is completed (direction:IN) and when received the packet

Endpoint5-0 buffer which is exceeded to maximum packet size (direction:OUT).

10

BEMP

empty/size error

interrupt

The endpoint which occurs the interrupt can be checked to see the

EPB_EMP_OVR[5:0].

R

0

-

This flag is cleared to clear the status flag of EPB_EMP_OVR[5:0].

15

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

Reset

W/R

Bit

Name

Function

Name

H/W S/W USB

This bit changes to "1" at the timing of token packet receive end when

buffer respond NAK, of its not ready state, to IN/OUT token of each

Endpoint5-0 buffer endpoint.

not ready

9

INTN

R

0

-

interrupt enable

The endpoint which occurred the interrupt is checked to see

EPB_NRDY[5:0].

This flag is cleared to clear the status flag of EPB_NRDY[5:0].

This bit changes to "1" when the buffer of each endpoint

became ready (read/write enable).

Endpoint5-0 buffer

ready

The endpoint which occurred the interrupt is checked to see

EPB_RDY[5:0].

8

INTR

R

0

-

interrupt enable

This flag is cleared to clear the status flag of

EPB_RDY[5:0].

Input data from external Vbus is stored.

0: Vbus input port is "L"

7

Vbus

Vbus input port

1: Vbus input port is "H"

R

Ext. Ext. Ext.

External Vbus input data is latched by the positive edge of internal clock.

Refer to this bit after enabled internal clock operation.

000: Powered State

001: Default State

010: Address State

011: Configured State

1xx: Suspended State

Device state can be known.

DVSQ

[2:0]

6-4

Device state

As to the device state shift, refer to Fig.5 in the later part.

When detect USB reset, this becomes 001: Default state automatically.

When detect suspend, this becomes 1xx: Suspended state automatically.

Whatever the automatic response mode is, this becomes 010: Address

state after executed Set_Address request, and becomes 011: Configured

state after executed Set_Configuration request.

R

000 000 001

(Write operation is available when S/W control mode is set)

This bit changes to "1" when received setup packet.

This flag does not the factor of interrupt.

When "0" is written, status flag is cleared .

When "1" is written, flag is not changed .

Setup packet

detect

3

VALID

W/R

0

-

000 : Idle or Setup stage

001 : Control read transfer data stage

010 : Control read transfer status stage

011 : Control write transfer data stage

100 : Control write transfer status stage

101 : Control write no data transfer status stage

110 : Control transfer sequence error

111 : Not assigned

CTSQ

[2:0]

Control transfer

Stage

2-0

R

000 000

-

Can be seen the stage of control transfer.

As to the stage shift of control transfer, refer to Fig.5 in the later part.

(Write operation is available when S/W control mode is set)

16

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(2-6) Interrupt Status Register 1 (Address : 1Ah)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

EPB_RDY[5:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

15 to 6 Reserved

Write/Read "0"

When buffer becomes ready (read/write enabled) to each endpoint,

the bit which corresponds to the number of endpoint changes to "1".

The factor of the interrupt is different by the transfer condition of each

endpoint.

1. As to EP0

This bit changes to "1" when receive buffer(OUT) became ready

(read enabled) in control write transfer.

If it is set to control write continuous receive mode or completed

receiving of the data of 255Bytes or received short data packet,

this bit changes to "1".

This bit is not changed even if the transmission buffer(IN) became

ready (write enabled) in control read transfer.

The ready state of the transmission buffer(IN) can be known by the

buffer empty interrupt.

2. As to EP1 to EP5, when CPU access

This bit changes to "1" when each buffer of each endpoint became

ready(read/write enabled).

This bit also changes to "1" when set the direction of the transfer to IN

in initialization.

Endpoint5-0 buffer

ready

EPB_RDY

5 to 0

[5:0]

R

00h 00h

-

3. As to EP1 to EP5, when DAM access

interrupt

If the direction of the transfer is set to OUT, this bit changes to "1"

when received short data packet and then completed DMA transfer

of received data.

In this case, clear is only available to write the BCLR command.

This bit is not changed if the direction of transfer is set to IN.

Clearance of this flag is different by the transfer direction of endpoint.

1. If the transfer direction is OUT

After set the number of the object endpoint to the "FIFO Selection

Register", write BCLR command or read all data of the buffer, then

flag is cleared.

(When DMA access, clearance is only available to write BCLR

command)

2. If the direction is IN

After set the number of the object endpoint to the "FIFO Selection

Register", write IVAL command or write data into the buffer of maximum

packet size (buffer size, if in continuous transmission mode ), then

flag is cleared.

17

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(2-7) Interrupt Status Register 2 (Address : 1Ch)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

EPB_NRDY[5:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

15 to 6 Reserved

Write/Read "0"

To IN/OUT token of each endpoint, if the set of response PID is not

NAK("00") and if buffer is in not ready state (receive/transmit disabled),

the bit which corresponds to the number of endpoint changes to "1".

(If the endpoint is control transfer or bulk transfer or interrupt transfer,

NAK response is executed)

EPB_

Endpoint5-0 buffer

not ready

If the endpoint is set to isochronous transfer, M66290A does not execute

NAK response, but when over-run or under-run of endpoint buffer

occurred, this bit changes to "1" at the timing of token packet receive end.

If it is set to isochronous (OUT), and if received data has error such as

CRC, this bit changes to "1" at the timing of transaction end.

5 to 0

NRDY

[5:0]

W/R 00h 00h

-

interrupt

When "0" is written, status flag is cleared.

When "1" is written, flag is not changed.

18

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(2-8) Interrupt Status Register 3 (Address : 1Eh)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

EPB_EMP_OVR[5:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

15 to 6 Reserved

Write/Read "0"

When factors below are occurred to each endpoint, the bit which

corresponds to the number of endpoint, changes to "1".

1. If the transfer direction is IN

In each endpoint, when transmission completed of all data which stored

in buffer, c

By this interrupt, if endpoint is set to double buffer, it can be known that

transmission of all data of buffer is completed.

EPB_

Endpoint5-0 buffer And also by this interrupt, it can be known that transmission of EP0 is

EMP_

5 to 0

empty/size error

interrupt

completed.

W/R 00h 00h

-

OVR

[5:0]

2. If the direction is OUT

In each endpoint, when received data which exceeds the maximum

packet size in data packet receive, the bit which corresponds to the

number of endpoint changes to "1".

When "0" is written, status flag is cleared.

When "1" is written, status flag is not cleared.

19

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(3) Control transfer / Enumeration

If it is control read transfer, data stage is IN transaction

and CPU prepares f or data transmit (write into endpoint

FIFO) at the timing of interrupt in setup stage.

M66290A is equipped with control transf er continuous

transmit and receive function. Af ter ended data stage,

it proceeds to status stage.

In control transf er, there are setup stage, data stage,

and status stage.

M66290A manages stage and inf orm CPU the stage

shift by interrupt. CPU do stage transact of control

transf er according to the interrupt f actor.

Setup stage

Status stage

In setup stage, 8Bytes request (setup data) of setup

transaction data packet which transf erred f rom host

is stored into f our registers automatically (Request,

Value, Index, and Length register).

Status stage executes receiv e/transmit of Null data

(data length 0), in both control write and control read

transf er. Receive/transmit of Null data is possible to

set control transf er complete enable bit (CCPL) after

ended setup stage.

Except f or dev ice state shif t request (Set Address and

Set Configuration) which can cope with by the automatic

response control function, analysis (decode) and

execution of contents of request must be done by CPU.

By executing the request, it proceeds to data stage or

to status stage.

Control transf er complete enable bit is reset when

received setup packet.

Control transf er executes data transf er using EP0.

To both control read and control write, buf f er size of

EP0 can be set by a unit of 64By tes by "Control

Transf er Control Register".

Data stage

Access to EP0_FIFO data register must be done by

CPU access. DMA transfer can not be set.

Data stage executes IN transaction or OUT transaction

according to the contents of request. If it is control

write transfer, data stage is OUT transaction and CPU

prepares f or data receiv e at the timing of interrupt in

setup stage and reads the received data from endpoint

FIFO when data receiv e ended.

Figure 3. shows the abstract of enumeration

operations.

Device state

M66290A

Device f irmware

Clock ON

Initializing

Tr ON

Idle

(Powered)

USB bus connect

Vbus interrupt

Full speed

device recognition

Default

state

USB reset receiv e

DVST interrupt

USB reset

USB request

(Control transf er)

Get xx command

CTRT interrupt

Set response data

Set Address

CTRT/DVST interrupt

(Automatic response available)

Address

state

USB request

Get xx command

CTRT interrupt

Set response data

Set Configuration

CTRT/DVST interrupt

(Automatic response available)

Configured

state

USB request

Set xx command

CTRT interrupt

Read receiv ed data

Figure 3. Abstract of enumeration operations

20

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

Auto-response control function

which extend plural of transaction.

M66290A has auto-response f unction to dev ice

state transition request (Set Address and Set

Configuration)in control transf er.

If continuous transfer mode is set, it can transfer the

transmit which data length is set to "EP0 Continuous

Transmit Data Length Register", without

By the set of "Auto-response Control Register",

auto-response mode to Set Address and to

Set Configuration can be set individually .

If the auto-response mode is set, device state

transition request can be ended without occurring

interrupt.

occurring interrupt.

Control read buf f er can be set up to 256Bytes at a unit

of 64By tes. Control write buf f er can receive continuously

up to 255By tes, so secure the area of 256Bytes.

Abstract of control transfer operations

Continuous transfer function

Figure 4. shows examples of abstraction of control

transf er operations.

M66290A has continuous transf er f unction to

transmit/receiv e continuously of requested data

Transf er direction of packet :

M66290A to Host

Host to M66290A

(1) Continuous receive mode (control write transfer)

INT1:

Setup

stage

INT1

Setup token

OUT token

Data packet

CTRT interrupt (setup stage completion)

Read EP0 request and conf irm the contents of request.

ACK

NAK

ACK

Data packet

By receiv ing SETUP token packet, response PID of

EP0 is set to NAK automatically.

Data

stage

By the set of response PID to BUF (buf f er control),

data receive starts.

INT2:

INT2

CTRT interrupt (control write transfer status stage shif t)

Confirm the number of by te of received data and read

the received data.

IN token

NAK

Status

stage

NAK

By the set of CCPL, transmit the Null data.

Interrupt, which is occurred by control write transf er

status stage shift and by control transf er completion is

dif f erent by interrupt enable setting.

Null data packet

ACK

(2) Continuous transmit mode (control read transfer)

INT1:

Setup

stage

INT1

Setup token

IN token

Data packet

NAK

CTRT interrupt (setup stage completion)

Read EP0 request and conf irm the contents of request.

ACK

By receiv ing SETUP token packet, response PID of

EP0 is set to NAK automatically.

NAK

Executes transmit data write which is requested,

set transmit data length, set response PID to BUF

(buf f er control), and data transmit is started.

Data

stage

Data packet

ACK

Data packet

IN token

ACK

By the set of CCPL, ACK handshake is executed

when received Null data.

Interrupt which is occurred by control read transf er

status stage shift and by control transf er completion is

dif f erent by interrupt enable setting.

Status

stage

Null data packet

OUT token

Figure 4. Examples of abstract of control transf er operations

21

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USB DEVICE CONTROLLER

other state and to Set_Address request which Dev iceAddess

is not equal to 01h to 7Fh, auto-response is not executed.

To Set_Conf iguration request, auto-response is executed

to Set_Conf iguration request (Conf igurationValue is not equal

to 0) which device state is in Address state and to

Set_Configuration request (ConfigurationValue=0) which device

state is in Conf igured state.

Device state transition

M66290A manages dev ice state by H/W.

It manages Powered, Default, Address, Conf igured,

and Suspended state of USB dev ice state.

To Set_Address and Set_Conf iguration request in

auto-response mode, transf er can be completed

without occurring interrupt to CPU.

To other state and to Set_Conf iguration request which is

dif f erent of its Conf igurationValue from the value abov e,

auto-response is not executed.

To Set_Address request, auto-response is executed to

Set_Address request (Dev iceAddess=01h

to 7Fh) which dev ice state is in Default state, and to

Suspend detection (DVST)

Powered

state

Suspended

state

(DVSQ="100")

(DVSQ="000")

Resume detection (RESM)

USB reset detection (DVST)

Suspend detection (DVST)

Default

state

(DVSQ="001")

Suspended

state

(DVSQ="101")

Resume detection (RESM)

Set Address execution (DVST)

(DeviceAddress=01h to 7Fh)

*Can be set to auto-response

Suspend detection (DVST)

Default

state

(DVSQ="010")

Suspended

state

(DVSQ="110")

Resume detection (RESM)

Set Configuration execution (DVST)

(Conf iguration Value is not equal to 0)

*Can be set to auto-response

Set Configuration execution (DVST)

(Conf iguration Value is not equal to 0)

*Can be set to auto-response

Suspend detection (DVST)

Default

state

Suspended

state

(DVSQ="111")

(DVSQ="011")

Resume detection (RESM)

Figure 5. Device state shift

22

MITSUBISHI <DIGITAL ASSP>

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USB DEVICE CONTROLLER

Control transfer stage transition

3. OUT token packet receive in control read data stage.

(OUT token packet receiv e which did not do data transf er

once to IN token packet in data stage).

M66290A manages control transfer sequence by H/W.

There are setup stage, data stage, and status stage in

control transf er stage, as shown in f igure 6. And when

stage shif ts, CTRT interrupt occurs.

4. IN token packet receive in control read status stage.

There are f ive f actors in CTRT interrupt, that is, setup

stage end, control write transf er status stage shift,

control read transf er status stage shif t, control transfer

end, and control transfer sequence error. And there are

seven errors as f ollows in control transfer sequence

error which can be detected by H/W.

5. Data packet receiv e except f or Null data in control

read status stage.

6. OUT token packet receive in control write no data

status stage.

7. Data receiv e which exceeds maximum packet size.

If H/W detected control transf er sequence error,

response PID is set to STALL("1x") automatically.

In control write data stage, it can not be recognized as

sequence error when receiv ed data packet which exceeds

request wLength v alue.

1. IN token packet receive in control write data stage

(In token packet receive which did not do ACK

handshake once to OUT token packet in data stage)

2. OUT token packet receive in control write status stage

Control

transf er

sequence

Error detected

error

Receive

setup packet

Receive short packet

ACK receiv e

(Control transfer

complete)

or Receiv e IN token

ACK transmit

(Setup stage complete)

(Control write transfer

Control

write

Control

write

status stage transition)

Setup

stage

status

stage

data

stage

Transmit short packet

or Receiv e OUT token

(Control read transfer

ACK receiv e

(Control transfer

complete)

ACK transmit

(Setup stage complete)

status stage transition)

Control

read

Control

read

status

stage

data

stage

ACK receiv e

(Control transfer

complete)

ACK transmit

(Setup stage complete)

Control

write

no data

status

stage

Figure 6. Stage shift of control transfer

23

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USB DEVICE CONTROLLER

(3-1) Request Register (Address : 20h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

bRequest[7:0]

bmRequestType[7:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

R

Name

bRequest

[7:0]

15 to 8

7 to 0

Request register This fields provides bRequest of the last setup packet received.

00h 00h

-

bmRequest

Type

RequestType

This fields provides bmRequest of the last setup packet received.

register

R

[7:0]

(3-2) Value Register (Address : 22h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

wValue[15:0]

Reset

Bit

Name

Function

W/R

R

Name

H/W S/W USB

wValue

[15:0]

15 to 0

Value register

This fields provides wValue of the last setup packet received.

0000h

-

(3-3) Index Register (Address : 24h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

wIndex[15:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

R

Name

wIndex

[15:0]

15 to 0

Index register

This fields provides wIndex of the last setup packet received.

0000h

-

(3-4) Length Register (Address : 26h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

wLength

Reset

H/W S/W USB

Bit

Name

Function

W/R

R

Name

wLength

[15:0]

15 to 0

Length register

This fields provides wLength of the last setup packet received.

0000h

-

24

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M66290AGP/FP

USB DEVICE CONTROLLER

(3-5) Control Transfer Control Register (Address : 28h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

CTRR

Ctr_Rd_Buf_Nmb[5:0]

CTRW

Ctr_Wr_Buf_Nmb[5:0]

Reset

Bit

Name

Function

W/R

Name

H/W S/W USB

Control read

Control read transfer continuous transmit mode is set

when "1" is written in this bit.

15

14

CTRR transfer continuous

transmit mode

W/R

0

-

Reserved

Write/Read "0"

Appoint the start number of the buffer which is used in control read

transfer by a unit of 64bytes.

Ctr_Rd_

Control read buffer

13 to 8 Buf_Nmb

[5:0]

The buffer is available from #00h to #2Fh.

W/R 00h

-

start number

When control read continuous transmit mode is set, it can

transmit continuously up to 255Bytes, so keep the area of the

buffer of 256Bytes (4 blocks).

Control write

When "1" is written, control write transfer continuous receive mode

is set.

7

6

CTRW transfer continuous

receive mode

W/R

0

Reserved

Write/Read "0"

Appoint the start number of the buffer which is used in control write

transfer by a unit of 64bytes.

Ctr_Wr_

Control write buffer The buffer is available from #00h to #2Fh.

5 to 0 Buf_Nmb

[5:0]

W/R 00h

-

start number

When control write continuous receive mode is set, it can receive

continuously up to 255bytes, so keep the area of buffer of 256bytes

(4 blocks).

(3-6) EP0 Packet Size Register (Address : 2Ah)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

EP0_MXPS[6:0]

Reset

Bit

Name

Function

W/R

Name

H/W S/W USB

15 to 7 Reserved

Write/Read "0"

Set the maximum value of data (byte) which transmit or receive in a

packet transfer.

EP0_MXPS

6 to 0

[6:0]

Max Packet size Set the value of wMaxPacketSize in request.

This bit must be set after set the response PID to NAK("00").

W/R 08h

-

25

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USB DEVICE CONTROLLER

(3-7) Auto-response Control Register (Address : 2Ch)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ASCN ATAD

Reset

Bit

Name

Function

W/R

Name

H/W S/W USB

15 to 2 Reserved

Write/Read "0"

When "1" is written into this bit, auto-response mode of

Set_Configuration request is set.

To the Set_Configuration request in auto-response mode,

transfer can be completed without occurring interrupt to CPU.

(Set of CCPL is not needed)

Set_Configuration

Auto-response

mode

Auto-response is done to the Set_Configuration request

(ConfigurationValue is not equal to 0) in Address device state

1

ASCN

W/R

0

-

and to the Set_Configuration request (ConfigurationValue is equal to 0)

in Configured state.

To the other state and to the Set_Configuration request which

ConfigurationVale is different from the value above, auto-response

is not done.

When "1" is written into this bit, automatic response mode of

Set_Address request is set.

To the Set_Address request in automatic response mode,

transfer can be completed without occurring the interrupt to

CPU. (Set of CCPL is not needed)

Set_Address

Auto-response

mode

0

ASTD

W/R

0

-

Automatic response is done to the Set_Address request (DeviceAddress

is equal to 01h to 7Fh) which device state is Default state.

To the other state and to the Set_Address request which DeviceAddress

is not equal to 01h to 7Fh, automatic response is not done.

(3-8) EP0_FIFO Selection Register (Address : 30h)

D15

D14

D13

D12

D11

D10

Octl

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RCNT

ISEL

Reset

H/W S/W USB

Bit

15

Name

Function

W/R

Name

If this bit is "1", every time when read EP0_FIFO register,the value of

ODLN register is counted down.

RCNT

Read count mode

0

-

14 to 11 Reserved

Write/Read "0"

If this bit is set to "1", data register of FIFO turns to 8-bit mode and

lower 8 bit[7:0] becomes enable when access the "FIFO Data Register"

FIFO access

8 bit mode

of endpoint.

10

Octl

W/R

0

-

When transmit data of odd number byte, data must be written in 8-bit

mode.

When read in 8-bit mode, set to 8-bit mode before data receive.

9-1

0

Reserved

ISEL

Write/Read "0"

0 : Control write (OUT) buffer select

1 : Control read (IN) buffer select

Buffer select

W/R

0

-

26

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USB DEVICE CONTROLLER

(3-9) EP0_FIFO Control Register (Address : 32h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

EP0_PID[1:0]

IVAL BCLR E0req CCPL

ODLN[7:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

Setting the response PID.

00 : NAK Whatever the buffer state is,do NAK handshake.

01 : BUF Response PID is selected by the state of buffer

and sequence toggle bit status.

(One of ACK, NAK, and DATA0/DATA1)

1x : STALL Do STALL handshake

EP0_PID

[1:0]

15 to 14

Response PID

1. When received Setup packet, turns to "00"(=NAK) automatically.

2. When received request (Set_Address, etc.) which is set to

automatic response, turns to "01"(=ACK) automatically after

completed the Setup transaction.

W/R 00

-

3. If sequence error occurred in control transfer,or received data

in control write transfer which exceed maximum packet size,

this turns to "1x"(=STALL) automatically.

If the control read buffer is selected, this becomes IN buffer

effective state flag.

When set to "1", it becomes to transmit data set state (SIE read enabled).

If data is written which exceeds to the maximum byte of maximum

packet size (MXPS), this bit is set to "1".

When short packet transmit, set this bit to "1" after wrote transmit data.

If the IVAL="1" and BCLR="1" is written at the same time,

IN buffer effective state flag is set.

13

IVAL

In buffer status

W/R

0

-

(This is effective to transmit 0 length data)

If the control readout) buffer is selected, it becomes OUT buffer

effective state status.

Status "1" shows that there is data which can be read.

This bit shows the effective value when E0req bit is "0".

If "1" is written, it is not changed.

If "0" is written, flag is not changed.

If "1" is written into this bit When the selected endpoint is set to IN, IN

buffer effective state flag and the data (byte) which is written are cleared.

If IVAL="1" and BCLR="1" is written at the same time, data is cleared

but IN buffer effective state flag is set.(This is effective to transmit 0

length data)

12

BCLR

Buffer clear

W/R

0

-

When "1" is written into this bit, if the selected endpoint is set to OUT,

OUT buffer effective state flag is cleared and read data is also cleared.

When "0" is written, this bit is not changed.

If this bit is "0", access to EP0_FIFO data register is enabled.

And when this bit is "0", IVAL and ODLN bit shows the effective value.

11

E0req

EP0_FIFO ready EP0_FIFO data register, when read or write, needs cycle time of

200ns (min).

R

1

-

(Continuous access at 5MHz is available)

27

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M66290AGP/FP

USB DEVICE CONTROLLER

Reset

W/R

Bit

10

Name

Function

Name

H/W S/W USB

To write "1" into this register, status stage of control transfer can be

completed.

If this bit is "1" and response PID is BUF("01"), Null data is transmitted

in control write transfer, and do response ACK in control read transfer

when received NULL data.

Control transfer

complete enable

CCPL

W/R

0

-

If this bit is "0", do response NAK in status stage.

This flag is reset to "0" when received setup packet.

9 to 8 Reserved

Write/Read "0"

Received data length(byte) can be read from this register.

If RCNT mode is set, every time when read EP0_FIFO data register,

it is counted down by -1(8-bit mode) or by -2(16-bit mode).

This bit shows effective value when E0req bit is "0".

Control write

receive

ODLN

7 to 0

R

00h

-

[7:0]

data length

(3-10) EP0_FIFO Data Register (Address : 34h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

EP0_FIFO[15:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

When read, this becomes to receive data FIFO register.

If it is set to 8-bit mode, lower 8 bit[7:0] is valid.

When write, this becomes to transmit data FIFO register.

If it is set to 8-bit mode, lower 8 bit[7:0] is valid.

EP0_FIFO

[15:0]

15 to 0

EP0_FIFO data

W/R xxxx

-

Both for read and write, cycle time of 200ns (min) is needed.

(Continuous access at 5MHz is available)

Read when IN buffer is selected or write when OUT buffer is

selected is inhibited.

(3-11) EP0 Continuous transmit Data Length (Address : 36h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDLN[7:0]

Reset

Bit

Name

Function

W/R

Name

H/W S/W USB

14-8 Reserved

Write/Read "0"

Set the control read continuous transmit data length (byte).

It can be set up to FFh (255bytes).

Control read

continuous transmit

data length

SDLN

7 to 0

In control read continuous transmit mode, write FIFO data (transmit data)

after set this register.

W/R 00h

-

[7:0]

This is available in control read continuous transmit mode.

28

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(4) Endpoint and FIFO control

To use with double buf f er constitution, 1kBy tes x2

maximum of buf f ering is realized.

Except f or EP0 for control transfer, M66290A can set

fiv e endpoints as EP1 to EP5.

Continuous receive mode can receiv e data packet

continuously up to the buf f er size which is set, or until

receives short packet. If the data to be receiv ed is data

packet of max packet size, it can receive continuously

up to the buf f er size without occurring interrupt to CPU,

and if the data is data packet (max packet size) which is

less than buf f er size, interrupt to CPU is not occurred.

In bulk transf er, when set max packet size as 64By tes,

buf f er size as 1024Bytes, and FIFO constitution as

double buf f er, when received data of max packet size

as 16 times (1024By tes), it became buf f er redried

enable) and urge to CPU by interrupt to read receiv ed

data. When receiv ed short packet, ends the continuous

receive and buf f er became redried enable).

Each of these f ive endpoints (EP1 to EP5) can be set to

bulk, interrupt, and isochronous transf er. And yet,

another constitution can conf igurated independently .

Below are the constitutions to be realized.

Built-in FIFO f or endpoint buf f er is 3kBy tes totally of its

memory capacity. This FIFO of 3kBytes can div ided

into each endpoint of EP0 to EP5 and to each endpoint,

can assign up to 1024Bytes (max) by a unit of 64Bytes.

Buf f er size of each endpoint must be set to ov er the

capacity which is set in maximum buf f er size.

In the buf f er size, which is set, by tes of maximum

packet size is used f or valid. (If set the buf f er size to

128By tes to the endpoint which maximum packet size

is set to 64Bytes, 64Bytes are valid)

Continuous transmit mode can transmit data packet

continuously up to buf f er size which is set. Short packet

transmit can be done to set IVAL flag. And it is needed

to set IVAL f lag to transmit a multiple data of maximum

packet size which is less than buf f er size.

We show setting examples to each of these buf f er of

EP0 to EP5 below, and next explain about continuous

transmit and receive function, FIFO control, DMA

transf er, and double buf f er.

Continuous transfer function

By set Null data transmit addition mode, when write a

multiple data of max packet size into buf f er and

transmit, Null data can be transmitted automatically

after the last packet is transmitted .

Continuous transf er function is to transmit/receive data

which extend plural transaction without occurring interrupt

to CPU.

For EP1 to EP5, this function is ef f ectiv e when transf er

type is bulk transf er.

In each endpoint, when continuous transf er mode is set,

it can transf er data up to the buf f er size which is set to

the endpoint without occurring interrupt to CPU.

Examples of endpoint FIFO setting

Memory

address

FIFO

Endpoint setting

number

EP0:Control write transfer

Buffer size:256Bytes

Control write continuous receive

mode(CTRW)

Construction of endpoint (EP1 to EP5) FIFO

00h to

03h

000h to

0FFh

Register

EP1 to EP5

Can be set to Bulk,

Interrupt, isochronous

transfer.

FIFO area:256Bytes(4 blocks)

Transfer type

EPi_TYP[1:0]

EP0:Control read transfer

Buffer size:256Bytes

Control read continuous transmit

mode(CTRR)

04h to

07h

100h to

1FFh

Transfer direction

EPi_DIR

Can be set to IN/OUT

Double buffer

(Toggle buffer)

FIFO area:256Bytes(4 blocks)

EPi_DBLB

Can be set

EP2:Interrupt transfer(IN)

Buffer size:64Bytes

FIFO area:64Bytes(1 block)

200h to

23Fh

08h

09h

Can be set

Continuous

transmit/receive

EPi_RWMD

(Effective in bulk transfer)

EP4:Interrupt transfer(OUT)

Buffer size:64Bytes

FIFO area:64Bytes(1 block)

240h to

27Fh

Can be set

EPi_Buf_siz[3:0] (Up to 1024bytes by

a unit of 64bytes)

Buffer size

EP3:Bulk transfer(IN)

Buffer size:64Bytes

Double buffer constitution(DBLB)

FIFO area:128Bytes(2 blocks)

0Ah to

0Bh

280h to

2FFh

Can be set to

NAK, STALL, and

BUF(buffer control).

Response PID

DMA transfer

EPi_PID[1:0]

EPi_DMAE

EPi_ACLR

0Ch to

0Fh

300h to

3FFh

Not used:256Bytes(4 blocks)

Can be set

Receive data

read and abandon

mode

EP1:Bulk transfer(OUT)

Buffer size:1024Bytes

Double buffer constitution(DBLB)

Continuous receive mode(RWMD)

FIFO area:2kBytes(32 blocks)

Can be set

10h to

2Fh

400h to

BFFh

Can be set

( 0 to 1023bytes)

Max packet size

EPi_MXPS[9:0]

29

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

DMA transfer

FIFO control

To endpoint of EP1 to EP5, 16bits width or 8bit width of

DMA

Access to endpoint buf f er of EP0 to EP5 is done by

three FIFO data registers. One is only f or EP0 and

Others are common to EP1 to EP5. Common data

registers are div ided into two, because accessing

is dif f erent, that is f or CPU access and for DMA

transf er. Which endpoint of EP1 to EP5 to be

accessed can be selected to set each FIFO

selection register.

transf er is available.

Each endpoint of EP1 to EP5 can be set to CPU access

mode or DMA access mode by set of "EPx Configuration

Register 1" mentioned later.

DMA transf er is realized to hand shake with external DMAC

and Dreq, Dack signal. Dreq is asserted when endpoint

buf f er, which is set to DMA transfer mode, became ready.

The means of Buf f er ready state is, if the endpoint

transf er

Accessing

Register name

Endpoint

EP0

EP0_FIFO

data register

CPU access

CPU_FIFO

data register

CPU access

DMA transf er

direction is set to Out (recive data from host) buf f er ready

means that in read enable state, if the endpoint transf er

direction is set to IN(transmit data to host) buf f er ready

means that in write enable state. Setting the transfer

direction can be done by "EPi Conf iguration Register 0" to

each endpoint.

EP1 to EP5

DMA_FIFO

data register

Each of three FIFO registers has f unctions as

follows. And these f unctions can be used to set

"Each FIFO Selection/Control Register".

Short packet transmission f unction

(IVAL : IN buf f er status bit)

When Dack comes f rom external DMAC after asserted

Dreq, Dreq is negated.

Transmit/receiv e buf f er clear f unction

(BCLR : Buf f er clear bit)

In DMA transfer, Dack is dealt equiv alently with CS signal

and DMA_FIFO address appointment.

Null data (data length 0) transmit f unction

(IVAL & BCLR)

Appoint read or write operation by RD or WR signal.

This DMA transf er can be used only f or single transf er,

which

Data length (8/16 bit) set f unction

(Octl : Register 8bit mode bit)

Received data length count down f unction

(RCNT : Read count mode bit)

*: There is none f or DMA transf er

transf ers one word (16bit or 8bit) by one time Dreq start.

In DMA transfer, as same as the CPU access, occurs

endpoint buf f er not ready interrupt and endpoint buf f er

empty interrupt according to endpoint buf f er state. But as

to endpoint buf f er ready interrupt, it is not same as the

CPU access as f ollows.

Access to CPU_FIFO data register when interrupt

occurred, to know the endpoint which requested

access, access the "Interrupt Status Register 0/1"

and by checking the interrupt status f lag and know

the endpoint which requested access, and then set

endpoint to be accessed by "CPU_FIFO Selection

Register".

In DMA transfer, endpoint buf f er ready interrupt is not

occurred if the transf er direction is IN.

If the transf er direction is OUT, interrupt is occurred when

received short data packet and ended data transfer of all

data which received in DMA transf er.

If there is no change of endpoint setting, it is not

needed to set again the CPU access endpoint

appointment bit.

Occurring of endpoint buf f er ready interrupt and to ref er

DMA_DTLN, it can be known that short data packet was

received.

Data transfer procedure

DMA_DTLN shows the number of by te of short data

packet,

Data which is set to endpoint FIFO, is sent to USB

bus by LSB f irst. When store the receiv ed data

from USB bus to endpoint FIFO, it is as the same

as abov e.

or in the continuous receiv e mode it shows the number of

byte

of received data bef ore short data packet receiv e.

Time scale

1

16

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D12 D13 D14D15

(Data send procedure to USB bus)

30

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

Double buffer operations

The endpoint FIFO of EP1 to EP5 can be

set to double buffer constitution.

So a double of transfer data of its buffer size, which

is set, can be stored.

(1) Receiv ing

Below are the receive status examples

of the endpoint which is set to double buf f er.

Endpoint buffer status

CPU bus side

USB side

IN

Buf f er1

Buf f er2

"Data1" receiv e start

data1

receiving data

Buf f er2

Buf f er1

data1

When data receive ended, the buf f er

is set to Ready state (read enable)

and occurs INTR interrupt

"Data1" receiv e end

"Data2" receiv e start

"Data1" read start

data receive

available

data receive completed

data read available

Buf f er2

data2

Buf f er1

IN

Continuous receiving is available

before data read.

data1

data read available

receiving data

Buf f er2

data2

Buf f er1

OUT

data1

receiving data

reading data

Buf f er2

data2

Buf f er1

data1

In OUT token receive to this

OUT

endpoint, M66290A occurs

Bef ore "Data1" read end

"Data2" receiv e end

INTN interrupt and do NAK

handshake.

reading data

data receive completed

data receive impossible

It becomes receive enable

after read of data1 ended.

And occurs INTR interrupt

because the buf f er is ready.

Buf f er1

Buf f er2

data2

"Data1" read end

data receive enable

Buf f er1

data read available

Buf f er2

data2

Af ter "Data1" read end

"Data2" receiv e end

M66290A Occurs INTR interrupt

because the buf f er is ready.

data receive available data read available

Buf f er1

data3

receiving data

Buf f er2

IN

"Data3" receiv e start

data2

data read available

data

: Data exists in buf f er

Figure 7. Double buf f er activ ities-1

31

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(2) Transmitting

Below are the transmit status examples

of the endpoint which is set to double buf f er.

Endpoint buffer status

CPU bus side

USB side

Buf f er1

Buf f er2

Can not transmit because the

In token receiv e

"Data1" write start

transmit buf f er is in NotReady .

Request CPU to prepare transmit

data by INTN interrupt

data transmit impossible

Buf f er1

data write available

Buf f er2

data1

IN

data transmit impossible

writing data

End of data write of maximum packet

size or to set(short packet transmit)

IVAL f lag, it becomes transmit data

set status, and transmit becomes enable.

And occurs INTR interrupt because

the buf f er is in Ready (write enable).

Buf f er2

data1

Buf f er1

"Data1" write end

data transmit available

data write available

Buf f er1

Buf f er2

OUT

IN

Data write is available during

data transmitting.

"Data1" transmit start

"Data2" write start

data1

data2

writing data

transmitting data

Buf f er2

data1

Buf f er1

data2

data write completed

data writeimpossible

End of data write of maximum packet

size or to set (short packet transmit)

IVAL flag, it becomes transmit data

set status, and transmit becomes enable.

OUT

Before "Data1" transmit end

"Data2" write end

transmitting data

When data transmit ended,

it occurs INTR interrupt

because the buf f er is in

Ready.

Buf f er1

data2

Buf f er2

"Data1" transmit end

data transmit avalable

data write avalable

Buf f er2

Buf f er1

data2

When data transmit ended, it occurs

INTR interrupt because the buf f er

is in Ready .

Af ter "Data1" transmit end

"Data2" write end

data transmit avalable

data write avalable

Buf f er1

Buf f er2

data3

IN

"Data3" write start

data2

writing data

data transmit avalable

data

: Data exists in buf f er

Figure 8. Double buf f er activ ities-2

32

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(4-1) CPU_FIFO Selection Register (Address : 40h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RCNT

CPU_EP[3:0]

Reset

Bit

15

Name

Function

W/R

Name

H/W S/W USB

If this bit is "1", every time when read CPU_FIFO register,

CPU_DTLN register value is counted down.

RCNT

Read count mode

0

-

14 to 4 Reserved

Write/Read "0"

Appoint the CPU access endpoint.

"0001"=EP1,"0010"=EP2,"0011"=EP3,

"0100"=EP4,"0101"=EP5

EP0 can not be appointed.

CPU_EP

CPU access

endpoint

Don't change the setting in writing (IN) or in reading (OUT).

Change of the setting of the endpoint of direction IN must be

done after confirmed that IVAL="0" and Creq="0", or IVAL="1"

and Creq="1".

3 to 0

[3:0]

W/R 0000

-

Change of the setting of the endpoint of direction OUT must

be done after confirmed that IVAL="1" and Creq="0", or

IVAL="0" and Creq="1".

(4-2) CPU_FIFO Control Register (Address : 42h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

IVAL BCLR Creq

CPU_DTLN[10:0]

Reset

Bit

Name

Function

W/R

Name

H/W S/W USB

15, 14 Reserved

Write/Read "0"

If the selected endpoint is set to IN, this becomes IN buffer

effective state flag.

When set to "1", it becomes transmit data set state.

(SIE is available to read)

When the data (byte) which exceeds to the maximum packet size

(MXPS) is written, this bit is set to "1".

In short packet transmit, set this bit to "1" after wrote the transmit data.

If IVAL="1" and BCLR="1" is written at the same time, the

effective state flag is set.

13

IVAL

IN buffer status

W/R

0

-

(This is effective to transmit 0 length data)

If the selected endpoint is set to OUT, it becomes to

OUT buffer effective state status.

Status "1" shows that there is data which is available to read.

When Creq bit is "0", this bit shows effective value.

This bit is not changed when "1" is written.

Flag is not changed when "0" is written.

33

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

Reset

W/R

Bit

Name

Function

Name

H/W S/W USB

If the selected endpoint is set to IN, when "1" is written into

this bit, the IN buffer effective state flag and the data (byte)

which is written are cleared.

If IVAL="1" and BCLR="1" is written at the same time, data

is cleared but the IN buffer effective state flag is set.

(This is effective to transmit 0 length data)

If the selected endpoint is set to OUT, when "1" is written into

this bit, the OUT buffer effective state flag and the read data (byte)

are cleared.

12

BCLR

Buffer clear

W/R

0

-

If it is set to double buffer, the state of write/read enable buffer

for CPU is cleared.

To set the EPi_ACLR, USB bus buffer is cleared.

This bit is not changed when "0" is written.

If this bit is "0", access to CPU_FIFO data register is available.

And if this bit is "0", the bit of IVAL and CPU_DTLN bit shows the

effective value.

11

Creq

CPU_FIFO ready

R

1

-

When read or write to CPU_FIFO register, 200ns (min) of cycle

time is needed. (Continuous access at 5MHz is available)

If the access end point is changed, 200ns (min) of recovery

time is needed.

When read this register, receive data length (byte) appears.

When RCNT mode is set, every time when read CPU_FIFO

register, it is counted down by -1 (8-bit mode) or by -2 (16-bit mode).

If RCNT mode is not set, this register turns to 000h after all of

received data is read.

CPU_FIFO

receive data

length

CPU_DTL

N[10:0]

10 to 0

R

000h

-

This bit shows effective value when Creq bit is "0".

34

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(4-3) CPU_FIFO Data Register (Address : 44h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

CPU_FIFO[15:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

If the selected endpoint is set to OUT, this becomes to

receive data FIFO register.

If the selected endpoint is set to IN, this becomes to

transmit data FIFO register.

CPU_FIFO

[15:0]

15 to 0

CPU_FIFO data If the selected endpoint is set to 8-bit mode, lower 8 bit [7:0] is valid.

When read or write, 200ns (min) of cycle time is needed.

W/R xxxx

-

(Continuous access at 5MHz is available)

Read operation when direction IN is appointed or write operation

when direction OUT is appointed, write operation is inhibited.

(4-4) DMA_FIFO Selection Register (Address : 48h)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DMAEN

MODE

DMA_EP[3:0]

Reset

H/W S/W USB

Bit

15

Name

Function

W/R

Name

Set the operation mode of DMA transfer.

0 : High speed transfer mode

1 : One word transfer mode

DMA operation

mode

In high speed transfer mode, when endpoint buffer is in read/write enable

in the state that DMA transfer enable, Dreq is asserted.

MODE

0

-

In one word transfer mode, when endpoint buffer is in read/write enable

in the state that DMA transfer enable and Dack="H", Dreq is asserted.

In both mode, Dreq detects Dack="L" and is negated.

14 to 9 Reserved

Write/Read "0"

If this bit is "1", endpoint buffer which is appointed by DMA_EP[3:0]

is enable to write or when read is enable, Dreq is asserted.

If "0" is written in DMA transferring, DMA transfer is forced to end.

DMA transfer

enable

8

DMAEN

W/R

0

-

7 to 4 Reserved

Write/Read "0"

Appoint the endpoint for DMA transfer.

"0001"=EP1,"0010"=EP2,"0011"=EP3,

"0100"=EP4,"0101"=EP5

EP0 can not be appointed.

DMA_EP

DMA transfer

endpoint

Don't change the setting during write (IN) or read (OUT).

Change of the setting of the endpoint of direction IN must

be done after confirmed that IVAL="0" and Dreq="0", or

IVAL="1" and Dreq="1".

3 to 0

[3:0]

W/R 0000

-

Change of the setting of the endpoint of direction OUT must

be done after confirmed that IVAL="0" and Dreq="1".

35

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(4-5) DMA_FIFO Control Register (Address : 4Ah)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

IVAL BCLR Dreq

DMA_DTLN[10:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

15, 14 Reserved

Write/Read "0"

If the selected endpoint is set to IN, this becomes IN buffer

effective state flag.

When set to "1", it becomes transmit data set state.

(SIE is available to read)

When the data (byte) which exceeds to the maximum packet size

(MXPS) is written, this bit is set to "1".

In short packet transmit, set this bit to "1" after wrote

the transmit data.

If IVAL="1" and BCLR="1" is written at the same time, the

IN buffer effective state flag is set to "1".

(This is effective to transmit 0 length data)

13

IVAL

IN buffer status

W/R

0

-

If the selected endpoint is set to OUT, it becomes to

OUT buffer effective state status.

Status "1" shows that there is data which is available to read.

When Creq bit is "0", the value of this bit is effective.

This bit is not changed when "1" is written.

Flag is not changed when "0" is written.

If "1" is written into this bit when the selected endpoint is

set to IN, IN buffer effective state flag and the data (byte)

which is written are cleared.

If the IVAL="1" and BCLR="1" is written at the same time,

the data is cleared but the IN buffer effective state flag

is set.(This is effective to transmit 0 length data)

If "1" is written into this bit when the selected endpoint is

set to OUT, OUT buffer effective state flag and the read data

(byte) are cleared.

12

BCLR

Buffer clear

W/R

0

-

If it is set to double buffer, the state of buffer which can

be read or write for CPU bus is cleared.

To set the EPi_ACLR, USB bus buffer is cleared.

This bit is not changed when "0" is written.

36

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

Reset

W/R

Bit

11

Name

Function

Name

H/W S/W USB

If this bit is "0", then access is available to DMA_FIFO register.

And if this bit is "0", then the bit of IVAL and DMA_DTLN is valid.

This bit is used as DMA request signal (Dreq).

Dreq

DMA_FIFO

ready

R

1

-

DMA_FIFO

receive data

length

DMA_DT

LN[10:0]

When read this register, receive data length (byte) is appears.

This bit is valid when Dreq bit is "0".

10 to 0

000h

(4-6) DMA_FIFO Data Register (Address : 4Ch)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DMA_FIFO[15:0]

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

If the selected endpoint is set to OUT, this becomes to receive data

FIFO register.

If the selected endpoint is set to IN, this becomes to transmit data

DMA_FI

FO[15:0]

15 to 0

DMA_FIFO data FIFO register.

If the selected endpoint is set to 8-bit mode, lower 8 bit [7:0] are valid.

Read operation when the endpoint appointed direction IN, or

write operation when the endpoint appointed direction OUT, is inhibited.

W/R xxxx

-

37

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(4-7) EPi Configuration Register 0 ( i=1 to 5)

(Address : EP1=60h, EP2=64h, EP3=68h, EP4=6Ch, EP5=70h)

D15

D14

D13

DIR

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

EPi_TYP[1:0]

ITMD

EPi_Buf_siz[3:0]

DBLB RWMD

EPi_Buf_Nmb[5:0]

The EPi configuration register 0 must be set in a state of response PID is NAK("00").

Bit

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

To set the transfer type of endpoint.

00 : not Configured

01 : bulk transfer

EPi_TYP

[1:0]

15 to 14

Transfer type

W/R 00

-

10 : interrupt transfer

11 : isochronous transfer

To set the transfer direction of endpoint

0 : OUT (receive data from host)

13

EPi_DIR Transfer direction 1 : IN (transmit data to host)

W/R

0

When changed the state of transfer direction, clear (EPi_ACLR)

the endpoint buffer.

To set the sequence toggle bit mode of interrupt transfer.

0 : Alternation data toggle bit mode

(Only toggled when transfer completed with no problem)

1 : Continuous toggle bit mode

Interrupt toggle

mode

12 EPi_ITMD

-

(Whatever the hand shake exists or the types are, it toggles

every time when data packet is transmitted )

This is effective when endpoint is set to interrupt(IN) transfer.

Set endpoint buffer size at a unit of 64Bytes.

"0000"=64Bytes, "0001"=128Bytes, ...., "1110"=960Bytes,

"1111"=1024Bytes

EPi_Buf_

siz[3:0]

11 to 8

Buffer size

W/R 0000

-

Set the constitution of endpoint buffer.

0 : Single buffer mode

7

EPi_DBLB Double buffer mode 1 : Double buffer mode

In double buffer mode, double of the buffer size is taken as the endpoint

W/R

0

buffer.

If "1" is written into this bit, continuous transfer mode of endpoint is set.

When the direction of endpoint is set to OUT, then it is set to continuous

receive mode. And when the direction of endpoint is set to IN, then it is

set to continuous transmit mode.

Continuous

transfer mode

(only for Bulk

transfer)

Continuous receive mode can receive data packet up to the buffer size

which is set, or can receive continuously before receives short packet.

Continuous transmit mode can transmit data packet up to the buffer size

which is set, and transmission of short packet can be done by set the

IVAL flag.

EPi_

6

W/R

0

-

RWMD

In data packet (max packet size) receive which is less than buffer

size, interrupt to CPU does not occur.

Continuous transfer mode is effective only in bulk transfer.

Appoint the first number of the buffer of a unit of 64Bytes.

Buffer exists from #00h to #2Fh.

EPi_Buf_

Nmb[5:0]

5 to 0

Buffer start number Buffer size(double of the buffer size in double buffer mode), which is

appointed from the first, is secured for endpoint buffer.

W/R 00h

-

Set that plural of endpoint do not occupy the same buffer area.

38

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(4-8) EPi Configuration Register 1 ( i=1 to 5 )

(Address : EP1=62h, EP2=66h, EP3=6Ah, EP4=6Eh, EP5=72h)

D15

D14

D13

D12

D11

D10

Octl

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DMAMD NULMD

EPi_PID[1:0]

ACLR

EPi_MXPS[9:0]

The EPi configuration register 1 must be set in a state of response PID is NAK("00").

Bit

Reset

H/W S/W USB

Bit

Name

Function

W/R

Name

Set response PID.

00 : NAK Whatever the buffer state is, do NAK handshake.

01 : BUF Response PID is selected according to the state of buffer

and sequence toggle bit. (In bulk/interrupt transfer, one of

ACK, NAK, DATA0, and DATA1)

EPi_

PID

15, 14

Response PID

W/R 00

-

[1:0]

1x : STALL Do STALL handshake.

If the transfer direction of selected endpoint is OUT, when received

data which exceeded maximum packet size (MXPS), it becomes

"1x" (=STALL) automatically.

Set the access mode to endpoint buffer.

EPi_

13

12

DMA transfer mode 0 : CPU access mode

1 : DMA transfer mode

W/R

0

-

DMAMD

To set this bit as "1", Null data addition transmit mode is set .

In the endpoint which is set to continuous transmit mode, when

write a multiple data of maximum packet size into buffer and transmit,

Null data is transmitted automatically after transmitted the last packet.

This setting is effective when continuous transmit mode is set.

Null data

addition

EPi_

NULMD

transmit mode

When the selected endpoint is set to OUT and if this bit is set to "1",

OUT buffer effective flag and read data (number of byte) is cleared.

In this state(OUT buffer does not become effective state), SIE side

writes data from host into OUT buffer but CPU side does not read.

When set this bit to "1", whatever the transfer direction is, endpoint

buffer (all buffer of single/double buffer) are cleared.

EPi_

OUT buffer

automatic

11

W/R

0

-

ACLR

clear mode

When clear the endpoint buffer, set this bit to "1" and then set again to "0".

When this bit is set to "1", FIFO data register becomes 8-bit mode and

when accessed "FIFO Data Register" of endpoint, lower 8bit[7:0]

becomes effective.

FIFO access

8 bit mode

10

EPi_Octl

W/R

0

-

When transmit odd number of byte, it is needed to write in 8-bit mode.

When read in 8-bit mode, set to 8-bit mode before data receive.

EPi_

MXPS

[9:0]

Set the maximum data size (Byte) to transmit/receive in one packet

transfer.

9 to 0

Max Packet size

W/R 040h

Set the value of wMaxPacketSize in request.

39

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

ABSOLUTE MAXIMUM RATINGS

Symbol

VCC

VI

Parameter

Supply voltage

Input voltage

Ratings

-0.3 to +4.2

-0.3 to VCC+0.3

±20

Unit

V

VO

Output voltage

Output current

Power dissipation

Storage temperature

V

IO

mA

mW

C

Pd

400

Tstg

-55 to +150

RECOMMENDED OPERATING CONDITIONS

Limits

Typ.

3.3

Symbol

Parameter

Unit

Min.

3.0

Max.

3.6

VCC

GND

VI

Supply voltage

V

0

Input voltage

0

VCC

5.25

VCC

+70

500

V

VI(Vbus)

VO

Input voltage ( Only for Vbus Input )

Output voltage

V

Topr

Operating temperature

Normal input

+25

C

ns

tr, tf

Input rise, fall time

Schmidt trigger input

5

ms

40

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

ELECTRICAL CHARACTERISTICS

Limits

Symbol

Parameter

Condition

Unit

Min.

2.52

0

Typ.

Max.

3.6

VIH

VIL

"H" input voltage

"L" input voltage

VCC = 3.6V

VCC = 3.0V

V

Xin

0.9

VT+

VT-

Threshold voltage in positive direction

Threshold voltage in negative direction

"H" output voltage

1.4

0.5

2.6

2.4

V

Note 1

Xout

VCC = 3.3V

1.65

V

VOH

VOL

VOH

VOL

VOH

VOL

IIH

IOH = -50uA

V

VCC = 3.0V

VCC = 3.6V

"L" output voltage

IOL = 50uA

IOH = -2mA

IOL = 2mA

IOH = -4mA

IOL = 4mA

VI = VCC

0.4

V

"H" output voltage

2.6

V

Note 2

Note 3

"L" output voltage

V

"H" output voltage

V

"L" output voltage

0.4

10

V

"H" input current

uA

kW

IIL

"L" input current

VI = GND

VO = VCC

VO = GND

-10

10

IOZH

IOZL

Rdv

Rdt

Ru

"H" output current in off status

"L" output current in off status

Pull down resistance

Pull up resistance

D15-0

,TDO

-10

Note 4

Note 5

Note 6

100

50

Average supply current in operation

mode

f(Xin)=48MHz,VCC = 3.6V

USB transmit state

ICC(A)

40

2

55

4

mA

Oscillator disable,PLL disable,

USB transceiver enable,

TrON=H/L output

VI=Vcc or GND fixed,Vcc = 3.6V

Oscillator disable,PLL disable,

USB transceiver disable,

TrON=H/L output

30

10

200

100

uA

ICC(S)

Supply current in static mode

VI=Vcc or GND fixed,Vcc = 3.6V

Suspend state

Oscillator disable,PLL disable,

USB transceiver disable,

TrON=H/L output

VI=Vcc or GND fixed,Vcc = 3.6V

H/W reset state

Notes 1: All input and bidirection pins except for Xin (except for USB buffer)

2: INT,Dreq,TDO output pins

3: D15-0 input /output pins

4: Vbus input pins

5: TEST1,TEST2,TCK input pins

6: TRST,TMS,TDI input pins

41

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

ELECTRICAL CHARACTERISTICS (USB)

(1) DC CHARACTERISTICS

Limits

Symbol

Parameter

Test condition

| (D+)-(D-) |

Unit

Min.

0.2

Typ.

Max.

2.5

VDI

Differential Input Sensitivity

V

VCM

Differential Common Mode Range

0.8

VSE

VOL

VOH

Single Ended Receiver Threshold

"L" Output voltage

2.0

0.3

3.6

V

RL of 1.5KWto 3.6V

VCC = 3.0V

VCC = 3.6V

VCC = 3.3V

"H" Output voltage

RL of 15KWto GND

VO =0V

2.8

-10

4

IOZL

IOZH

"L" output current in off status

"H" output current in off status

Output resistance

10

15

mA

W

VO =3.6V

Ro(Pch)

Ro(Nch)

VO =0V

7

Output resistance

VO =3.3V

4

W

(2) AC CHARACTERISTICS

Limits

Typ.

Symbol

Parameter

Test condition

Unit

Min.

4

Max.

20

tr

tf

Rise transition time

Fall transition time

10% to 90% of the data signal

CL=50pF

ns

%

V

10% to 90% of the data signal

4

20

TRFM

VCRS

Rise/fall time matching

Output signal crossover voltage

tr/tf

90

1.3

110

2.0

CL=50pF

42

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

SWITCHING CHARACTERISTICS

Limits

Symbol

Parameter

Test condition

Unit

ns

Min.

Typ.

Max.

30

ta(A)

Address access time

ta(CTRL)

tv(CTRL)

ten(CTRL)

Control access time

Data valid time after control

30

ns

0

Data output enable time after control

20

tdis(CTRL)

td(Dack-

Data output disable time after control

Dreq disable propagation time

INT disable propagation time

INT "H" pulse width

20

60

ns

td(WR-INT)

twh(INT)

CL=50pF

320

60

twh(Dreq)

Dreq "H" pulse width

td(CTRL-

Dreq)

Dreq output enable time after control

Dreq output enable time after Dack

TDO output enable time after TCK

TDO output disable time after TCK

60

20

ns

td(Dackh-

Dreq)

td(TCK-

TDOV)

30

td(TCK-

TDOX)

TIMING REQUIREMENTS

Limits

Typ.

Symbol

tsu(A)

Parameter

Test condition

Unit

Min.

30

Max.

Address setup time

Address hold time

ns

th(A)

0

tw(CTRL)

trec(CTRL)

tsu(D)

Control pulse width

Control recovery time

Data setup time

30

20

0

ns

th(D)

Data hold time

tw(cycle)

FIFO access cycle time

200

tw(RST)

tst(RST)

RESET pulse width

Control start time after RESET

TCK cycle time

100

40

ns

tc(TCK)

tw(TCKH)

tw(TCKL)

tsu(TDI-TCK)

th(TDI-TCK)

tw(TRST)

TCK "H" pulse width

TCK "L" pulse width

TDI,TMS setup time

TRST "L" pulse width

40

20

100

td(CTRL-

Dack)

83

43

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

Measurement circuit

1. Terminals except f or USB buf f er block

Vcc

Input

RL=1kohm

SW1

Item

SW1

close

open

close

open

SW2

open

close

open

close

tdis(CTRL(LZ))

tdis(CTRL(HZ))

ta(CTRL(ZL))

ta(CTRL(ZH))

D15-0, TDO

CL

SW2

P.G

DUT

RL=1kohm

(1) Input pulse level

: 0 to 3.3V

50ohm

Other output

Input pulse rise/f all time : tr=tf=3ns

Input timing v oltage

Output timing v oltage

: 1.65V

: Vcc/2

(tdis(LZ) is measured at 10% of output,

tdis(HZ) is measured at 90% of output)

(2) Capacitance CL includes stray capacitance

and probe capacitance.

2. USB buf f er block

Vcc

RL=1.5kohm

D+

CL

RL=27ohm

RL=15kohm

(1) tr, tf is measured f rom 10% to 90% of output.

(2) Capacitance CL includes stray capacitance

and probe capacitance.

DUT

D-

RL=15kohm

GND

44

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

TIMING DIAGRAM

(1) Write timing

tsu(A)

th(A)

Address is established

A6 to 1

tw(cycle)

trec(CTRL)

tw(CTRL)

CS ,WR

(note2)

tsu(D)

th(D)

Data input is established

D15 to 0

(2) Read timing

ta(A)

th(A)

Address is established

A6 to 1

(note1)

tw(cycle)

ta(CTRL)

trec(CTRL)

tw(CTRL)

CS ,RD

(note3)

tv(CTRL)

tdis(CTRL)

ten(CTRL)

Data output is established

D15 to 0

note 1 : tw(cycle) is needed when access FIFO.

note 2 : Write is done in the overlap period when CS and WR is active "L".

Spec from the positive edge is valid from the fastest inactive signal.

Spec of pulse width is valid of the overlap period of active "L".

note 3 : Read is done in the overlap period of CS and RD is active "L"

Spec from the negative edge is valid from the latest signal.

Spec from the positive edge is valid form the fastest inactive signal.

Spec of pulse width is valid during active "L" overlap period.

45

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(3) DMA Transfer Timing -1

In case of Full speed transfer mode (DMA operation mode register : MODE=0)

(3-1) Write timing -1

twh(Dreq)

(note 4)

Dreq

Dack

td(CTRL-Dreq)

td(Dack-Dreq)

trec(CTRL)

tw(CTRL)

WR

(note 5)

tsu(D)

th(D)

Data input is established

D15 to 0

(3-2) Read timing -1

twh(Dreq)

(note 4)

Dreq

Dack

td(CTRL-Dreq)

td(Dack-Dreq)

ta(CTRL)

trec(CTRL)

tw(CTRL)

(note 6)

RD

tv(CTRL)

tdis(CTRL)

ten(CTRL)

D15 to 0

Data output is established

note 4 : Inactive condition of Dreq is Dack="L"

And when next DMA transfer exists, spec when Dreq turns to active is valid the latest one of twh(Dreq) or td(CTRL-Dreq).

note 5 : Write is done in the overlap period when Dack and WR is active "L".

Spec from the positive edge is valid from the fastest inactive signal.

Spec of pulse width is valid of the overlap period of active "L".

note 6 : Read is done in the overlap period of Dack and RD is active "L"

Spec from the negative edge is valid from the latest signal.

Spec from the positive edge is valid form the fastest inactive signal.

Spec of pulse width is valid during active "L" overlap period.

46

MITSUBISHI <DIGITAL ASSP>

M66290AGP/FP

USB DEVICE CONTROLLER

(3-3) Write timing -2

(note 4)

Dreq

Dack

td(CTRL-Dreq)

td(Dack-Dreq)

RD

WR

tw(CTRL)

(note 5)

tsu(D)

th(D)

D15 to 0

(3-4) Read timing -2