M66287FP [MITSUBISHI]
262144-word x 8-bit x 3-FIELD MEMORY; 262144字×8位x 3场存储器
| 型号： | M66287FP |
| 厂家： | 
Mitsubishi Group |
| 描述： | 262144-word x 8-bit x 3-FIELD MEMORY |
| 文件： | 总21页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
DESCRIPTION
The M66287FP is a high-speed field memory with three FIFO (First In First Out) memories of 262144-word x 8-bit
configuration (2M bits) which uses high-performance silicon gate CMOS process technology. One of three FIFO memories
consists of two FIFO memories of 262144-word x 4-bit (1M bits). Five types of operation can be performed through the
following mode settings:
Mode1 : 3-system delay data output by 3-system individual input of 256K-word x 8-bit FIFO
Mode2 : Simultaneous output of 1 to 3-line delay data by 1-system input of 256K-word x 8-bit FIFO
Mode3 : Simultaneous output of 1 to 2-line delay data by 1-system input of 256K-word x 8-bit FIFO
and,1-system delay data output by 1-system input of 256K-word x 8-bit FIFO
Mode4 : 2-system delay data output by 2-system individual input of 256K-word x 12-bit FIFO
Mode5 : Simultaneous output of 1 to 2-line delay data by 1-system input of 256K-word x 12-bit FIFO
The above-mentioned function is most suitable for image data correction across multiple fields. Because three pieces of
2M-bit FIFO are contained in one chip, a low power consumption of a set can be realized.
FEATURES
z Memory configuration
The total memory capacity is 6M bits (static memory).
The following two types of memory configurations can be selected.
262144-word x 8-bit x 3-line configuration
262144-word x 12-bit x 2-line configuration
16.6 ns (Min.)
z High - speed cycle
z High - speed access
z Output hold
13.0 ns (Max.)
2.0 ns (Min.)
z Supply voltage
Internal = 1.8 V ± 0.18 V
I/O = 3.3 V ± 0.3 V
z Variable length delay bit
z Five modes can be selected
z Write and read function can be operated completely independently and asynchronously
z Output
3 states
z Package
100pin QFP (100P6Q-A)
APPLICATION
W-CDMA base station, Digital PPC, Digital television, VTR and so on.
MODE DESCRIPTIONS DRAWING
2M-bit x 3 configuration
8-bit bus I/F
3M-bit x 2 configuration
12-bit bus I/F
MODE 1
MODE 2
MODE 3
MODE 4
MODE 5
12
12
8
8
8
8
8
8
8
8
12
12
DA<7:0>
WCKA
WRESA
WEA
QA<7:0>
RCKA
DA<7:0>
WCKA
QA<7:0>
RCKA
DA<11:0>
WCKA
DA<7:0>
WCKA
WRESA
WEA
QA<7:0>
RCKA
QA<11:0>
DA<11:0>
QA<11:0>
256K
x
8-bit
FIFO
256K
x
8-bit
FIFO
256K
x
256K
x
12-bit
FIFO
256K
x
12-bit
FIFO
RCKA
RCKA
WCKA
WRESA
RRESA
8-bit
FIFO
RRESA
REA
RRESA
WRESA
WRESA
WEA
RRESA
REA
RRESA
REA
REA
WEA
REA
WEA
8
DB<7:0>
WCKB
WRESB
WEB
QB<7:0>
RCKB
256K
x
256K
x
8-bit
FIFO
256K
x
8-bit
FIFO
8
8
8
8
8
QB<7:0>
QB<7:0>
8-bit
FIFO
RRESB
REB
12
12
DB<11:0>
WCKB
QB<11:0>
RCKB
12 256K
x
12-bit
FIFO
12
256K
x
12-bit
FIFO
QB<11:0>
8
8
8
WRESB
WEB
RRESB
REB
QC<7:0>
DC<7:0>
WCKC
WRESC
WEC
QC<7:0>
RCKC
DC<7:0>
WCKC
WRESC
WEC
256K
x
8-bit
FIFO
256K
x
8-bit
FIFO
256K
x
8-bit
FIFO
8
RCKC
RRESC
REC
QC<7:0>
RRESC
REC
The three pieces of 256K- The three pieces of 256K- The two pieces of 256K-
The two pieces of 256K-
The two pieces of 256K-
word x 8-bit FIFO can be
operated completely
independently.
word x 8-bit FIFO are
cascade-connected.
Write and read operation
of FIFO after the 2nd line
is controlled by the read
system pin of the 1st line.
word x 8-bit FIFO are
word x 12-bit FIFO can be word x 12-bit FIFO are
cascade-connected and, a operated completely
piece of 256K-word x 8-bit independently.
FIFO can be operated
completely independently.
Write and read operation
cascade-connected.
Write and read operation
of FIFO at the 2nd line is
controlled by the read
system pin of the 1st line.
of FIFO at the 2nd line is
controlled by the read
system pin of the 1st line.
Note: Please refer to “Pin Assignment Table” in “MODE 4 and MODE 5 OPERATION DESCRIPTIONS” for
assignment of external pins, Dx<11:0> and Qx<11:0> when used in 12-bit bus interface.
© 2002 MITSUBISHI ELECTRIC CORPORATION
1
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
PIN CONFIGURATION (TOP VIEW)
1
TEST3
WCKA
WRESA
WEA
VCCIO
GND
WCKB
WRESB
WEB
VCCIO
GND
WCKC
WRESC
WEC
VCC18
GND
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
GND
RCKA
75
2
74
3
73
RRESA
REA
VCCIO
GND
RCKB
RRESB
REB
MODE1
MODE2
MODE3
RCKC
RRESC
4
72
5
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
6
7
8
9
10
11
12
13
14
15
REC
VCCIO
GND
QB7
QB6
QB5
16
17
18
19
20
21
QB4
QB3
QB2
QB1
QB0
22
54
53
52
51
23
24
25
VCCIO
Outline 100P6Q-A
© 2002 MITSUBISHI ELECTRIC CORPORATION
2
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
BLOCK DIAGRAM
Data input
DC<7:0>
DA<7:0>
DB<7:0>
INPUT BUFFER
Mode setting
input
MODE CONTROL CIRCUIT
MODE<3:1>
Read control inputs
for A-system
Write control inputs
for A-system
RCKA
RRESA
REA
WCKA
WRESA
WEA
MEMORY ARRAY
Read control inputs
for B-system
Write control inputs
for B-system
256K-WORD x 8-BIT
256K-WORD x 4-BIT
256K-WORD x 4-BIT
256K-WORD x 8-BIT
RCKB
RRESB
REB
WCKB
WRESB
WEB
Read control inputs
for C-system
Write control inputs
for C-system
RCKC
RRESC
REC
WCKC
WRESC
WEC
Test setting
input
MODE CONTROL CIRCUIT
TEST<3:1>
VCC 18
GND
OUTPUT BUFFER
VCC IO
GND
Data output
QC<7:0>
QB<7:0>
QA<7:0>
© 2002 MITSUBISHI ELECTRIC CORPORATION
3
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
PIN FUNCTION DESCRIPTIONS
Pin name
Name
Input /
output
Input
Function
WCKA
WCKB
WCKC
WEA
WEB
WEC
Write clock input
They are write clock inputs.
WCKA is a write clock for the A-system, WCKB for the B-system and
WCKC for the C-system.
Write enable input
Write reset input
Input
Input
They are write enable control inputs.
When they are "L", a write enable status is provided.
WEA is a write enable for the A-system, WEB for the B-system and
WEC for the C-system.
WRESA
WRESB
WRESC
They are reset inputs to initialize a write address counter of internal
FIFO.
When they are "L", a write reset status is provided.
WRESA is a write reset for the A-system, WRESB for the B-system
and WRESC for the C-system.
RCKA
RCKB
RCKC
REA
Read clock input
Read enable input
Input
Input
They are read clock inputs.
RCKA is a read clock for the A-system, RCKB for the B-system and
RCKC for the C-system.
They are read enable control inputs.
REB
REC
When they are "L", a read enable status is provided.
REA is a read enable for the A-system, REB for the B-system and
REC for the C-system.
RRESA
RRESB
RRESC
Read reset input
Input
They are reset inputs to initialize a read address counter of internal
FIFO.
When they are "L", a read reset status is provided.
RRESA is a read reset for the A-system, RRESB for the B-system
and RRESC for the C-system.
DA<7:0>
DB<7:0>
DC<7:0>
QA<7:0>
QB<7:0>
QC<7:0>
Data input
Input
They are 8-bit data input bus.
DA<7:0> is a data input bus for the A-system, DB<7:0> for the B-
system and DC<7:0> for the C-system.
Data output
Output
They are 8-bit data output bus.
QA<7:0> is a data output bus for the A-system, QB<7:0> for the B-
system and QC<7:0> for the C-system.
MODE<3:1> Mode setting input
Input
Input
They are pins for setting operation mode.
Setting is refer to MODE SET-table.
TEST<3:1>
Test setting input
They are pins for test.
Setting of TEST1 depends on the rising time of the 1.8 V system
power supply. For further details, refer to page 11.
TEST2 and TEST3 should be fixed at "L".
This is a 3.3 V power supply pin for I/O.
VCCIO
VCC18
GND
Power supply pin for
I/O
-
-
-
Power supply pin for
internal circuit
Ground pin
This is a 1.8 V power supply pin for internal circuit.
This is a ground pin.
© 2002 MITSUBISHI ELECTRIC CORPORATION
4
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
MODE SET
MODE<3:1> should be set to “L” or “H” as shown below according to the five modes to be used.
MODE 3
MODE 2
MODE 1
Operation mode
MODE 1
L
L
L
L
H
L
L
L
H
L
MODE 2
MODE 3
MODE 4
MODE 5
MODE 1
H
H
L
H
L
other than those above
MODE 1 OPERATION DESCRIPTIONS
<Mode 1>
8
8
8
8
8
8
DA<7:0>
WCKA
WRESA
WEA
QA<7:0>
RCKA
RRESA
REA
In mode 1, three FIFO memories with 8-bit data bus can be controlled completely
individually. Taking FIFO (A) as an example, the operation of FIFO memory is
described below. The operation of FIFO (B) and FIFO (C) are the same as that of
FIFO (A).
256K
x
8-bit
FIFO(A)
DB<7:0>
WCKB
WRESB
WEB
QB<7:0>
RCKB
RRESB
REB
256K
x
8-bit
FIFO(B)
When write enable input WEA is "L", the contents of data input DA<7:0> are
written into FIFO (A) in synchronization with the rising of write clock input WCKA.
At this time, the write address counter of FIFO (A) is incremented.
When WEA is "H", writing into FIFO (A) is disabled and the write address counter
of FIFO (A) is stopped.
DC<7:0>
WCKC
WRESC
WEC
QC<7:0>
RCKC
RRESC
REC
256K
x
8-bit
FIFO(C)
When write reset input WRESA is "L", the write address counter of FIFO (A) is
initialized.
When read enable input REA is "L", the contents of FIFO (A) are outputted to data output QA<7:0> in synchronization with
the rising of read clock input RCKA. At this time, the read address counter of FIFO (A) is incremented.
When REA is "H", reading from FIFO (A) is disabled and the read address counter of FIFO (A) is stopped. Also QA<7:0>
become high impedance state.
When read reset input RRESA is "L", the read address counter of FIFO (A) is initialized.
Note : The three pieces of 256K-word x 8-bit FIFO can be operated completely independently.
© 2002 MITSUBISHI ELECTRIC CORPORATION
5
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
MODE 2 OPERATION DESCRIPTIONS
<Mode 2>
8
8
8
8
8
8
In mode 2, three FIFO memories with 8-bit data bus are cascade-connected
and it is possible to generate delay data for 3-lines without external wiring.
QA<7:0>
RCKA
RRESA
REA
DA<7:0>
WCKA
WRESA
WEA
256K
x
8-bit
FIFO(A)
When write enable input WEA is "L", the contents of data input DA<7:0> are
written into FIFO (A) in synchronization with the rising of write clock input
WCKA. At this time, the write address counter of FIFO (A) is incremented.
When WEA is "H", writing into FIFO (A) is disabled and the write address
counter of FIFO (A) is stopped.
QB<7:0>
256K
x
8-bit
FIFO(B)
When write reset input WRESA is "L", the write address counter of FIFO (A) is
initialized.
QC<7:0>
256K
x
8-bit
FIFO(C)
When read enable input REA is "L", the contents of FIFO (A), FIFO (B) and
FIFO (C) are outputted to each QA<7:0>, QB<7:0>, QC<7:0> in
synchronization with the rising of read clock input RCKA. At this time, the read
address counters of all FIFOs are incremented.
Also the data of the upper FIFO is written into the lower FIFO in synchronization with the rising of RCKA. At this time, the
write address counters of FIFO (B) and FIFO (C) are incremented simultaneously.
When REA is "H", reading from FIFO (A), FIFO (B) and FIFO (C) is disabled and the read address counter of each FIFO is
stopped. Also all data outputs become high impedance state. And writing into FIFO (B) and FIFO (C) is disabled and the
write address counters of FIFO (B) and FIFO (C) are stopped.
When read reset input RRESA is "L", the read address counter of FIFO (A) and the write address counters/read address
counters of FIFO (B) and FIFO (C) are initialized.
And, in mode 2, all pins for the A-system, QB<7:0> and QC<7:0> are only used. Therefore the write/read control pins for
the B-system and C-sytsem, DB<7:0> and DC<7:0> should be fixed at "L" or "H".
Note : The three pieces of 256K-word x 8-bit FIFO are cascade-connected, and a line delay data can be made
easily. Write and read operation of FIFO after the 2nd line is controlled by the read system pin of the 1st
line.
© 2002 MITSUBISHI ELECTRIC CORPORATION
6
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
MODE 3 OPERATION DESCRIPTIONS
<Mode 3>
8
8
In mode 3, two FIFO memories with 8-bit data bus are cascade-connected
and the other FIFO memory with an 8-bit data bus is configured completely
independently. This makes it possible to generate delay data for 2-lines
without external wiring and to control the other independent one FIFO
memory.
QA<7:0>
DA<7:0>
WCKA
WRESA
WEA
256K
x
8-bit
FIFO(A)
RCKA
RRESA
REA
8
8
QB<7:0>
256K
x
8-bit
FIFO(B)
When write enable input WEA is "L", the contents of data input DA<7:0> are
written into FIFO (A) in synchronization with the rising of write clock input
WCKA. At this time, the write address counter of FIFO (A) is incremented.
When WEA is "H", writing into FIFO (A) is disabled and the write address
counter of FIFO (A) is stopped.
8
8
QC<7:0>
RCKC
RRESC
REC
DC<7:0>
WCKC
WRESC
WEC
256K
x
8-bit
FIFO(C)
When write reset input WRESA is "L", the write address counter of FIFO (A) is
initialized.
When read enable input REA is "L", the contents of FIFO (A) and FIFO (B) are
outputted to each QA<7:0> and QB<7:0> in synchronization with the rising of
read clock input RCKA. At this time, the read address counters of FIFO (A)
and FIFO (B) are incremented.
Also the data of FIFO (A) is written into FIFO (B) in synchronization with the rising of RCKA. At this time, the write address
counter of FIFO (B) is incremented simultaneously.
When REA is "H", reading from FIFO (A) and FIFO (B) is disabled and the read address counter of each FIFO is stopped.
Also QA<7:0> and QB<7:0> become high impedance state. And writing into FIFO (B) is disabled and the write address
counter of FIFO (B) is stopped.
When read reset input RRESA is "L", the read address counter of FIFO (A) and the write address counter/read address
counter of FIFO (B) are initialized.
The operation of FIFO (C) is the same as that of mode 1.
And, in mode 3, all pins for the A-system and C-system, and QB<7:0> are only used. Therefore the write/read control pins
for the B-system and DB<7:0> should be fixed at "L" or "H".
Note : The two pieces of 256K-word x 8-bit FIFO are cascade-connected and, a piece of 256K-word x 8-bit FIFO
can be operated completely independently.
Write and read operation of FIFO at the 2nd line is controlled by the read system pin of the 1st line.
© 2002 MITSUBISHI ELECTRIC CORPORATION
7
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
MODE 4 OPERATION DESCRIPTIONS
<Mode 4>
12
12
DA<7:0>
DB<3:0>
QA<7:0>
QB<3:0>
In mode 4, two FIFO memories with 12-bit data bus can be controlled completely
individually. Taking FIFO (A) as an example, the operation of FIFO memory is
described below. The operation of FIFO (B) is the same as that of FIFO (A).
256K
x
12-bit
FIFO(A)
WCKA
WRESA
WEA
RCKA
RRESA
REA
When write enable input WEA is "L", the contents of data input DA<7:0> and
DB<3:0>are written into FIFO (A) in synchronization with the rising of write clock
input WCKA. At this time, the write address counter of FIFO (A) is incremented.
When WEA is "H", writing into FIFO (A) is disabled and the write address counter
of FIFO (A) is stopped.
12
12
QC<7:0>
QB<7:4>
DC<7:0>
DB<7:4>
256K
x
12-bit
FIFO(B)
WCKB
WRESB
WEB
RCKB
RRESB
REB
When write reset input WRESA is "L", the write address counter of FIFO (A) is
initialized.
When read enable input REA is "L", the contents of FIFO (A) are outputted to data output QA<7:0> and QB<3:0> in
synchronization with the rising of read clock input RCKA. At this time, the read address counter of FIFO (A) is incremented.
When REA is "H", reading from FIFO (A) is disabled and the read address counter of FIFO (A) is stopped. Also QA<7:0>
and QB<3:0> become high impedance state.
When read reset input RRESA is "L", the read address counter of FIFO (A) is initialized.
Also, set the 12-bit I/O buses of FIFO (A) and FIFO (B) as shown in the table below.
In mode 4, all pins for the A-system and B-system, DC<7:0> and QC<7:0> are only used. Therefore the write/read control
pins for the C-system should be fixed at "L" or "H".
External pin Data
input External pin Data output External pin Data
input External pin Data output
name
bus of FIFO name
(A)
bus of FIFO name
(A)
bus of FIFO name
(B)
bus of FIFO
(B)
DA<7>
DA<6>
DA<5>
DA<4>
DA<3>
DA<2>
DA<1>
DA<0>
DB<3>
DB<2>
DB<1>
DB<0>
11-bit
10-bit
9-bit
8-bit
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
QA<7>
QA<6>
QA<5>
QA<4>
QA<3>
QA<2>
QA<1>
QA<0>
QB<3>
QB<2>
QB<1>
QB<0>
11-bit
10-bit
9-bit
8-bit
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
DC<7>
DC<6>
DC<5>
DC<4>
DC<3>
DC<2>
DC<1>
DC<0>
DB<7>
DB<6>
DB<5>
DB<4>
11-bit
10-bit
9-bit
8-bit
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
QC<7>
QC<6>
QC<5>
QC<4>
QC<3>
QC<2>
QC<1>
QC<0>
QB<7>
QB<6>
QB<5>
QB<4>
11-bit
10-bit
9-bit
8-bit
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
Note : The two pieces of 256K-word x 12-bit FIFO can be operated completely independently.
© 2002 MITSUBISHI ELECTRIC CORPORATION
8
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
MODE 5 OPERATION DESCRIPTIONS
<Mode 5>
12
12
DA<7:0>
DB<3:0>
QA<7:0>
QB<3:0>
In mode 5, two FIFO memories with 12-bit data bus are cascade-connected
and it is possible to generate delay data for 2-lines without external wiring.
256K
x
12-bit
FIFO(A)
WCKA
WRESA
WEA
RCKA
RRESA
REA
When write enable input WEA is "L", the contents of data input DA<7:0> and
DB<3:0> are written into FIFO (A) in synchronization with the rising of write
clock input WCKA. At this time, the write address counter of FIFO (A) is
incremented.
12
12
QC<7:0>
QB<7:4>
256K
x
12-bit
FIFO(B)
When WEA is "H", writing into FIFO (A) is disabled and the write address
counter of FIFO (A) is stopped.
When write reset input WRESA is "L", the write address counter of FIFO (A) is
initialized.
When read enable input REA is "L", the contents of FIFO (A) and FIFO (B) are outputted to each QA<7:0>, QB<3:0> and
QC<7:0> and QB<7:4> in synchronization with the rising of read clock input RCKA. At this time, the read address counters
of FIFO (A) and FIFO (B) are incremented.
Also the data of FIFO (A) is written into FIFO (B) in synchronization with the rising of RCKA. At this time, the write address
counter of FIFO (B) is incremented simultaneously.
When REA is "H", reading from FIFO (A) and FIFO (B) is disabled and the read address counter of each FIFO is stopped.
Also all data outputs become high impedance state. And writing into FIFO (B) is disabled and the write address counter of
FIFO (B) is stopped.
When read reset input RRESA is "L", the read address counter of FIFO (A) and the write address counter/read address
counter of FIFO (B) are initialized.
Also, set the 12-bit I/O buses of FIFO (A) and FIFO (B) as shown in the table below.
In mode 5, all pins for the A-system, DB<3:0>, QB<7:0> and QC<7:0> are only used. Therefore the write/read control pins
for the B-system and the C-system, DB<7:4> and DC<7:0> should be fixed at "L" or "H".
External pin Data
input External pin Data output External pin Data output
name
bus of FIFO name
(A)
bus of FIFO name
(A)
bus of FIFO
(B)
DA<7>
DA<6>
DA<5>
DA<4>
DA<3>
DA<2>
DA<1>
DA<0>
DB<3>
DB<2>
DB<1>
DB<0>
11-bit
10-bit
9-bit
8-bit
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
QA<7>
QA<6>
QA<5>
QA<4>
QA<3>
QA<2>
QA<1>
QA<0>
QB<3>
QB<2>
QB<1>
QB<0>
11-bit
10-bit
9-bit
8-bit
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
QC<7>
QC<6>
QC<5>
QC<4>
QC<3>
QC<2>
QC<1>
QC<0>
QB<7>
QB<6>
QB<5>
QB<4>
11-bit
10-bit
9-bit
8-bit
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
Note : The two pieces of 256K-word x 12-bit FIFO are cascade-connected, and a line delay data can be made easily.
Write and read operation of FIFO at the 2nd line is controlled by the read system pin of the 1st line.
© 2002 MITSUBISHI ELECTRIC CORPORATION
9
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (Ta = 0 ~ 70°C, unless otherwise noted)
Symbol
Parameter
Supply voltage
Conditions
Ratings
-0.3~+2.5
Unit
VCC18
A value based on GND
V
(1.8 V power supply )
Supply voltage
VCCIO
-0.3~+3.8
V
(3.3 V power supply )
Input voltage
VI
-0.3~VCCIO+0.3
-0.3~VCCIO+0.3
800
V
VO
Pd
Output voltage
V
Maximum power dissipation
Storage temperature
Ta = 70 °C
mW
°C
Tstg
-55~150
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Test conditions
Limits
Unit
V
Min.
1.62
Typ.
1.8
Max.
VCC18
Supply voltage for internal circuit
(1.8 V power supply )
A value based on GND
1.98
VCCIO
Topr
Supply voltage for I/O
(3.3 V power supply )
3.0
0
3.3
3.6
70
V
Operating ambient temperature
°C
DC CHARACTERISTICS
(Ta = 0 ~ 70°C, Vcc18 = 1.8 ± 0.18 V, VccIO = 3.3 ± 0.3 V, GND = 0 V, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Typ.
Unit
V
Min.
0.8 x
Max.
VIH
"H" input voltage
A value based on GND
VccIO
VIL
"L" input voltage
0.2
x
V
VccIO
VOH
"H" output voltage
IOH = -4mA
VccIO
- 0.4
V
VOL
IIH
"L" output voltage
IOL = 4mA
0.4
10
V
"H" input current
VI = VCCIO
µA
µA
µA
µA
mA
IIL
"L" input current
VI = GND
-10
10
IOZH
IOZL
ICC18
Off state "H" output current
Off state "L" output current
Operating mean current dissipation
(1.8 V)
VO = VCCIO
VO = GND
-10
135
VCC18 = 1.8 V ± 0.18 V
VCCIO = 3.3 V ± 0.3 V
VI = repeat "H" and "L"
Output open
ICCIO
Operating mean current dissipation
(3.3 V)
145
mA
tWCK = tRCK = 16.6 ns
f = 1 MHz
CI
Input capacitance
10
15
pF
pF
CO
Off state output capacitance
f = 1 MHz
© 2002 MITSUBISHI ELECTRIC CORPORATION
10
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
POWER - ON
After power-on, this IC initializes some circuits of internal FIFO (1.8 V), using the built-in power-on reset circuit.
This power-on reset is performed by using the VCC18 = 1.8 V system power supply.
Either of the following conditions (1) or (2) should be met according to the power-on time of the VCC18.
(1) When the power-on time of the VCC1.8 is 1 msec or less:
Some circuits of internal FIFO are initialized by the built-in power-on reset circuit. No restriction is imposed on the
power-on sequence between VCC18 and VCCIO = 3.3 V system power supply. When powering on again after power-on,
provide an interval of 100 ms or more for the VCC18. At this time, the TEST1 (pin 99) pin should be fixed at "L".
1ms(max)
100ms(min)
VCC18
VCC18
VCC18 x 10%
VCC18 x 10%
GND
(2) When the power-on time of the VCC18 is more than 1 msec:
Some circuits of internal FIFO should be initialized by the TEST1 (pin 99) pin.
Input a initialize reset pulse of 200 ns or more after the power supplies (VCCIO, VCC18) reach to the VCC level.
There is no problem even if reaching to the VCC level on which power supply.
3.0V~3.6V
VCCIO
3.0V~3.6V
VCCIO
VCC18
TEST1
GND
GND
GND
1ms or more
1.62V~1.98V
VCC18
VCCIO
200ns(min)
200ns(min)
Note : Some circuits of internal FIFO can be initialized by the TEST1 pin even if the power-on time of the VCC18 is 1
msec or less.
Note : Important matter;
Provide write reset cycles and read reset cycles of 100 cycles or more, respectively after the VCC reaches
to the specified voltage after power-on.
When inputting a reset pulse using the TEST1 (pin 99) pin, provide write reset cycles and read reset cycles
of 100 cycles or more, respectively after inputting a reset pulse at power-on.
There is no problem in this reset operation if a total of 100 cycles or more is achieved, even if
discontinuous reset input is made.
© 2002 MITSUBISHI ELECTRIC CORPORATION
11
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
TIMING REQUIREMENTS
(Ta = 0 ~ 70°C, VCC18 = 1.8 ± 0.18 V, VCCIO = 3.3 ± 0.3 V, GND = 0 V, unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min. Typ. Max.
t WCK
Write clock (WCK) cycle
16.6
6.5
6.5
16.6
6.5
6.5
3.5
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t WCKH
t WCKL
t RCK
Write clock (WCK) "H" pulse width
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
t RCKH
t RCKL
t DS
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
Input data setup time to WCK
t DH
Input data hold time to WCK
t RESS
t RESH
t NRESS
t NRESH
t WES
t WEH
t NWES
t NWEH
t RES
Reset setup time to WCK or RCK
Reset hold time to WCK or RCK
Reset nonselect setup time to WCK or RCK
Reset nonselect hold time to WCK or RCK
Write enable setup time to WCK
Write enable hold time to WCK
3.5
2
3.5
2
3.5
2
Write enable nonselect setup time to WCK
Write enable nonselect hold time to WCK
Read enable setup time to RCK
Read enable hold time to RCK
3.5
2
3.5
2
t REH
t NRES
t NREH
t r, t f
Read enable nonselect setup time to RCK
Read enable nonselect hold time to RCK
Input pulse rise/fall time
3.5
2
3
SWITCHING CHARACTERISTICS
(Ta = 0 ~ 70°C, VCC18 = 1.8 ± 0.18 V, VCCIO = 3.3 ± 0.3 V, GND = 0 V, unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min. Typ. Max.
t AC
Output access time to RCK
Output hold time to RCK
Output enable time to RCK
Output disable time to RCK
13
ns
ns
ns
ns
t OH
2
t OEN
t ODIS
2
2
13
13
© 2002 MITSUBISHI ELECTRIC CORPORATION
12
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT
Vcc IO
RL=1KΩ
SW1
SW2
Qn
Qn
CL=10pF: tAC,tOH
CL=3pF: tOEN,tODIS
RL=1KΩ
Parameter
tODIS (LZ)
SW1
SW2
Close
Open
Close
Open
Open
tODIS (HZ)
tOEN (ZL)
Close
Open
Close
tOEN (ZH)
Input pulse level
: 0~VCCIO
Input pulse rise/fall time : 1 ns
Decision voltage input : 1/2 VCCIO
Decision voltage output : 1/2 VCCIO (However, tODIS (LZ) is 10% of output amplitude and tODIS (HZ) is 90%
of that for decision).
The load capacitance CL includes the floating capacitance of connection and the input capacitance of probe.
t
ODIS and tOEN MEASUREMENT CONDITION
VIH
VIL
1/2 VccIO
1/2 VccIO
RCK
VIH
VIL
RE
OEN
t
(ZH)
ODIS
t
t
(HZ)
OH
V
90%
Qn
Qn
1/2 VccIO
1/2 VccIO
OEN
t
(ZL)
ODIS
(LZ)
10%
OL
V
© 2002 MITSUBISHI ELECTRIC CORPORATION
13
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
OPERATING TIMING
l
WRITE CYCLE
n+4 cycle
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
Disable cycle
WCK
WE
Dn
tWCK
tWCKH tWCKL tWEH tNWES
tNWEH tWES
tDS tDH
tDS tDH
(n)
(n+1)
(n+2)
(n+3)
(n+4)
WRES = "H"
l
WRITE RESET CYCLE
n-1 cycle
tWCK
n cycle
0 cycle
1 cycle
Reset cycle
WCK
tNRESH tRESS
tRESH tNRESS
WRES
tDS tDH
(n-1)
tDS tDH
Dn
(n)
(0)
(1)
In case of WE = "L"
© 2002 MITSUBISHI ELECTRIC CORPORATION
14
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
z WRITE RESET and WRITE ENABLE COMBINATION CYCLE
n+1 cycle
n+2 cycle
Disable cycle
0 cycle
1 cycle
n cycle
tWCK
WCK
tWCKH tWCKL tWEH tNWES
tNWEH tWES
WE
tNRESH tRESS tRESH tNRESS
WRES
tDS tDH
(n)
tDS tDH
(n+2)
Dn
(n+1)
(0)
(1)
Note : There are no restrictions of WE to WRES.
© 2002 MITSUBISHI ELECTRIC CORPORATION
15
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
l
READ CYCLE
n cycle
n+1 cycle
n+2 cycle
n+3 cycle
n+4 cycle
Disable cycle
RCK
tNREH tRES
tRCK
tRCKH tRCKL tREH tNRES
RE
Qn
tODIS
tOEN
tAC
HIGH-Z
(n)
(n+1)
(n+2)
(n+3)
(n+4)
tOH
tOH
RRES = "H"
l
READ RESET CYCLE
n cycle
n-1 cycle
Reset cycle
0 cycle
1 cycle
RCK
tRCK
tNRESH tRESS
tRESH tNRESS
RRES
Qn
tAC
tAC
tAC
(n-1)
(n)
(0)
(1)
tOH
tOH
tOH
In case of RE = "L"
© 2002 MITSUBISHI ELECTRIC CORPORATION
16
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
z READ RESET and READ ENABLE COMBINATION CYCLE
n cycle
n+1 cycle
n+2 cycle
0 cycle
1 cycle
Disable cycle
RCK
RE
tRCK
tRCKH tRCKL tREH tNRES
tNREH tRES
tNRESH tRESS tRESH tNRESS
RRES
Qn
tOEN
tAC
tAC
tAC
tODIS
HIGH-Z
(n)
tOH
(n+1)
(n+2)
tOH
(0)
tOH
(1)
Note : There are no restrictions of RE to RRES.
© 2002 MITSUBISHI ELECTRIC CORPORATION
17
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
z ATTENTIONS when WCK and RCK STOP
The intervals of 16 cycles or more between a write cycle and a read cycle should be secured, and WCK and RCK should be
inputted for 16 cycles or more based on beginning of write n cycle at any timing, when both WCK and RCK or either of both
is stopped and the newest data is read after it restarts.
Output data becomes undefined when these restrictions are not filled.
<TIMING 1> When WCK and RCK stop synchronously
n cycle
n+1 cycle
n+2 cycle
n+m-1 cycle
n+m cycle n+m+1 cycle
n+m+3 cycle
n+m+2 cycle
WCK
Dn
tDS tDH
(n)
(n+1)
(n+2)
(n+m-1)
(n+m)
(n+m+1)
(n+m+2)
(n+m+3)
m cycle
n-m cycle
n-1 cycle
n-m+1 cycle
n-m+2 cycle
n cycle
n+1 cycle
n+3 cycle
n+2 cycle
RCK
Qn
tAC
tOH
(n-m)
(n-m+1)
(n-m+2)
(n-1)
(n)
(n+1)
(n+2)
(n+3)
m ≥ 16
WRES = "H"
RRES = "H"
WE = "L"
RE = "L"
<TIMING 2> When WCK and RCK stop asynchronously
n+m+3 cycle
n+m+4 cycle
n+m+1 cycle n+m+2 cycle
n+m cycle
n-1 cycle
n cycle
WCK
Dn
tDS tDH
(n-1)
(n)
(n+m)
(n+m+1)
(n+m+2)
(n+m+3)
(n+m+4)
m cycle
Please secure m ≥ 16 interval cycles also in the timing which a write
cycle and a read cycle approach most.
n-m-1cycle
n cycle
n-m-2 cycle
n-m cycle
n-m-3 cycle
n+1 cycle
n+2 cycle
RCK
Qn
tAC
tOH
(n-m-3)
(n-m-2)
(n-m-1)
(n-m)
(n)
(n+1)
(n+2)
m ≥ 16
WRES = "H"
RRES = "H"
WE = "L"
RE = "L"
© 2002 MITSUBISHI ELECTRIC CORPORATION
18
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
VARIABLE LENGTH DELAY BITS
z 1-LINE (262144-BIT) DELAY
In read cycles, an output data is read at the (first) rising edge of RCK start the cycle. In write cycles, an input data is written
at the (second) rising edge of WCK end the cycle. So 1-line delay can be made easily according to the control method of
the following figure.
262142
cycle
262143
cycle
262144
cycle
262146
cycle
(2’)
262145
cycle
2 cycle
Reset cycle
0 cycle
1 cycle
(0’)
(1’)
WCK
RCK
tRESS tRESH
WRES
RRES
tDS tDH
tDS tDH
(262141)
(262142)
(262143)
(0)
(1)
(2)
(0’)
(1’)
(2’)
Dn
Qn
tOH
tAC
262144 cycle
(0)
(1)
(2)
WE, RE = "L"
z N-BIT DELAY 1
(Reset at a cycle corresponding to delay length)
0 cycle
(0’)
1 cycle
(1’)
2 cycle
(2’)
n cycle
Reset cycle
0 cycle
1 cycle
Reset cycle
2 cycle
WCK
RCK
tRESS tRESH
tRESS tRESH
WRES
RRES
tDS tDH
tDS tDH
(n)
(0)
(1)
(2)
(n-1)
(0’)
(1’)
(2’)
Dn
Qn
tOH
tAC
Delay length n
(0)
(1)
(2)
262144 ≥ n ≥ 16
WE, RE = "L"
Note : The intervals of 16 cycles or more between a write cycle and a read cycle should be secured to read data
written in a certain cycle.
© 2002 MITSUBISHI ELECTRIC CORPORATION
19
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
z N-BIT DELAY 2
(Sliding timings of WRES and RRES at a cycle corresponding to delay length)
n+1 cycle
1 cycle
n-1 cycle
Reset cycle 0 cycle
n cycle
n+2 cycle
2 cycle
n+3 cycle
3 cycle
·····Write side
·····Read side
0 cycle
1 cycle
2 cycle
Reset cycle
WCK
RCK
RESS RESH
t
t
WRES
RESS
t
RESH
t
DS DH
DS DH
t
t
(n)
t
t
t
RRES
Dn
(0)
(1)
(2)
(n-2)
(n-1)
(n+1)
(n+2)
(n+3)
AC
t
OH
Delay length n
(0)
(1)
(2)
(3)
Qn
262144 ≥ n ≥ 16
WE, RE = "L"
z N-BIT DELAY 3
(Sliding address by disabling RE at a cycle corresponding to delay length)
n+1 cycle
1 cycle
n-1 cycle
n cycle
0 cycle
n+2 cycle
2 cycle
n+3 cycle
3 cycle
·····Write side
·····Read side
0 cycle
1 cycle
2 cycle
Reset cycle
WCK
RCK
RESS
RESH
t
t
WRES
RRES
tNREH tRES
RE
tDS tDH
tDS tDH
(0)
(1)
(2)
(n-2)
(n-1)
(n)
(n+1)
(n+2)
(n+3)
Dn
tAC
tOH
Delay length n
(0)
(1)
(2)
(3)
Qn
262144 ≥ n ≥ 16
WE = "L"
© 2002 MITSUBISHI ELECTRIC CORPORATION
20
MITSUBISHI <DIGITAL ASSP>
M66287FP
262144-word x 8-bit x 3-FIELD MEMORY
SHORTEST READING of WRITTEN DATA in N CYCLE WHEN WRITE and READ OPERATED
ASYNCHRONOUSLY
The intervals of 16 cycles or more between a write cycle and a read cycle should be secured and WCK and RCK should be
inputted for 16 cycles or more based on beginning of write n cycle at any timing to read written data (data fetched at the
rising edge of WCK shown *1 in the following figure) with n cycles on write side.
On read side, n cycles should be started after the completion of n+15 cycles on write side (∆t ≥0 in the following figure).
Output data becomes undefined when these restrictions are not filled.
Reference
16 cycles or more are required in WCK.
n-1 cycle
n cycle
n+1 cycle
n+14 cycle
n+15 cycle n+16 cycle
n+17 cycle
n+18 cycle
n+19 cycle
WCK
Dn
*1
(n+14)
(n+16)
(n+19)
(n-1)
(n)
(n+1)
(n+15)
(n+17)
(n+18)
16 cycles or more are required in RCK.
n-1 cycle
∆ t ≥ 0
n cycle
n+1 cycle
RCK
Qn
(n)
invalid
(n+1)
LONGEST READING of WRITTEN DATA in N CYCLE : 1-LINE DELAY
Data output Qn of n cycle <1>* can be read immediately before until the start of n cycle <1>* on read side and the start of
n cycle <2>* on write side over lap each other.
n cycle <1>*
0 cycle <2>*
n cycle <2>*
WCK
Dn
(n-1)<1>*
(n)<1>*
(0) <2>*
(n-1) <2>*
(n) <2>*
n cycle <0>*
0 cycle <1>*
n cycle <1>*
RCK
Qn
(n-1)<0>*
(n) <0>*
(0) <1>*
(n-1) <1>*
(n) <1>*
<0>*, <1>* and <2>* indicate a line value.
© 2002 MITSUBISHI ELECTRIC CORPORATION
21
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