M66282FP [RENESAS]
8192 × 8-Bit Line Memory; 8192 × 8位直插式内存
| 型号： | M66282FP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8192 × 8-Bit Line Memory |
| 文件： | 总14页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M66282FP
8192 × 8-Bit Line Memory
REJ03F0255-0200
Rev.2.00
Sep 14, 2007
Description
The M66282FP is high speed line memory that uses high performance silicon gate CMOS process technology and
adopts the FIFO (First In First Out) structure consisting of 8192 words × 8 bits.
The M66282FP, performing reading and writing operations at different cycles independently and asynchronously, is
optimal for buffer memory to be used between equipment of different data processing speeds.
Features
•
•
•
•
•
•
•
•
Memory configuration:
High speed cycle:
High speed access:
Output hold:
8192 words × 8 bits (dynamic memory)
25 ns (Min)
18 ns (Max)
3 ns (Min)
Reading and writing operations can be completely carried out independently and asynchronously
Variable length delay bit
Input/output:
Output:
TTL direct connection allowable
3 states
Application
Digital copying machine, laser beam printer, high speed facsimile, etc.
Block Diagram
Data inputs
D0 to D7
Data outputs
Q0 to Q7
13 14 15 16 21 22 23 24
1 2 3 4 9 10 11 12
Input buffer
Output buffer
REB
20
19
5
6
WEB
Write
Read
enable input
enable input
Memory array
RRESB
Read
WRESB
Write
8192 × 8 bits
reset input
reset input
17
18
8
7
RCK
WCK
Write
clock input
Read
clock input
GND
VCC
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 1 of 13
M66282FP
Pin Arrangement
M66282FP
1
2
24
23
22
21
20
19
18
17
16
15
14
13
Q0
Q1
D0
D1
Data input
Data output
3
Q2
D2
4
Q3
D3
Read enable input
Read reset input
5
Write enable input
REB
RRESB
GND
RCK
Q4
WEB
6
WRESB Write reset input
VCC
7
8
Read clock input
Data output
Write clock input
WCK
D4
9
10
11
12
Q5
D5
Data input
Q6
D6
Q7
D7
(Top view)
Outline: PRSP0024GA-A (24P2Q-A)
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 2 of 13
M66282FP
Absolute Maximum Ratings
(Ta = 0 to 70°C, unless otherwise noted)
Item
Symbol
Ratings
−0.3 to +4.6
−0.3 to VCC + 0.3
−0 3 to VCC + 0 3
300
Unit
V
Conditions
Supply voltage
Input voltage
Output voltage
VCC
VI
Value based on the GND pin
V
VO
V
Power dissipation
Pd
mW
°C
Storage temperature
Tstg
−55 to 150
Recommended Operating Conditions
Item
Symbol
VCC
Min
2.7
Typ
3.15
0
Max
3.6
Unit
V
Supply voltage
Supply voltage
GND
V
Operating temperature
Topr
0
70
°C
Electrical Characteristics
(Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item
Symbol
VIH
Min
2.0
Typ
Max
Unit
V
Test Conditions
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
High-level input current
VIL
0.8
V
VOH
VOL
V
CC − 0.4
V
IOH = −4 mA
0.4
1.0
V
IOL = 4 mA
VI = VCC
IIH
µA
WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 to D7
Low-level input current
IIL
−1.0
µA
VI = GND WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 to D7
Off-state high-level output current
Off-state low-level output current
lOZH
IOZL
ICC
5.0
−5.0
70
µA
µA
Vo = VCC
Vo = GND
Average supply current during
operation
mA VI = VCC, GND, Output open
WCK, tRCK = 25 ns
t
Input capacitance
CI
10
15
pF
pF
f = 1 MHz
f = 1 MHz
Off-time output capacitance
CO
Function
When write enable input WEB is set to "L", the contents of data inputs D0 to D7 are read in synchronization with a
rising edge of write clock input WCK to perform writing operation. When this is the case, the write address counter is
also incremented simultaneously.
When WEB is set to "H", the writing operation is inhibited and the write address counter stops.
When write reset input WRESB is set to "L", the write address counter is initialized.
When read enable input REB is set to "L", the contents of memory are output to data outputs Q0 to Q7 in
synchronization with a rising edge of read clock input RCK to perform reading operation. When this is the case, the
read address counter is incremented simultaneously.
When REB is set to "H", the reading operation is inhibited and the read address counter stops. The outputs are placed
in a high impedance state.
When read reset input RRESB is set to "L", the read address counter is initialized.
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 3 of 13
M66282FP
Switching Characteristics
(Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item
Access time
Symbol
Min
3
Typ
Max
18
Unit
ns
tAC
tOH
Output hold time
ns
Output enable time
Output disable time
tOEN
3
18
ns
tODIS
3
18
ns
Timing Requirements
(Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item
Write clock (WCK) cycle
Symbol
tWCK
Min
25
11
11
25
11
11
7
Typ
Max
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Write clock (WCK) "H" pulse width
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
tWCKH
tWCKL
tRCK
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
Input data setup time for WCK
Input data hold time for WCK
Reset setup time for WCK/RCK
Reset hold time for WCK/RCK
Reset non-selection setup time for WCK/RCK
Reset non-selection hold time for WCK/RCK
WEB setup time for WCK
tRCKH
tRCKL
tDS
tDH
3
tRESS
tRESH
tNRESS
tNRESH
tWES
tWEH
tNWES
tNWEH
tRES
7
3
7
3
7
WEB hold time for WCK
3
WEB non-selection setup time for WCK
WEB non-selection hold time for WCK
REB setup time for RCK
7
3
7
REB hold time for RCK
tREH
3
REB non-selection setup time for RCK
REB non-selection hold time for RCK
Input pulse up/down time
tNRES
tNREH
tr, tf
7
3
Data hold time*
tH
Notes: Perform reset operation after turning on power supply.
For 1 line access, the following conditions must be satisfied:
*
WEB high-level period ≤ 20 ms − 8192 • tWCK − WRESB low-level period
REB high-level period ≤ 20 ms − 8192 • tRCK − RRESB low-level period
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 4 of 13
M66282FP
Switching Characteristics Measurement Circuit
VCC
RL = 1 kΩ
Qn
SW1
CL = 30 pF: tAC, tOH
Qn
SW2
CL = 5 pF: tOEN, tODIS
RL = 1 kΩ
Input pulse level:
0 to 3 V
Input pulse up/down time: 3 ns
Judging voltage Input: 1.3 V
Output: 1.3 V (However, tODlS (LZ) is judged with 10% of the output amplitude, while tODIS (HZ) is
judged with 90% of the output amplitude.)
Load capacitance CL includes the floating capacity of connected lines and input capacitance of probe.
Item
SW1
Close
Open
Close
Open
SW2
Open
Close
Open
Close
tODIS (LZ)
tODIS (HZ)
tOEN (ZL)
tOEN (ZH)
tODIS and tOEN Measurement Condition
3 V
RCK
1.3 V
1.3 V
GND
3 V
REB
GND
tODIS (HZ)
tOEN (ZH)
VOH
90%
1.3 V
Qn
tODIS (LZ)
tOEN (ZL)
Qn
1.3 V
VOL
10%
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 5 of 13
M66282FP
Operation Timing
Write Cycle
n cycle
n + 1 cycle
n + 2 cycle
Disable cycle
n + 3 cycle n + 4 cycle
WCK
tWCK
tWCKH tWCKL tWEH tNWES
tNWEH tWES
WEB
Dn
tDS tDH
(n)
(n + 1)
(n + 2)
(n + 3)
(n + 4)
WRESB = "H"
Write Reset Cycle
n − 1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
2 cycle
WCK
tWCK
tNRESH tRESS
tRESH tNRESS
WRESB
tDS tDH
(n − 1)
(n)
(0)
(1)
(2)
Dn
WEB = "L"
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 6 of 13
M66282FP
Matters that Needs Attention when WCK Stops
n cycle
n + 1 cycle
n cycle
Disable cycle
WCK
WEB
tWCK
tNWES
tDS tDH
tDS tDH
Dn
(n)
(n)
Period for writing data (n)
into memory
Period for writing data (n)
into memory
WRESB = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level
period of n + l cycle. The writing operation is complete at the falling edge after n + l cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n + l cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 7 of 13
M66282FP
Read Cycle
n cycle
n + 1 cycle
n + 2 cycle
Disable cycle
n + 3 cycle n + 4 cycle
RCK
REB
tRCK
tRCKH tRCKL tREH tNRES
tNREH tRES
tAC
tODIS
Reset cycle
(0)
tOEN
HIGH-Z
(n)
(n + 1)
(n + 2)
(n + 3)
tOH
(n + 4)
Qn
RRESB = "H"
Read Reset Cycle
n − 1 cycle
n cycle
0 cycle
1 cycle
2 cycle
RCK
tRCK
tNRESH tRESS
tRESH tNRESS
RRESB
tAC
(n − 1)
(n)
(0)
(0)
tOH
(1)
(2)
Qn
REB = "L"
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 8 of 13
M66282FP
Variable Length Delay Bit
1 Line (8192 Bits) Delay
Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK
before read cycle to easily make 1 line delay.
8192 cycle 8193 cycle 8194 cycle
0 cycle
1 cycle
2 cycle
8190 cycle 8191 cycle
(0')
(1')
(2')
WCK
RCK
tRESS tRESH
WRESB
RRESB
tDS tDH
tDS tDH
(0)
(1)
(2)
(8189)
(0')
(8190)
(8191)
(1')
(1)
(2')
(2)
(3')
(3)
Dn
Qn
tAC
tOH
8192 cycle
(0)
WEB, REB = "L"
n-bit Delay Bit
(Reset at cycles according to the delay length)
n cycle n + 1 cycle n + 2 cycle n + 3 cycle
(0') (1') (2') (3')
0 cycle
1 cycle
2 cycle
n − 2 cycle n − 1 cycle
WCK
RCK
tRESS tRESH
tRESS tRESH
WRESB
RRESB
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 3)
(n − 2)
(n − 1)
(0')
(1')
(1)
(2')
(2)
(3')
(3)
Dn
Qn
tAC
tOH
m cycle
(0)
WEB, REB = "L"
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 9 of 13
M66282FP
n-bit Delay 2
(Slides input timings of WRESB and RRESB at cycles according to the delay length)
0 cycle
1 cycle
2 cycle n − 2 cycle n − 1 cycle
n cycle
n + 1 cycle n + 2 cycle n + 3 cycle
WCK
RCK
tRESS tRESH
WRESB
RRESB
tRESS tRESH
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 2)
(n − 1)
(n)
(n +1)
(n +2)
(2)
(n +3)
(3)
Dn
Qn
tAC
tOH
m cycle
(0)
(1)
WEB, REB = "L"
m ≥ 3
n-bit Delay 3
(Slides address by disabling REB in the period according to the delay length)
0 cycle
1 cycle
2 cycle
n − 1 cycle
n cycle
n + 1 cycle n + 2 cycle n + 3 cycle
WCK
RCK
tRESS tRESH
WRESB
RRESB
tNREH tRES
REB
Dn
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 2)
(n − 1)
(n)
(n + 1)
(n + 2)
(n + 3)
tAC
tOH
m cycle
HIGH-Z
(0)
(1)
(2)
(3)
Qn
WEB = "L"
m ≥ 3
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 10 of 13
M66282FP
Reading Shortest n-cycle Write Data "n"
(Reading side n − 1 cycle starts after the end of writing side n − 1 cycle)
When the reading side n − 1 cycle starts before the end of the writing side n + l cycle, output Qn of n cycle is made
invalid. In the following diagram, reading operation of n − 1 cycle is invalid.
n cycle
n + 1 cycle
n + 2 cycle
n + 3 cycle
WCK
Dn
(n)
(n +1)
(n +2)
(n +3)
n − 2 cycle
n − 1 cycle
n cycle
RCK
Qn
Invalid
(n)
Reading Longest n-cycle Write Data "n": 1 Line Delay
(When writing side n-cycle <2>* starts, reading side n cycle <1>* then starts)
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle
<2>* overlap each other.
n cycle <1>*
0 cycle <2>*
n cycle <2>*
WCK
Dn
(n − 1) <1>*
(n) <1>*
(0) <2>*
(n − 1) <2>*
(n) <2>*
n cycle <0>*
0 cycle <1>*
n cycle <1>*
RCK
Qn
(n − 1) <0>*
(n) <0>*
(0) <1>*
(n − 1) <1>*
(n) <1>*
Note: <0>*, <1>* and <2>* indicate value of lines.
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 11 of 13
M66282FP
Application Example
Sub Scan Resolution Compensation Circuit with Laplacian Filter
N
M66282
n line image data
D0 Q0
to
to
B
D7 Q7
(n + 1) line
image data
Compensated
image data
× 2
1 line
delay
× K
M66282
D0 Q0
A
(n − 1) line
image data
to
to
D7 Q7
1 line
delay
Main scan direction
A
N
B
(n − 1) line
n line
N' = N + K { (N − A) + (N − B) }
= N + K {2N − (A + B)}
K: Laplacian coefficient
(n + 1) line
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 12 of 13
M66282FP
Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
24P2Q-A
MASS[Typ.]
0.2g
P-SSOP24-5.3x10.1-0.80
PRSP0024GA-A
24
13
NOTE)
1. DIMENSIONS "*1" AND "*2"
F
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
1
12
Index mark
Dimension in Millimeters
Reference
c
A2
A1
*2
Symbol
D
Min Nom Max
D
E
10.0 10.1 10.2
5.2 5.3 5.4
A2
A
1.8
2.1
A1
bp
c
0.1 0.2
0.35 0.45
0
0.3
0.18
0°
*3
0.25
0.2
bp
e
y
8°
HE
e
y
7.5 7.8 8.1
Detail F
0.65
0.95
0.10
0.8
L
0.4 0.6 0.8
REJ03F0255-0200 Rev.2.00 Sep 14, 2007
Page 13 of 13
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
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but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
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