M66281FP [RENESAS]
5120 × 8-Bit × 2 Line Memory; 5120 × 8位× 2行内存
| 型号： | M66281FP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 5120 × 8-Bit × 2 Line Memory |
| 文件： | 总16页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M66281FP
5120 × 8-Bit × 2 Line Memory
REJ03F0254-0200
Rev.2.00
Sep 14, 2007
Description
The M66281FP is high speed line memory that uses high performance silicon gate CMOS process technology and
adopts the FIFO (First In First Out) structure consisting of 5120 words × 8 bits × 2.
Since memory is available to simultaneously output 1 line delay and 2 line delay data, the M66281FP is optimal for the
compensation of data of multiple lines.
Features
•
•
•
•
•
•
•
•
•
•
Memory configuration:
High speed cycle:
High speed access:
Output hold:
5120 words × 8 bits × 2 (dynamic memory)
25 ns (Min)
18 ns (Max)
3 ns (Min)
Reading and writing operations can be completely carried out independently and asynchronously
Variable length delay bit
Input/output:
Output:
Q00 to Q07:
Q10 to Q17:
TTL direct connection allowable
3 states
1 line delay
2 line delay
Application
Digital copying machine, laser beam printer, high speed facsimile, etc.
Block Diagram
Data inputs
D0 to D7
Data outputs
Q0 to Q7
Data outputs
Q10 to Q17
31 30 29 28 27 23 22 21
Input buffer
45 46 47
2
3
4
5
6
9
10 11 12 13 16 17 18
Output buffer
REB
36
35
34
42
41
40
WEB
Read
Write
enable input
enable input
RRESB
Read
reset input
WRESB
Write
reset input
Memory array
5120 words × 8 bits × 2
Memory only for 1 line delay data
Memory only for 2 line delay data
(
)
RCK
WCK
Write
clock input
Read
clock input
VCC
VCC
VCC
VCC
8
7
GND
GND
GND
GND
19
32
44
20
33
43
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 1 of 15
M66281FP
Pin Arrangement
NC
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
NC
D5
RCK
RRESB
REB
GND
VCC
D6
D7
GND
VCC
Q17
Q16
Q15
NC
M66281FP
Q00
Q01
Q02
NC
NC: No connection
(Top view)
Outline: PRQP0048JA-A (48P6S-A)
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 2 of 15
M66281FP
Absolute Maximum Ratings
(Ta = 0 to 70°C, unless otherwise noted)
Item
Symbol
Ratings
−0.3 to +4.6
−0.3 to VCC + 0.3
−0.3 to VCC + 0.3
540
Unit
V
Conditions
Supply voltage
Input voltage
Output voltage
VCC
VI
Value based on the GND pin
V
VO
V
Power dissipation
Pd
mW
°C
*
Storage temperature
Tstg
−55 to 150
Note:
*
Ta = 0 to 63°C. Ta > 63°C are derated at −9 mW / °C
Recommended Operating Conditions
Item
Symbol
VCC
Min
2.7
Typ
3.15
0
Max
3.6
Unit
V
Supply voltage
Supply voltage
GND
V
Operating temperature
Topr
0
70
°C
Electrical Characteristics
(Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item
Symbol
VIH
Min
2.0
Typ Max
Unit
V
Test Conditions
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
High-level input current
0.8
VIL
V
VOH
VOL
V
CC − 0.4
V
IOH = −4 mA
0.4
1.0
V
IOL = 4 mA
VI = VCC
IIH
µA
WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 to D7
Low-level input current
IIL
−1.0
µA
VI = GND WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 to D7
Off-state high-level output current
Off-state low-level output current
IOZH
IOZL
ICC
5.0
−5.0
150
µA
µA
VO = VCC
VO = GND
Average supply current during
operation
mA
VI = VCC, GND, Output open
t
WCK, tRCK = 25 ns
Input capacitance
CI
10
15
pF
pF
f = 1 MHz
f = 1 MHz
Off-time output capacitance
CO
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 3 of 15
M66281FP
Function
When write enable input WEB is set to "L", the contents of data inputs D0 to D7 are written into memory only for 1 line
delay data in synchronization with a rising edge of write clock input WCK to perform writing operation. When this is
the case, the write address counter of memory only for 1 line delay data is incremented simultaneously.
When WEB is set to "H", the writing operation is inhibited and the write address counter of memory only for 1 line
delay data stops.
When write reset input WRESB is set to "L", the write address counter of memory only for 1 line delay data is
initialized.
When read enable input REB is set to "L", the contents of memory only for 1 line delay data are output to data outputs
Q00 to Q07 and the contents of memory only for 2 line delay data are output to Q10 to Q17 in synchronization with a
rising edge of read clock input RCK to perform reading operation.
When this is the case, the read address counters of memory only for 1 line delay data and memory only for 2 line delay
data are incremented simultaneously.
In addition, data of Q00 to Q07 is written into memory only for 2 line delay data in synchronization with a rising edge
of RCK. When this is the case, the write address counter of memory only for 2 line delay data is then incremented.
When REB is set to "H", operation for reading data from memory only for 1 line delay and from memory only for 2 line
delay data is inhibited and the read address counter of each memory stops.
Outputs Q00 to Q07 and Q10 to Q17 are placed in a high impedance state. In addition, the write address counter of
memory only for 2 line delay data then stops.
When read reset input RRESB is set to "L", the read address counters of memory only for 1 line delay data as well as
the write address counter and read address counter of memory only for 2 line delay data are then initialized.
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 4 of 15
M66281FP
Switching Characteristics
(Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item
Access time
Symbol
tAC
Min
3
Typ
Max
18
Unit
ns
Output hold time
tOH
ns
Output enable time
Output disable time
tOEN
tODIS
3
18
ns
3
18
ns
Timing Requirements
(Ta = 0 to 70°C, VCC = 2.7 to 3.6 V, GND = 0 V, unless otherwise noted)
Item
Symbol
tWCK
Min
25
11
11
25
11
11
7
Typ
Max
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Write clock (WCK) cycle
Write clock (WCK) "H" pulse width
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
tWCKH
tWCKL
tRCK
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
Input data setup time for WCK
Input data hold time for WCK
Reset setup time for WCK/RCK
Reset hold time for WCK/RCK
Reset non-selection setup time for WCK/RCK
Reset non-selection hold time for WCK/RCK
WEB setup time for WCK
tRCKH
tRCKL
tDS
tDH
3
tRESS
tRESH
tNRESS
tNRESH
tWES
tWEH
tNWES
tNWEH
tRES
7
3
7
3
7
WEB hold time for WCK
3
WEB non-selection setup time for WCK
WEB non-selection hold time for WCK
REB setup time for RCK
7
3
7
REB hold time for RCK
tREH
3
REB non-selection setup time for RCK
REB non-selection hold time for RCK
Input pulse up/down time
tNRES
tNREH
tr, tf
7
3
Data hold time*
tH
Notes: Perform reset operation after turning on power supply.
For 1 line access, the following conditions must be satisfied:
*
WEB high-level period ≤ 20 ms − 5120 • tWCK − WRESB low-level period
REB high-level period ≤ 20 ms − 5120 • tRCK − RRESB low-level period
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 5 of 15
M66281FP
Switching Characteristics Measurement Circuit
VCC
RL = 1 kΩ
Qn
SW1
CL = 30 pF: tAC, tOH
Qn
SW2
CL = 5 pF: tOEN, tODIS
RL = 1 kΩ
Input pulse level:
0 to 3 V
Input pulse up/down time: 3 ns
Judging voltage Input: 1.3 V
Output: 1.3 V (However, tODIS (LZ) is judged with 10% of the output amplitude, while tODIS (HZ) is
judged with 90% of the output amplitude)
Load capacitance CL includes the floating capacity of connected lines and input capacitance of probe.
Item
SW1
Close
Open
Close
Open
SW2
Open
Close
Open
Close
tODIS (LZ)
tODIS (HZ)
tOEN (ZL)
tOEN (ZH)
tODIS and tOEN Measurement Condition
3 V
RCK
1.3 V
1.3 V
GND
3 V
REB
GND
tODIS (HZ)
tOEN (ZH)
VOH
90%
1.3 V
Qn
tODIS (LZ)
tOEN (ZL)
Qn
1.3 V
VOL
10%
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 6 of 15
M66281FP
Operation Timing
Write Cycle
n cycle
n + 1 cycle
n + 2 cycle
Disable cycle
n + 3 cycle n + 4 cycle
WCK
tWCK
tWCKH tWCKL tWEH tNWES
tNWEH tWES
WEB
Dn
tDS tDH
(n)
(n + 1)
(n + 2)
(n + 3)
(n + 4)
WRESB = "H"
Write Reset Cycle
n − 1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
2 cycle
WCK
tWCK
tNRESH tRESS
tRESH tNRESS
WRESB
tDS tDH
(n − 1)
(n)
(0)
(1)
(2)
Dn
WEB = "L"
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 7 of 15
M66281FP
Matters that Needs Attention when WCK Stops
n cycle
n + 1 cycle
n cycle
Disable cycle
WCK
WEB
tWCK
tNWES
tDS tDH
tDS tDH
Dn
(n)
(n)
Period for writing data (n)
into memory
Period for writing data (n)
into memory
WRESB = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level
period of n + 1 cycle. The writing operation is complete at the falling edge after n + 1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n + 1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 8 of 15
M66281FP
Read Cycle
n cycle
n + 1 cycle
n + 2 cycle
Disable cycle
n + 3 cycle n + 4 cycle
RCK
REB
tRCK
tRCKH tRCKL tREH tNRES
tNREH tRES
tAC
tODIS
Reset cycle
(0)
tOEN
Q0n
(Q1n)
HIGH-Z
(n)
(n + 1)
(n + 2)
(n + 3)
tOH
(n + 4)
RRESB = "H"
Read Reset Cycle
n − 1 cycle
n cycle
0 cycle
1 cycle
2 cycle
RCK
tRCK
tNRESH tRESS
tRESH tNRESS
RRESB
tAC
Q0n
(Q1n)
(n − 1)
(n)
(0)
(0)
tOH
(1)
(2)
REB = "L"
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 9 of 15
M66281FP
Notes on Reading of Written Data in Read Disable
When writing operation is performed at n cycle and n + 1 cycle on the writing side in the read disable period after n − 1
cycle on the reading side, output at n cycle and n + 1 cycle after read enable is invalid. For output at n + 2 cycle and
after, however, data written in the read disable period is to be output.
n − 1 cycle
n cycle
n + 1 cycle n + 2 cycle n + 3 cycle n + 4 cycle n + 5 cycle n + 6 cycle n + 7 cycle
WCK
tDS tDH
(n − 1)
(n)
(n + 1)
(n + 2)
(n + 3)
(n + 4)
(n + 5)
(n + 6)
(n + 7)
Dn
n − 1 cycle
Disable cycle
n cycle
n + 1 cycle n + 2 cycle
RCK
REB
tAC
tODIS
tOEN
Q0n
(Q1n)
HIGH-Z
(n − 1)
Invalid
Invalid
(n + 2)
WEB = "L"
WRESB = "H"
RRESB = "H"
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 10 of 15
M66281FP
Variable Length Delay Bit
1 Line (5120 Bits) Delay
Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK
before read cycle to easily make 1 line delay.
5120 cycle 5121 cycle 5122 cycle
0 cycle
1 cycle
2 cycle
5118 cycle 5119 cycle
(0')
(1')
(2')
WCK
RCK
tRESS tRESH
WRESB
RRESB
tDS tDH
tDS tDH
(0)
(1)
(2)
(5117)
(5118)
(5119)
(0')
(1')
(1)
(2')
(2)
(3')
(3)
Dn
tAC
tOH
5120 cycle
Q0n
(Q1n)
(0)
WEB, REB = "L"
n-bit Delay Bit
(Reset at cycles according to the delay length)
n cycle n + 1 cycle n + 2 cycle n + 3 cycle
(0') (1') (2') (3')
0 cycle
1 cycle
2 cycle
n − 2 cycle n − 1 cycle
WCK
RCK
tRESS tRESH
tRESS tRESH
WRESB
RRESB
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 3)
(n − 2)
(n − 1)
(0')
(1')
(1)
(2')
(2)
(3')
(3)
Dn
tAC
tOH
m cycle
Q0n
(Q1n)
(0)
WEB, REB = "L"
m ≥ 3
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 11 of 15
M66281FP
n-bit Delay 2
(Slides input timings of WRESB and RRESB at cycles according to the delay length)
0 cycle
1 cycle
2 cycle n − 2 cycle n − 1 cycle
n cycle
n + 1 cycle n + 2 cycle n + 3 cycle
WCK
RCK
tRESS tRESH
WRESB
RRESB
tRESS tRESH
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 2)
(n − 1)
(n)
(n + 1)
(n + 2)
(n + 3)
Dn
tAC
tOH
m cycle
Q0n
(Q1n)
(0)
(1)
(2)
(3)
WEB, REB = "L"
m ≥ 3
n-bit Delay 3
(Slides address by disabling REB in the period according to the delay length)
0 cycle
1 cycle
2 cycle
n − 1 cycle
n cycle
n + 1 cycle n + 2 cycle n + 3 cycle
WCK
RCK
tRESS tRESH
WRESB
RRESB
tNREH tRES
REB
Dn
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 2)
(n − 1)
(n)
(n + 1)
(n + 2)
(n + 3)
tAC
tOH
m cycle
HIGH-Z
Q0n
Invalid
(1)
(2)
(3)
(Q1n)
WEB = "L"
m ≥ 3
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 12 of 15
M66281FP
Reading Shortest n-cycle Write Data "n"
(Reading side n − 2 cycle ends after the end of writing side n + 1 cycle)
When the reading side n − 2 cycle ends before the end of the writing side n + 1 cycle, output Qn of n cycle is made
invalid. In the following diagram, end of reading side n − 2 cycle and end of writing side n + 1 cycle overlap each other.
This example can read n cycle data in the shortest time. When this is the case, reading operation at n − 1 cycle is
invalid.
n cycle
n + 1 cycle
n + 2 cycle
n + 3 cycle
WCK
Dn
(n)
(n +1)
(n + 2)
(n + 3)
n − 2 cycle
n − 1 cycle
n cycle
RCK
Q0n
(Q1n)
Invalid
(n)
Reading Longest n-cycle Write Data "n": 1 Line Delay
(When writing side n-cycle <2> starts, reading side n cycle <1> then starts)
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle
<2>* overlap each other.
n cycle <1>*
0 cycle <2>*
n cycle <2>*
WCK
(n − 1) <1>*
(n) <1>*
(0) <2>*
(n − 1) <2>*
(n) <2>*
Dn
n cycle <0>*
0 cycle <1>*
n cycle <1>*
RCK
Q0n
(Q1n)
(n − 1) <0>*
(n) <0>*
(0) <1>*
(n − 1) <1>*
(n) <1>*
Note: <0>*, <1>* and <2>* indicate value of lines.
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 13 of 15
M66281FP
Application Example
Sub Scan Resolution Compensation Circuit with Laplacian Filter
N
M66281
n line image data
D0 Q00
to
to
B
D7 Q07
(n + 1) line
image data
Compensated
image data
× 2
1 line
delay
× K
A
(n − 1) line
image data
Q10
to
Q17
2 line
delay
Main scan direction
A
N
B
(n − 1) line
n line
N' = N + K { (N − A) + (N − B) }
= N + K {2N − (A + B)}
K: Laplacian coefficient
(n + 1) line
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 14 of 15
M66281FP
Package Dimensions
JEITA Package Code
P-QFP48-7x10-0.65
RENESAS Code
Previous Code
48P6S-A
MASS[Typ.]
0.3g
PRQP0048JA-A
HD
*2
D
25
38
39
24
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
48
15
Dimension in Millimeters
Reference
Symbol
Min Nom Max
D
Index mark
9.8
10.0 10.2
1
14
c
E
A2
HD
HE
A
ZD
6.8 7.0 7.2
1.85
11.7 12.0 12.3
8.7 9.0 9.3
2.15
F
A1
bp
c
0
0.2
0.13 0.15
0°
0.1 0.2
0.25 0.35
0.2
10°
*3
y
e
bp
e
x
0.65
x
L
0.13
0.10
y
Detail F
ZD
ZE
L
0.775
0.575
0.3 0.5 0.7
REJ03F0254-0200 Rev.2.00 Sep 14, 2007
Page 15 of 15
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
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Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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