M66272 [MITSUBISHI]
LCD CONTROLLER with VRAM; LCD控制器， VRAM
| 型号： | M66272 |
| 厂家： | 
Mitsubishi Group |
| 描述： | LCD CONTROLLER with VRAM |
| 文件： | 总4页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI <DIGITAL ASSP>
M66272FP
LCD CONTROLLER with VRAM
• Displayable LCD
• Binary display
Monochrome STN-LCD of up to 153600 dots(equivalent to 1/2
VGA)
• 4 gray scale display
DESCRIPTION
The M66272FP is a graphic display-only controller for dot matrix
type STN-LCD which is used widely for OA equipment, PDA,
amusement equipment, etc.
It is capable of displaying six types of LCD by combining the panel
configuration(single or dual scan), LCD display function(binary or
gray scale), LCD display data bus width(4 or 8 bit).
Monochrome STN-LCD of up to 76800 dots(equivalent to 1/4
VGA)
Reflective color STN-LCD of up to 76800 dots (equivalent to
1/4 VGA)
• Interface with MPU
• Capability of switching the interface with two-way 8/16-bit MPU
• Provides WAIT output pin(WAIT output when access from MPU
to VRAM is gained)
• Capability of controlling BHE or LWR/HWR at the interface with
a 16-bit MPU
Panel
Binary/
LCD display data
Displayable LCD size
configuration gray scale
4bit
8bit
4bit
8bit
4bit
4bit
Binary
Single scan
Equivalent to 640 x 240
Gray scale
Equivalent to 320 x 240
Equivalent to 320 x 240 x 2 screens
Equivalent to 320 x 120 x 2 screens
Binary
Dual scan
Gray scale
• Interface with LCD
• LCD display data bus is a 4-bit or 8-bit parallel output.
• 4 kinds of control signals: CP, LP, FLM and M
• Display functions
• Graphic display only
• Binary or 4 gray scale display(gray scale palette is used to set
pseudo medium 2 gray scale.)
• Reflective color(ECB) uses a gray scale function.
• Vertical scrolling is allowed within memory range.
• Additional function for LCD module built-in system
• Capability of interfacing with two-way 8/16-bit MPU(16-bit MPU
byte access is not allowed.)
The M66272FP can support the reflective color type LCD (ECB :
Electrically Controlled Birefringence).
The IC has a built-in 19200-byte VRAM as a display data memory.
All of the VRAM addresses are externally opened. Direct
addressing of display data can be performed from MPU, thus
display data processing such as drawing can be efficiently carried
out.
The built-in arbiter circuit(cycle steal system) which gives priority to
display access allows timing-free access from MPU to VRAM,
preventing display screen distortion.
The IC provides has a function for LCD module built-in system by
lessening connect pins between the MPU and the IC.
• Access from MPU to VRAM is gained via the I/O register.
• 5V or 3V single power supply
FEATURES
APPLICATION
• PPC/FAX operation panel, display/operation panel of other OA
equipment, multifunction/public telephone
• Display memory
• Built-in 19200-byte(153.6-Kbit) VRAM(Equivalent to 320 x 240
dots x 2 screens)
• PDA/electronic notebook/information terminal, portable terminal
• Game, Amusements, kid's computer etc.
• All addresses of built-in VRAM are externally opened.
PIN CONFIGURATION
(TOP VIEW)
40
65
VSS
VSS
39
66
DISPLAY DATA TRANSFER CLOCK CP
N.C
67
38
DISPLAY DATA LATCH PULSE
FIRST LINE MARKER SIGNAL
LP
FLM
N.C
N.C
CSE
VSS
VDD
37
68
69
70
71
72
73
74
75
76
77
78
79
80
36
CYCLE STEAL ENABLE
VD<0>
VD<1>
VD<2>
VD<3>
35
34
33
32
31
30
29
28
27
26
25
SWAP BUS SWAP
A<14>
A<13>
LCD DISPLAY DATA BUS
M66272FP
VD<4>
VD<5>
VD<6>
VD<7>
VDD
A<12>
MPU ADDRESS
BUS
A<11>
A<10>
A<9>
A<8>
VSS
N.C
N.C
VSS
Outline 80P6N-A
N.C : No Connection
1
MITSUBISHI <DIGITAL ASSP>
M66272FP
LCD CONTROLLER with VRAM
BLOCK DIAGRAM 1
VDD
8
23 34 42
63
52 77
15
22
ADDRESS
BUFFER
LCD CONTROL
MPU ADDRESS
BUS
A<14:0>
61
26
LCDENB
SIGNAL
DISPLAY DATA
TRANSFER CLOCK
DISPLAY DATA LATCH
PULSE
FIRST LINE MARKER
SIGNAL
LCD ALTERNATING
SIGNAL
CONTROL
REGISTER
32
66
CP
LCD
DISPLAY
TIMING
CONTROL
CIRCUIT
67
LP
68 FLM
62
M
43
DATA
BUFFER
50
53
MPU DATA BUS
D<15:0>
IOCS
60
VRAM
CONTROL REGISTER
CHIP SELECT
2
6
3
4
LCD
DISPLAY
DATA
CONTROL
CIRCUIT
69
76
VRAM CHIP SELECT
HIGH WRITE STROBE
LOW WRITE STROBE
READ STROBE
19200byte
MCS
HWR
LCD DISPLAY
DATA BUS
VD<7:0>
LWR
5
MPU I/F
CONTROL
CIRCUIT
RD
MPUSEL
12
8/16MPU SELECT
RESET
11
RESET
14
33
9
BUS HIGH ENABLE
BUS SWAP
BHE
SWAP
MPU CLOCK
WAIT
BUS
ARBITER
TIMIG
MPUCLK
7
WAIT
CSE
36
CYCLE STEAL ENABLE
CONTROL
(CYCLE
STEAL
CONTROL)
CLOCK
CONTROL
(BASIC
TIMING
CONTROL)
38 78 79
39
1
10 13 24
35
41 51
65
80
37
25
40
64
VSS
N.C
BLOCK DIAGRAM 2 (When interfacing with the LCD module built-in system and having the maximum number of pins connected with MPU)
INPUT FIXED PIN
OPEN PIN
VDD
3
6
11 12 14 15
8
23 34 42
63
52 77
7
–
26
32 33
16
22
ADDRESS
BUFFER
LCD CONTROL
SIGNAL
DISPLAY DATA
TRANSFER CLOCK
DISPLAY DATA LATCH
PULSE
FIRST LINE MARKER
SIGNAL
MPU ADDRESS
BUS
61
A<7:1>
LCDENB
CONTROL
REGISTER
66
67
CP
LP
LCD
DISPLAY
TIMING
CONTROL
CIRCUIT
68 FLM
43
62
LCD ALTERNATING
SIGNAL
M
VRAM
ADDRESS
INDEX
50
53
MPU DATA BUS D<15:0>
CONTROL REGISTER
DATA
BUFFER
REGISTER
60
DATA
PORT
REGISTER
VRAM
2
LCD
DISPLAY
DATA
CONTROL
CIRCUIT
IOCS
CHIP SELECT
69
76
19200byte
LCD DISPLAY
DATA BUS
VD<7:0>
MPU I/F
CONTROL
CIRCUIT
4
5
LOW WRITE STROBE
READ STROBE
LWR
RD
BUS
ARBITER
TIMIG
CONTROL
CLOCK
CONTROL
9
MPU CLOCK
MPUCLK
(BASIC
TIMING
CONTROL)
38 78 79
39
1
10 13 24
35
41 51
65
80
36 37
25
40
64
N.C
VSS
2
MITSUBISHI <DIGITAL ASSP>
M66272FP
LCD CONTROLLER with VRAM
PIN DESCRIPTIONS
Input/
Number
of pins
Item
Pin name
D<15:0>
Function
Output
MPU data bus
Input/
Output
16
When selecting 8 bit MPU by MPUSEL input, connect D<15:8> to VDD or VSS.
MPU address bus
When selecting 8-bit MPU, use A<14:0>.
When selecting 16-bit MPU, use A<14:1> as a address bus. By combining A<0> and BHE, access to internal
VRAM can be gained.
A<14:0>
Input
15
When driving two screens (dual scan mode), notice that the allowable setup range of VRAM address is
restricted. Use A<7:0> for selecting address of control register.
Chip select input of control register
When this pin is "L", select the internal control register. Assign to I/O space of MPU.
IOCS
MCS
Input
Input
1
1
Chip select input of VRAM
When this pin is "L", select the internal VRAM. Assign to memory space of MPU.
High-Write strobe input
When this pin is "L", write data to the internal VRAM. HWR is valid only in using 16-bit MPU
controlled byte access by LWR and HWR.
HWR
1
Input
Low-Write strobe input
When this pin is "L", write data to the internal control register or VRAM.
Input
Input
Input
1
1
1
LWR
Read strobe input
RD
When this pin is "L", read data from the internal control register or VRAM.
MPU
interface
8/16-bit MPU select input
According to MPU, set "VSS" for 8-bit MPU and set "VDD" for 16-bit MPU.
MPUSEL
Reset input
Use reset signal of MPU. When this pin is "L", initialize (reset) all internal control registers and
counters.
1
1
1
Input
Input
Input
RESET
MPU clock
Input system clock output from MPU.
MPUCLK
Bus-High-Enable input
This pin is valid when using 16-bit MPU controlling byte access with A<0> and BHE.
Connect to "VDD" to select 8-bit MPU.
BHE
Bus swap input
When selecting 16-bit MPU, connect SWAP to “VSS” to transfer VD<n:0> in order of Upper/Lower byte of
MPU data bus, reversally connect to “VDD” in order of Lower/Upper byte.
When selecting 8-bit MPU, connect to “VSS”. Even if connecting to “VDD”, use D<7:0> to access to register of
8-bit width.
Input
1
1
SWAP
WAIT output for MPU
This signal makes WAIT for MPU. Change WAIT to "L" at timing of falling edge of overlapping with MCS and
RD or LWR and HWR. And return to "H" at synchronization with the rising edge of MPUCLK after internal
processing. (Output WAIT only when requested access from MPU to VRAM is gained during cycle steal
access.)
Output
WAIT
Cycle Steal Enable output
State output of internal cycle steal access.
1
8
CSE
Output
Output
Display data bus for LCD
Transfer the LCD display data in synchronization with a rising edge of CP by putting 4-bit or 8-bit in parallel.
The VD<n:0> output pin in use differs depending on the number of driven screens and the display mode.
VD<7:0>
Display data transfer clock
1
1
Shift clock for the transfer of display data to LCD.
Take the display data of VD<n:0> to LCD at falling edge of CP.
Output
Output
CP
LP
Display data latch pulse
This clock use both as the latch pulse of display data for LCD and the transfer of scanning signal.
LP is output when it finishes transferring display data of a line.
Latch of display data and the transfer of scanning signal at falling edge of LP.
LCD
interface
First Line Marker signal output
Output the start pulse of scanning line.
This signal is "H" active, the IC for driving scanning line catches FLM at falling edge of LP.
1
1
FLM
M
Output
Output
LCD alternating signal output
Signal for driving LCD by alternating current.
LCD (ON/OFF) control signal output
Output data which is set at bit "0" of mode register (R1) in the control register. This signal can be
used for controlling the LCD power supply, because LCDENB is set to "L" by RESET.
LCDENB Output
1
7
12
5
VDD
VSS
N.C
Power supply pin
Ground
Others
No connection
3
MITSUBISHI <DIGITAL ASSP>
M66272FP
LCD CONTROLLER with VRAM
OUTLINE
• Cycle steal system
M66272FP is a graphic display only controller for displaying a dot
matrix type STN-LCD.
• LCD display mode
It is capable of displaying six types of LCD by combining the
panel configuration, binary/gray scale, LCD display data bus
width.
Cycle steal system is interact method of transforming display
data for LCD from VRAM and accessing VRAM from MPU on
the basic cycle (MAINCLK) of internal operation.
Basic timing is two clocks of MAINCLK, and assign first clock to
the access from MPU to VRAM and second clock to the transfer
of display data from VRAM to LCD.
Panel
Binary/
LCD display
data
Display
mode
Displayable LCD
size
configuration gray scale
In accessing VRAM from MPU, output WAIT. Change WAIT to
"L" at the timing of the falling edge of overlapping with MCS and
RD or LWR / HWR, and return to "H" at synchronizing with rising
edge of MPUCLK after internal processing.
For the cycle steal system, this IC provides a cycle steal control
function to improve data transfer efficiency in a line. This func-
tion gains access with the cycle steal system by taking WAIT for
MPU during the display term with necessity for the display data
transfer from built-in VRAM to LCD. On the other side, it does
not output WAIT for keeping throughput of MPU during
horizontal synchronous term (idle running term) with no
necessity for the display data transfer from VRAM to LCD side.
1
2
3
4
4bit
8bit
4bit
8bit
Equivalent to
640 x 240
Binary
Single
scan
Equivalent to
320 x 240
Gray scale
Equivalent to 320 x
240 x 2 screens
5
6
4bit
4bit
Binary
Dual
scan
Equivalent to 320 x
240 x 2 screens
Gray scale
• Control register
When accessing the control register from MPU, use pins IOCS,
LWR, RD, A<7:0> and D<7:0>. (However, use D<15:0> only
when 16-bit MPU controls the LCD module built-in support
function.)
• Output to LCD side
LCD display data VD<7:0> is output in parallel per 4 bits or 8
bits in synchronization with the rising edge of CP.
Pin VD<n:0> differs depending on the display mode.
The IC contains the following registers as control registers.
Single scan
Dual scan
Operation control
R1 to R11
Supporting LCD module built-in type
Gray scale pattern table
R12 to 14 or R15 to 16
R17 to R80
4-bit transfer
8-bit transfer
4-bit transfer
VD<7:4>
VD<3:0>
VD<3:0>
VD<7:0>
• VRAM
This IC has a built-in 19200-byte VRAM which is equivalent to
two screens of 320 x 240 dots LCD.
When accessing VRAM from MPU, use pins MCS, HWR, LWR,
RD, BHE, A<14:0> and D<15:0>.
Use of MPUSEL input can support both 8-bit MPU and 16-bit
MPU.
The VRAM address settable range is restricted depending on
the panel configuration, as follows.
1
3
2
4
5
6
Display mode
When display data for a line has been sent, LP outputs data in
synchronization with the falling edge of MAINCLK.
The IC enables adjustment to an optimum value of the frame
frequency as requested from the LCD PANEL side by adjusting
pulse width of LP with the LPW register value.
FLM is output when the display data for the first line has been
sent.
M output is an LCD alternating signal for driving LCD with
alternating current.
M output cycles can be set in lines with the M output cycle
variable register and is available to prevent LCD from
deterioration.
VRAM address settable range
♦ When single scan mode
• A<14:0>=0000 to 4AFFH --- 19200 byte
0000H
VRAM
• Gray scale display function
Gray scale display can assign 2-bit VRAM data to a picture
element of LCD display to show the display density at four
levels.
Gray scale display pattern tables 0 and 1 (4 x 4 matrix x 16
patterns x 2 medium gray scale), consisting of SRAM of 64
bytes in total, can set any gray scale display pattern.
4AFFH
♦ When dual scan mode
• For the 1st screen --- A<14:0>=0000 to 257FH --- 9600 byte
• For the 2nd screen --- A<14:0>=2580 to 4AFFH --- 9600 byte
0000H
• Application to reflective color type LCD
The above gradation display function is available to control
about four display colors on the reflective color type LCD with
ECB (Electrically Controlled Birefringence).
VRAM for the 1st screen
257FH
2580H
VRAM for the 2nd screen
4AFFH
4
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