M66271FP [MITSUBISHI]
OPERATION PANEL CONTROLLER; 操作面板控制器
| 型号： | M66271FP |
| 厂家： | 
Mitsubishi Group |
| 描述： | OPERATION PANEL CONTROLLER |
| 文件： | 总21页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
DESCRIPTION
The M66271FP is a graphic display-only controller for displaying a
high duty dot matrix type LCD which is used widely for PPC,FAX
and multi-function telephones.
●Interface with MPU
•Capability of switching 8-bit type MPU/16-bit type MPU
•With WAIT output pin (Accessing register from MPU without
WAIT output. Accessing VRAM from MPU with WAIT output.)
•Capability of controlling BHE or LWR/ HWR at the interface
with a 16-bit MPU.
It is capable of controlling a monochrome STN LCD system of up
to 320 x 240 dots.
The IC has a built-in 9600-byte VRAM as a display data memory.
All of the VRAM addresses are externally opened. Address
mapping in the MPU memory space allows direct addressing of all
display data from the MPU,thus providing efficient display data
processing such as drawing.
The built-in arbiter circuit (cycle steal system) which gives priority
to display access allows timing-free access from MPU to VRAM,
preventing display screen distortion.
The IC provides interface with a 8-bit/16-bit MPU with a
READY(WAIT) pin.
And this IC has a function for LCD module built-in system by
lessening connect pins between MPU.
●Interface with LCD
•LCD display data are 4-bit parallel output
•4 kinds of control signals: CP,LP,FLM and M
●Display functions
•Graphic display only (characters drawn graphically)
•Binary display only (without tone display function)
•Vertical scrolling is allowed within memory range
(small size LCD only)
●Additional function for LCD module built-in system
•15 kinds of interface with MPU : A<4:1>,D<7:0>,IOCS,LWR,RD
•Accessing VRAM from MPU through I/O register
•Capability of interfacing with 8-bit type MPU only
●5V single power supply
FEATURES
● Displayable LCD
●80-pin QFP
•Monochrome STN dot matrix type LCD of up to 76800
dots (equivalent to 320 × 240 dots)
•Maximum display duty : 1/240 (set to 240 Line)
: 1/255 (Max)
APPLICATION
•PPC/FAX operation panel,display/operation panel of other OA
equipment
● Display memory
•Multi-function/public telephones
•PDA/electronic notebook/information terminal
•Other applications using LCD of 76800 dots or less
•Built-in 9600-byte(76800-bit)VRAM (equivalent to one
screen of 320 × 240 dots LCD)
•All addresses of built-in VRAM are externally opened.
PIN CONFIGURATION(TOP VIEW)
40
65
VSS
VSS
39
66
DISPLAY DATA TRANSFER CLOCK CP
N.C
67
38
DISPLAY DATA LATCH PULSE LP
N.C
37
68
FIRST LINE MARKER FLM
N.C
69
36
UD<0>
N.C
35
70
UD<1>
VSS
LCD DISPLAY DATA BUS
71
34
UD<2>
VDD
72
33
UD<3>
N.C
N.C
N.C
N.C
VDD
OSC1
OSC2
VSS
N.C
N.C
M66271FP
32
31
30
29
28
27
26
25
73
74
A<13>
A<12>
A<11>
A<10>
A<9>
A<8>
VSS
75
76
MPU ADDRESS BUS
77
78
OSCILLATOR INPUT
79
80
OSCILLATOR OUTPUT
Outline 80P6N-A
N.C : No Connection
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
BLOCK DIAGRAM 1
VDD
8
23 34 42 52 63 77
15
22
26
MPU ADDRESS
BUS
ADDRESS
BUFFER
LCD CONTROL
A<13:0>
61
LCDENB
SIGNAL
DISPLAY DATA
TRANSFER CLOCK
CONTROL
REGISTER
31
66
CP
LCD DISPLAY
TIMING
CONTROL
CIRCUIT
DISPLAY DATA LATCH
PULSE
67
LP
F I RST L I NE MARKER
SIGNAL
LCD ALTERNATING
SIGNAL
68
62
FLM
M
43
DATA
BUFFER
50
53
MPU DATA BUS
D<15:0>
60
VRAM
CONTROL REGISTER
CH I P SELECT
2
6
IOCS
MCS
HWR
69
70
71
72
LCD DISPLAY
DATA
CONTROL
CIRCUIT
9600byte
VRAM CH I P SELECT
LCD DISPLAY
DATA BUS
UD<3:0>
3
HIGH WRITE STROBE
4
LOW WRITE STROBE LWR
MPU I/F
CONTROL
CIRCUIT
5
READ STROBE
RD
12
11
14
9
8/16 MPU SELECT
MPUSEL
RESET
RESET
BUS HIGH ENABLE
BHE
MPUCLK
MPU CLOCK
7
WAIT
WAIT
BUS ARBITER
TIMING
CONTROL
CLOCK
CONTROL
78
79
(CYCLE STEAL
CONTROL)
OSCILLATOR INPUT
OSC1
OSCILLATOR OUTPUT
OSC2
(BASIC TIMING
CONTROL)
1
10 13 24
35
41 51
65
32 33 36 37 38 39 73 74 75 76
25
40
64
80
VSS
N.C
BLOCK DIAGRAM 2 (In case of LCD module built-in system)
NO USE PINS
VDD
8
6
12
31
3
20
9
11
–
14 15
53
–
23
42 52 63
34 77
7
22 26
60
–
16
19
MPU ADDRESS
BUS
ADDRESS
BUFFER
LCD CONTROL
SIGNAL
DISPLAY DATA
TRANSFER CLOCK
DISPLAY DATA LATCH
PULSE
A<4:1>
61
LCDENB
CONTROL
REGISTER
66 CP
67 LP
LCD DISPLAY
TIMING
CONTROL
CIRCUIT
F I RST L I NE MARKER
SIGNAL
LCD ALTERNATING
SIGNAL
FLM
68
62
M
VRAM
ADDRESS
INDEX
REGISTER
DATA
BUFFER
43
50
MPU DATA BUS
D<7:0>
DATAPORT
REGISTER
VRAM
CONTROL REGISTER
CH I P SELECT
2
IOCS
69
70
71
72
LCD DISPLAY
DATA
CONTROL
CIRCUIT
9600byte
LCD
DISPLAY
DATA BUS
UD<3:0>
MPU I/F
CONTROL
CIRCUIT
4
5
LOW WRITE STROBE
READ STROBE
LWR
RD
BUS ARBITER
TIMING
CONTROL
CLOCK
CONTROL
78
79
OSCILLATOR INPUT
OSC1
OSC2
OSCILLATOR OUTPUT
(BASIC TIMING
CONTROL)
10 13 24 25
40 41 51
1
35
64 65
80
32 33 36 37 38 39 73 74 75 76
VSS
N.C
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
PIN DESCRIPTIONS
Number
Input/
Output
Pin
name
Item
Function
of pins
MPU data bus
Connect to MPU data bus.
Input/
Output
D<15:0>
A<13:0>
16
Selecting 8bit MPU by MPUSEL input, D<15:8> connect to VDD or VSS.
MPU address bus
Connect to MPU address bus. When selecting 8-bit MPU, use A<13:0>. And selecting
16-bit MPU, use A<13:1> for the address bus with combining A<0> and BHE by the method
of access to internal VRAM (Refer to Figure-1). Use A<4:0> for selecting address of control register.
14
Input
Chip select input of control register
When this pin is "L", select the internal control register. Assign to I/O space of MPU.
1
1
IOCS
MCS
Input
Input
Chip select input of VRAM
When this pin is "L", select the internal VRAM. Assign to memory space of MPU.
High-Write strobe input
1
When this pin is "L", data write to the internal VRAM. HWR is valid only in using 16-bit MPU
controlled byte access by LWR and HWR. (Refer to Figure-1)
HWR
Input
Low-Write strobe input
When this pin is "L", data write to the internal control register or VRAM. (Refer to Figure-1)
1
1
LWR
Input
Input
Input
MPU
interface
Read strobe input
RD
When this pin is "L", data read from the internal control register or VRAM.(Refer to Figure-1)
8/16-bit MPU select input
According to MPU, set "VSS" for 8bit MPU and set "VDD" for 16bit MPU.
MPUSEL
1
1
1
Reset input
RESET Input
Use reset signal of MPU.When this pin is "L", initialize all internal control register and counter.
MPU clock
Input of MPU clock.
MPUCLK
BHE
Input
Input
Bus-High-Enable input
This pin is valid when using 16-bit MPU controlled byte access by A<0> and BHE (Refer to Figure-
1). Connect to "VDD" when using 8-bit MPU.
Set to "L" when using the additional function for the LCD Module built-in system.
1
1
WAIT output for MPU
This signal makes WAIT for MPU.
Change WAIT "L" at timing of falling edge of overlapping with MCS and (RD or LWR or HWR).
And return to "H" at synchronizing with the rising edge of MPUCLK after internal processing.
(Output WAIT only when requested access from MPU to VRAM during cycle steal access.)
WAIT
Output
Display data bus for LCD
Transfer the LCD display data with 4-bit parallel signal.
Mutually output upper/lower data every CP output.
UD<3:0>
CP
Output
Output
4
1
Display data transfer clock
Shift clock for the transfer of display data to LCD.
Take the display data of UD<3:0> to LCD at falling edge of CP.
Display data latch pulse
This clock use both as the latch pulse of display data for LCD and the transfer of scanning signal.
LP output when finish the transfer of display data of a line.
Latch of display data and the transfer of scanning signal at falling edge of LP.
First line marker signal
Output the start pulse of scanning line.
This signal is "H" active,the IC for driving scanning line catch FLM at falling edge of LP.
LCD alternating signal output
LP
1
Output
LCD
interface
FLM
M
1
1
Output
Output
Signal for driving LCD by alternating current.
LCD(ON/OFF) control signal output
Output data which is set at bit"0 " of mode register(R1) in control register. This signal can use
for controlling the LCD power supply, because LCDENB set to "L" byRESET.
LCDENB
OSC1
1
1
Output
Input
Input pin for oscillator
Generate an internal clock.
Oscillator
Others
For crystal oscillator or external clock signal.
OSC2
VDD
1
7
Output Output pin for oscillator
Power supply.(source +5V )
Ground
VSS
12
10
N.C
No connection
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
In accessing VRAM from MPU,output WAIT. Change WAIT to
"L" at the timing of the falling edge of overlapping with MCS and
(RD or LWR/HWR). And return to "H" at synchronizing with
rising edge of MPUCLK after internal processing.
Cycle steal system can transfer data with more efficient. This
function access with the cycle steal method as taking WAIT for
MPU during the display term with necessity for the display data
transfer from built-in VRAM to LCD. On other side, don't output
WAIT for keeping throughput of MPU during horizontal
synchronous term with no necessity for the display data transfer
from VRAM to LCD side.
OUTLINE
M66271FP is graphic display only controller for displaying a dot
matrix type LCD. This IC has a built-in display data memory
(VRAM) which is equivalent to 320×240 dots LCD.
● Control register
When access the control register from MPU side, use IOCS,
LWR,RD,A<4:0> and D<7:0>. Refer to Table-1,when set control
type inputs.
Control registers are R1 – R8 for the normal mode function and
R9 – R11 for the exclusive register for the LCD module built-in
system.
Refer to the following description of cycle steal.
● VRAM
● Output to LCD side
When access VRAM from MPU side, use MCS,HWR,LWR,
RD,BHE, A<13:0> and D<15:0>. And enable to correspond to
both 8-bit and 16-bit MPU by using MPUSEL input. Refer to
Figure-1 and Table-2 – 6 for a form of VRAM and input setting
for 8/16-bit MPU.
LCD display data UD<3:0> output synchronized with the rising
edge of CP output per 4bits.
LP output synchronized with the falling edge of OSC when finish
the transfer of display data for a line.
Enable to adjust the fittest value of the frame frequency
requested by the LCD PANEL side with adjusting pulse width by
LPW register.
FLM output, when finish the transfer of display data of 1st line.
M output is the LCD alternating signal which is signal for driving
LCD by alternating current.
M-cycle enable to set variably by M-cycle variable register in
line unit, and enable to utilize for preventting LCD from being
inferior.
● Cycle steal system
Cycle steal is interact method of transferring display data for
LCD from VRAM and accessing VRAM from MPU on the basic
cycle of OSC.
Basic timing is two clocks of OSC,and assign first clock to the
access from MPU to VRAM and second clock to the transfer of
display data from VRAM to LCD.
Difference in VRAM between 8-bit and 16-bit MPU
(1) When accessing built-in VRAM by 8-bit MPU
(MPUSEL="L",BHE="H",HWR="H" :set)
A<13:0>
A<13:0>
CEC
MCS
VRAM
WEC
LWR
9600byte
DI<7:0>
D<7:0>
DO<7:0>
RD
(2) When accessing built-in VRAM by 16-bit MPU
(2-1) In case MPU use A<0> and BHE for byte access
(MPUSEL="H",HWR="H":set)
(2-2) In case MPU use LWR and HWR for byte access
(MPUSEL="H",BHE="H",A<0>="H":set)
A<13:1>
A<13:1>
A<13:1>
A<13:1>
A<0>
A<0>
VRAM
VRAM
CEC
CEC
MCS
MCS
4800byte
4800byte
WEC
WEC
LWR
LWR
(Lower byte)
(Lower byte)
DI<7:0>
D<7:0>
DI<7:0>
D<7:0>
DO<7:0>
DO<7:0>
A<13:1>
A<0>
A<13:1>
BHE
VRAM
VRAM
CEC
CEC
4800byte
4800byte
WEC
WEC
HWR
(Upper byte)
(Upper byte)
D<15:8>
DI<15:8>
D<15:8>
RD
DI<15:8>
DO<15:8>
DO<15:8>
RD
Figure-1 Difference in VRAM between 8-bit and 16-bit MPU
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
Combination of control input pins for MPU interface
Table-1 – 6 show conditions of input setting when access the control register and VRAM from MPU
(1) Access control register (Use address=A<4:0>,Data=D<7:0>)
Table-1
IOCS LWR RD
Operation
L
L
L
H
X
H
L
Write to control register
Read from control register
Invalid
H
X
(2) Writing to VRAM
(2-1) When use 8-bit MPU (MPUSEL="L",BHE=HWR="H":set)
MPU
SEL
Valid data bus
width of MPU
Table-2
MCS BHE A<0> HWR LWR Odd address Even address
L
L
H
L
H
H
L
Invalid
Write
Write
Invalid
8-bit
X
X
H
X
Invalid
Invalid
H
(2-2) When use 16-bit MPU (In MPU controls byte access with A<0> and BHE. MPUSEL=HWR="H":set)
MPU
SEL
Valid data bus
width of MPU
Table-3
MCS BHE A<0> HWR LWR
Upper byte
Lower byte
H
L
L
L
H
L
H
L
Write
Invalid
Write
Write
16-bit
Invalid
Invalid
Invalid
Upper 8-bit
H
L
H
Invalid
L
H
L
H
X
Invalid
Invalid
Invalid
Write
Invalid
Write
Lower 8-bit
Lower 8-bit
H
X
Even if A<0>="H",
enable to write
H
X
Invalid
Invalid
H
(2-3) When use 16-bit MPU (In MPU controls byte access with LWR and HWR. MPUSEL=BHE=A<0>="H":set)
MPU
SEL
Valid data bus
width of MPU
Table-4
MCS BHE A<0> HWR LWR
Upper byte
Lower byte
H
L
H
H
L
H
X
L
H
L
Write
Write
Invalid
Write
Invalid
Write
16-bit
Upper 8-bit
Lower 8-bit
H
X
Invalid
Invalid
H
(3) Reading from VRAM
(3-1) When use 8-bit MPU (MPUSEL="L",BHE="H":set)
MPU
SEL
Valid data bus
width of MPU
Table-5
MCS BHE A<0>
RD
L
Odd address
Even address
Invalid
Read
Read
L
L
H
L
8-bit
H
X
Invalid
H
X
Invalid
Invalid
H
(3-2) When use 16-bit MPU (MPUSEL="H":set)
MPU
SEL
Valid data bus
width of MPU
Table-6
MCS BHE A<0>
RD
Upper byte
Read
Lower byte
Read
16-bit
H
L
X
X
L
H
Invalid
Invalid
H
X
Note:Avoid setting combination except above,as cause of error action
:X="L" or "H"
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
Description of cycle steal
BASIC TIMING
Access
from MPU
to VRAM
Data transfer
from VRAM
to LCD
Basic timing of M66271FP is two clocks of OSC
MPU
LCD
(internal clock after dividing OSC1 input).
Assign first clock to accessing from MPU to VRAM
and second clock to transferring of display data
from VRAM to LCD
OSC
(Internal clock after
dividing OSC1 input)
CP output
(Display data transfer)
Basic cycle
Figure-2 BASIC TIMING
Operation cycle of MPU access(during WAIT output)
Writing or Reading operation for VRAM during cycle steal
needs 1 cycle in best case or 3 cycles in worst case,
according to the condition of the internal cycle steal at staring
access requested from MPU.
Ex.) Assuming that MCS input is later than RD,LWR and HWR input.
Cycle of
LCD access
Cycle of
LCD access
Cycle of
MPU access
Cycle of
LCD access
Cycle of
MPU access
Best case
Operation cycle of MPU access
MCS
WAIT
Cancel WAIT,when synchronize
with rising edge of MPUCLK
MPUCLK
Worst case
Operation cycle of MPU access
MCS
WAIT
Cancel WAIT,when synchronize
with rising edge of MPUCLK
MPUCLK
Figure-3 Operation cycle of MPU access
Function of cycle steal control
M66271FP has a function for processing data of a line with
more efficient. This function access with the cycle steal
method as taking WAIT for MPU during the display term
with necessity for the display data transfer from built-in
VRAM to LCD.
MPU during the horizontal synchronous term with no necessity
for the display data transfer from VRAM to LCD side.
But certainly set a term of accessing with the cycle steal
method by CSW register, for controlling an error action near
the end of horizontal synchronous term.
On other side, don't output WAIT for keeping throughput of
Ex.) Assuming 320×240 dots LCD
1 Line
Output when finish transfer
of display data with a line
LP
CP
1
1
2
3
78
79
80
Output every transfer of
a display data
4bit transfer
UD<3:0>
Setting by CR register
Displaying term (Cycle steal method)
Setting by LPW register
Horizontal synchronous term
(No necessity for data transfer from VRAM to LCD side)
(Necessity for data transfer from VRAM to LCD side)
CSE
(Internal signal)
Setting by CSW register
Start WAIT for MPU according to
cycle steal access.
Access with bus timing of MPU
without WAIT for MPU.
Start WAIT for MPU in timing of CSE "H"
according to bus timing of MPU.
Figure-4 Function of cycle steal control
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
Handling of oscillator pin
<1> Crystal oscillator
<2> Input from external clock directly
Crystal oscillator
Clock
generator
OSC1
OSC1
C1
C2
M66271FP
M66271FP
Rf
OSC2
Open
OSC2
Rd
As far as possible, connect C,R and the crystal oscillator at near the pin.
Figure-5 Oscillator pin
Additional function for LCD module built-in system
As all of the VRAM address in M66271FP are
externally opened for addressing VRAM from MPU
directly.
When consider the LCD module built-in system,connect
pins are increased.
Outline of the additional function for the LCD module built-in system
● Interface pins with MPU
15 kinds of Interface with MPU:A<4:1>,D<7:0>,IOCS,LWR,RD
● Method of accessing the internal VRAM
Access the internal VRAM through the VRAM address index
register (IDXL,IDXH) and the Data port register (DP) which are
used for I/O register.
But M66271FP has an additional function for the LCD
module built-in system by lessening connect pins.
The following show the process of accessing VRAM.
● No use pins set the following.
Setting to MPUSEL,BHE="L"
HWR="H",MCS="H",WAIT= open,MPUCLK="L",MPUSEL="L",
BHE="L",A<0>="L",A<13:5>="L",D<15:8>="L",
● RESET=Power on reset or soft ware reset.
(In case of soft ware reset RESET ="H" :set)
Select VRAM address index register (IDXL,
IDXH),and write access address(14bit) as
data.
● Enable to change IDXL and IDXH,even if either.
● Access the DP after writing the mode register (DISP(R1-D2)) =" 0".
Always enable to access (CSES register ="0"),because the display
signal fix "H" or "L" in DISP="0" and a term is no wait access.
● Access DP without WAIT function.
● VRAM address is automatically increased of +1 ,when finished
access to DP.
When access to continuous address,it doesn't need to set IDXL
and IDXH.
Select Data port register (DP).
Reading/Writing data for appointed
VRAM address.
VRAM address is increased of +1.
Application
MPU side
LCD side
Common
driver
A<4:1>
D<7:0>
Graphic LCD PANEL
IOCS
LWR
RD
M66271FP
Segment driver
Crystal
Oscillator
LCD module of small size for only graphics
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
Control register
M66271FP has 9 kinds of control register.
To set mode from MPU to control register,use IOCS,
LWR,RD,A<4:0> and D<7:0>.
(1) Kind of control register
Control register Table
Data
Kind of register
Address
Functions of register
R/W
No.
Name
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
R/W
D6 – D0 set the basic mode.
D7 is the status register of cycle steal
state.
CSES RESET
DISP
REV LCDE
OSCC
CR
R1
R2
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
Mode register
D7=Only
"R"
Horizontal display
character number
register
Set the number of horizontal display
characters per line.
W
W
W
W
Horizontal
R3 synchronous pulse
LPW
CSW
Set the pulse width of LP per line.
width register
Cycle steal enable
width register
Set the term of cycle steal enable access
during horizontal synchronous term.
R4
R5
R6
R7
R8
Vertical line
number register
Set the number of display line of
vertical direction.
SLT
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
SAL
SAH
MT
Set the display start address of VRAM.
Set lower 8-bit to SAL and upper 6-bit to
SAH. Max=257FH
Display start
address register
R/W
Set the cycle of LCD alternating signal
from M .
M cycle variable
register
W
Data port
register
Data port register for accessing VRAM
through the register.
R/W
DP
R9
Set the address for accessing VRAM.
Set lower 8-bit to IDXL and upper 6-bit to
IDXH. Max=257FH
And automatically increase in continuous
address .
IDXL
IDXH
R10
R11
VRAM address
index register
R/W
Note:Data port register(DP) and VRAM address index register(IDXL,IDXH) are exclusive register,when using this IC for
the LCD module built-in system.
When RESET,each register is initialize the setting which is assumed LCD size of 320×240 dots.
Then,even if each register has not setting,output the signal to LCD side ,it is possible to be alternation of LCD.
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
(2) Description of register
(2-1) Mode register [R1]
Address
R/W
Function
Reset
•Status register for identifying active or inactive in cycle steal
function.
CSES
D7
•Set "1" during active with cycle steal function.
•CSES is for only reading,not for writing.
0
0
No wait access
0
1
Cycle steal access
•Software reset.
•Surely return to reset off after reset on.
D6 RESET
0
1
Reset OFF
Reset ON
OSCC
•Set the division of OSC clock for internal operation from
OSC1 input pin.
•When reset,OSCC=000,OSC1 clock doesn't divide.
Division of OSC1
D5 D4 D3
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
•Don't set except left table.
000
1/2 Division
1/4 Division
1/8 Division
1/16 Division
R/W
00000
D7=
Only
"R"
•Control the displaying ON/OFF of LCD.
•When reset,DISP=0,set display OFF.
D2 DISP
0
0
0
1
Display OFF
Display ON
•REV(D1) set "1", and when DISP= "0" display data UD<3:0> output "1" in
reversal mode.
•Control normal/reversal of LCD display.
•When reset,REV=0,set normal display .
•In using LCD of permeation method,REV="1" has effect.
D1 REV
0
1
Normal display
Reversal display
•Set the output data from LCDENB output pin.
D0 LCDE
•When reset,LCDE=0,LCDENB output "0"(VSS potential).
•This function is prepared for controlling the voltage of LCD.
When the power supply is ON after finish each register setting ,LCDE="1",supply
voltage of LCD. Conversely for setting power supply OFF,first LCDE="0",the
voltage of LCD is OFF. Therefore enable to prevent LCD from being unusual
voltage as DC.
0
1
LCDENB="0"output
LCDENB="1"output
0
This function use for satisfy the need of LCD.
(2-2) Horizontal display characters number register [R2]
R/W
Address
Function
Reset
CR
Character
number
Display dot
number
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
2
8
00010
W
28H
16
1
1
1
1
1
1
63
504
•The number of horizontal display characters per line can set to the extent of max=504 dots(=63 characters)
•When reset,CR= "28H"(=40 characters =320 dots)
Note: Definition of the number of display characters
The number of display characters means data which is corresponding with 1 byte of VRAM.
In case of binary,1 bit of VRAM corresponds to 1 dot of display,then 1 character means 8 dots of display.
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
(2-3) Horizontal synchronous pulse width register [R3]
Address R/W
Function
Reset
LPW
Character
number
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
2
00100 W
01H
1
1
1
1
1
1
1
1
255
•Set the length of horizontal synchronous pulse width which appeared per line in character unit.
Horizontal synchronous pulse output from LP output pin,and use for changing serial/parallel of displaying data.
Adjusting this pulse width is possible to set frame frequency the fittest value.
And the actual LP output pulse is (LPW setting value - 1CP) in consideration of timing with CP output.
•When reset,LPW= "01H"(=1 character)
(2-4) Cycle steal enable width register [R4]
Address R/W
Function
Reset
CSW
Character
number
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
2
1
1
1
1
1
1
1
1
255
00110
W
00H
•During the horizontal synchronous term, set term of access by cycle steal method in character number unit.
Setting value of CSW sets below LPW value.
•When reset,CSW= "00H".
Note: Be careful with first and second byte of display data UD<3:0> output indefinite data when setting
value of CSW is still reset (00H).
Surely CSW set over 01H.
(When select 8-bit MPU,1 byte is indefinite.
When 16-bit and SAL:D<0>=0, 2 byte are indefinite.
When 16-bit and SAL:D<0>=1, 1 byte is indefinite.)
(2-5) Vertical line number register [R5]
Address R/W
Function
Reset
SLT
Vertical line
number
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
2
01000
W
F0H
1
1
1
1
1
1
1
1
255
•SLT combine the setting of display driving duty of LCD.
•Setting of SLT is sure to adjust to the number of display line of LCD.
•When reset,SLT= "F0H"(=240 lines).
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
(2-6) Display start address register [R6,R7]
Address R/W
Function
Reset
SAH
SAL
Display start
address
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0000H
0001H
0002H
01010
SAL
1
0
0
1
0
1
0
1
1
1
1
1
1
1
257FH
0000H
R/W
•D6 and D7 output "0" when read SAH.
•It is possible to set display start address to the extent of 257FH (=9600 address).
•Don't set over 2580H.
•When reset,SAL and SAH= "0000H".
•Display start address is established by the writing data to SAH register. Even if only change SAL,
surely set SAH after SAL.
•When select 8-bit MPU,start address set in SAL <D7 – D0> + SAH <D5 – D0>.
When select16-bit MPU,start address set in SAL <D7 – D1> + SAH <D5 – D0>.
•Even if selecting 16-bit MPU,enable to set display start address in character unit.
In case the display reading data from VRAM start at D<15:12>,set SAL <D0>="0",
and if start at D<7:4>,set SAL <D0>="1". (Refer to Figure-8)
01100
SAH
(2-7) M cycle variable register [R8]
Address R/W
Function
Reset
MT
Cycle of M
D7 D6 D5 D4 D3 D2 D1 D0
Toggle change at every 1 frame.
Toggle change at every 1 line(1LP).
Toggle change at every 2 lines.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
01110
W
00H
Toggle change at every 255 lines.
1
1
1
1
1
1
1
1
•Set the cycle of M. In case of MT=01H,M repeat reversal(toggle) at every 1 line (at every 1 count of LP).
•When reset,MT="00H",toggle M signal at every 1 frame.
•We recommend this register set suitable value for user's LCD.
(2-8) Data port register [R9]
Address
R/W
Function
Reset
DP
Data port (8bit)
D7 D6 D5 D4 D3 D2 D1 D0
XXH
10000
R/W
(indefinite)
•Exclusive data port register for the LCD module built-in system.
Reading or writing 8bit data between MPU and VRAM through this register.
•VRAM address index register (IDXL,IDXH) is increased of +1,when finished access to DP.
•Output indefinite data when reset.
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
(2-9) VRAM address index register [R10,R11]
Address R/W
Function
Reset
IDXH
IDXL
Accessing
VRAM address
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
10010
IDXL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0000H
0001H
0002H
0000H
R/W
1
0
0
1
0
1
0
1
1
1
1
1
1
1
257FH
•Exclusive VRAM address index register for the LCD module built-in system.
10100
IDXH
•It is possible to change the register only one side,because IDXH and IDXL are independent each other.
•It is possible to set VRAM access address to the extent of 257FH (=9600 address).
•Don't set address over 2580H.
•D6 and D7 output "0" when read IDXH
•When reset,IDXL and IDXH="0000H".
Description of LCD display
Relation between setting of control register and LCD displaying
1 horizontal line
CR
LPW
CSW
Expectant
LCD PANEL
SLT
Condition of control register
>
(CR × 8)× SLT 76800 dots
—
1 horizontal line
× Vertical line number
SLT
CR
LPW
Horizontal syncronous pulse width
Character number of horizontal display
OSC
2
1
1
2
3
n-2
n-1
n
CP
Data is indefinite
UD<3:0>
1 Character number=8 dots display
LP
(1) Time for proccessing a horizontal line(TH)
CR, LPW,CSW : Unit of character number
SLT : Unit of line number
2
×
TH =
(CR+LPW)
fOSC : Internal OSC clock frequency
after dividing OSC1 input
fOSC
(2) Time for proccessing a frame(TFR)
By adjusting LPW,it is possible to set a frame frequency
which is requested from LCD PANEL the fittest value.
TFR= TH × SLT
Figure-6 Relation between setting of control register and LCD displaying
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
Relation between address of VRAM and LCD display
ex.1) When display start address =0000H
0000H 0001H
VRAM address mapping on the LCD PANEL
0000H 0001H
VRAM
9600byte
LCD
PANEL
SLT line
257EH 257FH
257EH 257FH
CR×8 dots
ex.2) When display start address =1000H
0000H 0001H
1000H 1001H
LCD
PANEL
VRAM
9600byte
1000H 1001H
257EH 257FH 0000H 0001H
257EH 257FH
Remark) VRAM address counter return to "0000H",
after count up address to "257FH".
Figure-7 Relation between address of VRAM and LCD display
Relation between VRAM data ,LCD display and display start address register
(1) When select 8-bit MPU
UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0
LCD display data
D7
1
D6
0
D5
1
D4
0
D3
0
D2
1
D1
0
D0
1
Data of one address for VRAM
LCD PANEL
(2) When select 16-bit MPU (SAL :D0="0")
UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0
LCD display data
D15 D14 D13 D12
D11 D10
D9
0
D8
1
D7
0
D6
0
D5
0
D4
0
D3
1
D2
1
D1
1
D0
1
Data of one address for VRAM
1
0
1
0
0
1
LCD PANEL
(3) When select 16-bit MPU (SAL :D0="1")
Invalid display data
UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0
LCD display data
D15 D14 D13 D12 D11 D10
D9
0
D8
1
D7
0
D6
0
D5
0
D4
0
D3
1
D2
1
D1
1
D0
1
Data of one address for VRAM
1
0
1
0
0
1
LCD PANEL
• Only upper byte data of the display start address is invalid data(cut off data).
• Output the display data normally from next address of the display start address.
Figure-8 Relation between VRAM data ,LCD display and display start address register
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
Output signal of LCD side
Ex.) Assuming 320×240 dots LCD
(In setting of CR=40characters,LPW=2characters,SLT=240lines,OSCC=1division,MT=1toggle per line)
(1) Output signal per line
Division of OSC1 = 1.
OSC1
80
1
2
79
80
1
2
Output every display data transfer.
CP
4bit parallel output
UD<3:0>
LP
Output when finish the transfer of
one line of display data.
(2) Output signal per frame
239
240
1
239
240
1
LP
FLM
M
Output at finishing the transfer of
first line display data.
Cycle of reversing output of M is
able to be set by MT register.
(3) LCDENB output signal
OSC1
LCDENB
(4) Reset – 1st line of 1st frame
RESET
OSC1
LCDENB
LP
FLM
M
"L"
1
2
3
4
5
6
CP
1st line of 1st frame
(5) 1st line – 2nd line
OSC1
LP
FLM
M
76
77
78
79
80
1
2
3
4
5
6
7
8
CP
1st line
2nd line
(6) 240th line of 1st frame – 1st line of 2nd frame
OSC1
LP
FLM
M
"L"
76
77
78
79
80
1
2
3
4
5
6
7
8
CP
240th line of 1st frame
1st line of 2nd frame
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
ABSOLUTE MAXIMUM RATINGS (Ta=0 – +70˚C unless otherwise noted)
Symbol
Parameter
Supply voltage
Conditions
Ratings
Unit
–0.3 – +6.5
V
V
VDD
VI
–0.3 – VDD+0.3
Input voltage
–0.3 – VDD+0.3
V
VO
IO
Output voltage
Output current
±10
mA
mW
˚C
Pd
600
Power dissipation
–55 – +150
Tstg
Storage temperature
RECOMMENDED OPERATING CONDITIONS (Ta=0 – +70˚C unless otherwise noted)
Limits
Symbol
Parameter
Conditions
Unit
Min.
4.5
Typ.
5.0
Max.
5.5
V
V
VDD
VSS
VI
Supply voltage
Supply voltage
Input voltage
0
V
0
0
0
VDD
VDD
+70
V
VO
Output voltage
+25
˚C
Topr
Operating temperature
ELECTRICAL CHARACTERISTICS (VDD=5V±10%, Ta=0 – +70˚C unless otherwise noted)
Limits
Parameter
Conditions
Unit
Symbol
Min.
2.2
Typ.
Max.
0.8
All inputs
except for
OSC1,RESET
and MPUSEL
VIH
VIL
High-level input voltage
Low-level input voltage
High-level input voltage
Low-level input voltage
VDD=5.5V
V
V
V
V
V
V
VDD=4.5V
VDD=5.5V
VDD=4.5V
VDD=5.0V
VDD=5.0V
VIH
VIL
3.5
OSC1
1.0
3.7
2.3
Positive-going
VT +
VT –
2.3
threshold voltage
MPUSEL,
RESET
Negative-going
1.25
threshold voltage
All outputs
except for
OSC2 and
outputs of
D<15:0>
IOH=–4mA
IOL= 4mA
IOH=–50uA
VOH
VOL
High-level output voltage
Low-level output voltage
4.1
V
V
VDD=4.5V
VDD=4.5V
0.4
VOH
High-level output voltage
4.1
V
OSC2
IOL= 50uA
VOL
IIH
Low-level output voltage
High-level input current
Low-level input current
0.4
10
V
µA
VDD=5.5V,VI=VDD
VDD=5.5V,VI=VSS
–10
µA
IIL
Off-state high-level
output current
µA
µA
IOZH
IOZL
VDD=5.5V,VO=VDD
VDD=5.5V,VO=VSS
10
D<15:0>
Off-state low-level
output current
–10
VDD=5.5V,VI=VDD or VSS
fosc=10MHz,Output=open
Operating supply current
IDD(A)
40
mA
(Average)
VDD=5.5V,
IOCS,MCS=VDD
Other's VI=VDD or VSS (valid)
Stand-by supply current
µA
IDD(S)
500
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
SWITCHING CHARACTERISTICS (VDD=5V±10%, Ta=0 – +70˚C)
Limits
Unit
Test
condition
Symbol
Parameter
Min.
Typ.
Max.
ta(IOCS-D)
ta(MCS-D)
ta(RD-D)
IOCS data access time
MCS data access time
RD data access time
Output disable time after IOCS
Output disable time after MCS
Output disable time after RD
WAIT output propagation time after MCS
WAIT output propagation time after WR
WAIT output propagation time after RD
70
ns
ns
ns
tdis(IOCS-D)
tdis(MCS-D)
tdis(RD-D)
20
40
tpHL(MCS-WAIT)
tpHL(WR-WAIT)
tpHL(RD-WAIT)
20
40
ns
ns
tpLH(CLK-WAIT)
tpd(OSC-CP)
WAIT output propagation time after MPUCLK
CP output propagation time after OSC
CL=50pF
tpLH(OSC-LP)
tpHL(OSC-LP)
LP output propagation time after OSC
40
ns
ta(UD)
40
40
40
ns
ns
ns
UD access time
tpLH(OSC-FLM)
tpHL(OSC-FLM)
FLM output propagation time after OSC
M output propagation time after OSC
tpd(OSC-M)
tpLH(OSC-LE)
tpHL(OSC-LE)
40
ns
ns
LCDENB output propagation time after OSC
Data definite time before cancelling WAIT
tpd(D-WAIT)
0
TIMING REQUIREMENTS (VDD=5V±10%, Ta=0 – +70˚C)
(1) Accessing to control register
Limits
Typ.
Test
condition
Symbol
Parameter
Unit
Min.
70
Max.
tW(IOCS)
tW(LWR)
IOCS pulse width
LWR pulse width
ns
ns
tsu(D-IOCS)
tsu(D-LWR)
Data set up time before falling edge of IOCS
Data set up time before falling edge of LWR
0
th(IOCS-D)
th(LWR-D)
Data hold time after rising edge of IOCS
Data hold time after rising edge of LWR
15
ns
ns
tsu(A-IOCS)
tsu(A-LWR)
tsu(A-RD)
Address set up time before falling edge of IOCS
Address set up time before falling edge of LWR
Address set up time before falling edge of RD
15
15
th(IOCS-A)
th(LWR-A)
th(RD-A)
Address hold time after rising edge of IOCS
Address hold time after rising edge of LWR
Address hold time after rising edge of RD
ns
(2) Accessing to VRAM
Symbol
Limits
Typ.
Test
condition
Parameter
Unit
ns
Min.
70
Max.
tW(MCS)
tW(WR)
MCS pulse width
WR pulse width
tsu(D-MCS)
tsu(D-WR)
Data set up time before falling edge of MCS
Data set up time before falling edge of WR
0
ns
ns
th(MCS-D)
th(WR-D)
Data hold time after rising edge of MCS
Data hold time after rising edge of WR
15
tsu(A-MCS)
tsu(A-WR)
tsu(A-RD)
Address set up time before falling edge of MCS
Address set up time before falling edge of WR
Address set up time before falling edge of RD
15
15
ns
ns
th(MCS-A)
th(WR-A)
th(RD-A)
Address hold time after rising edge of MCS
Address hold time after rising edge of WR
Address hold time after rising edge of RD
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
(3) Clock and accessing to LCD display
Limits
Unit
Symbol
Parameter
Test condition
MIn.
50
Typ.
Max.
tC(CLK)
MPUCLK cycle time
ns
ns
ns
ns
ns
ns
tWH(CLK)
MPUCLK "H" pulse width
tC(CLK)
2
tWL(CLK)
tC(OSC)
MPUCLK "L" pulse width
OSC cycle time
50(note)
tWH(OSC)
tWL(OSC)
OSC "H" pulse width
OSC "L" pulse width
CP cycle time
tC(OSC)
2
tC(OSC)
(1/n)
tC(CP)
tWH(CP)
tWL(CP)
CP "H" pulse width
CP "L" pulse width
tC(OSC)
2•(1/n)
2•tC(OSC)•LPW
(1/n)
tW(FLM)
FLM pulse width
ns
Note: Clock frequency of OSC1 input is less than fmax=20MHz.
Limit of OSC clock for the internal operation is fmax=10MHz.
When OSC1 is more than 10MHz from external input, set OSC clock
up to 10MHz by using division of OSCC register.
1/n =Division of OSC1
LPW=Setting value of LPW register
Division is set with rising edge of OSC1 input.
Test circuit
VDD
Input
VDD
Parameter
SW1
Closed
Open
SW2
RL=1KΩ
tdis(LZ)
tdis(HZ)
ta(ZL)
Open
Closed
Open
SW1
Closed
Open
D<15:0>
SW2
ta(ZH)
Closed
CL
(1)
(2)
DUT
Input pulse level : 0 – 3V
Input pulse rise/fall time : tr,tf=3ns
Input decision voltage : 1.5V
Output decision voltage : VDD/2
(However,tdis(LZ) is 10% of output amplitude and tdis
(HZ) is 90% of that for dezision.)
P.G
RL=1KΩ
50Ω
Outputs
except for
D<15:0>
CL
VSS
Load capacity CL include float capacity of connection
and input capacity of probe.
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
TIMING DIAGRAM
( RD = "H" )
(1) Write to control register
Without WAIT
tw(IOCS)
tw(LWR)
IOCS
LWR
"H"
tsu(D-IOCS)
th(IOCS-D)
WAIT
D<7:0>
A<4:0>
tsu(D-LWR)
th(LWR-D)
Data input is established
Address is established
tsu(A-IOCS)
tsu(A-LWR)
th(IOCS-A)
th(LWR-A)
(2) Read from control register
Without WAIT
(LWR= "H" )
IOCS
RD
"H"
WAIT
tdis(IOCS-D)
tdis(RD-D)
ta(IOCS-D)
ta(RD-D)
Data output is established
D<7:0>
tsu(A-IOCS)
tsu(A-RD)
th(IOCS-A)
th(RD-A)
A<4:0>
Address is established
Note 1: Writing/Reading operation for the control register is performed during overlapping IOCS and (LWR or RD).
Limits of IOCS,LWR and RD are prescribed by the input signal of last change to "L" in starting access,
and by the input signal of first change to "H" in ending access.
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
( RD = "H" )
(3) Write to VRAM
Term of non cycle steal access
tw(MCS)
tw(WR)
MCS
LWR
(+HWR)
"H"
tsu(D-MCS)
th(MCS-D)
WAIT
tsu(D-WR)
th(WR-D)
D<7:0>
(D<15:0>)
Data input is established
Address is established
tsu(A-MCS)
th(MCS-A)
th(WR-A)
tsu(A-WR)
A<13:0>
(+BHE)
(LWR,HWR = "H" )
(4) Read from VRAM
Term of non cycle steal access
MCS
RD
"H"
WAIT
tdis(MCS-D)
tdis(RD-D)
ta(MCS-D)
ta(RD-D)
D<7:0>
(D<15:0>)
tsu(A-MCS)
Data output is established
th(MCS-A)
th(RD-A)
tsu(A-RD)
A<13:0>
Address is established
Note 2: Writing/Reading operation for VRAM during non cycle steal access is performed during overlapping MCS and
[LWR(+HWR) or RD].
Limits of MCS,LWR(+HWR) and RD are prescribed by the input signal of last change to "L" in starting access,
and by the input signal of first change to "H" in ending access.
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
( RD = "H" )
(5) Write to VRAM
Term of cycle steal access
tC(CLK)
tWH(CLK) tWL(CLK)
MPUCLK
MCS
tw(MCS)
tw(WR)
LWR
(+HWR)
tpLH(CLK-WAIT)
tpHL(MCS-WAIT)
WAIT
tsu(D-MCS)
tsu(D-WR)
th(MCS-D)
th(WR-D)
tpHL(WR-WAIT)
D<7:0>
(D<15:0>)
Data input is established
Address is established
tsu(A-MCS)
tsu(A-WR)
th(MCS-A)
th(WR-A)
A<13:0>
(+BHE)
( LWR,HWR = "H" )
(6) Read from VRAM
Term of cycle steal access
tC(CLK)
tWH(CLK) tWL(CLK)
MPUCLK
MCS
RD
tpLH(CLK-WAIT)
WAIT
tpHL(MCS-WAIT)
tpHL(RD-WAIT)
tdis(MCS-D)
tdis(RD-D)
tpd(D-WAIT)
ta(MCS-D)
ta(RD-D)
D<7:0>
Data output is established
(D<15:0>)
tsu(A-MCS)
tsu(A-RD)
th(MCS-A)
th(RD-A)
A<13:0>
Address is established
Note 3: Reading/writing operation for VRAM during cycle steal needs 1tc(Internal) in best case or 3tc(Internal) in worst
case,according to the condition of the internal cycle steal at starting access requested from MPU.
tc(Internal) = Clock cycle time after setting division of OSC1.
Data output D in reading is established before changing WAIT to "H".
4: Limits of MCS,LWR(+HWR) and RD are prescribed by the input signal of last change to "L" in starting access,
and by the input signal of first change to "H" in ending access.
5: Always once return MCS,LWR(+HWR) or RD to "H" after canceling WAIT output.
In case of latching "L",as don't output next WAIT,this is cause of error action.
MITSUBISHI <DIGITAL ASSP>
M66271FP
OPERATION PANEL CONTROLLER
(OSCC = 1 division : set)
(7) Interface timing with LCD
<7-1> Transfer of LCD display data
OSC1
When OSCC = 1 division ,OSC clock for internal operation = OSC1 input.
*
tC(OSC)
tWH(OSC)
tWL(OSC)
tpd(OSC-CP)
tWH(CP)
tC(CP)
tWL(CP)
CP
LP
tpLH(OSC-LP)
tpHL(OSC-LP)
ta(UD)
Data is indefinite
UD<3:0>
<7-2> LCD control signal
OSC1
CP
LP
tpLH(OSC-FLM)
tpHL(OSC-FLM)
FLM
M
tW(FLM)
tpd(OSC-M)
tpLH(OSC-LE)
tpHL(OSC-LE)
LCDENB
Note 6: Output signal to LCD side is syncronized with OSC clock for internal operation.
When division is set to 1/2 – 1/16 by OSCC register, switching characteristics is defined by rising edge of OSC1.
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