STS4C3F60L [STMICROELECTRONICS]
StripFET⑩ MOSFET; 的STripFET ™ MOSFET
| 型号： | STS4C3F60L |
| 厂家： | 
ST |
| 描述： | StripFET⑩ MOSFET |
| 文件： | 总11页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STS4C3F60L
N-CHANNEL 60V - 0.045 Ω - 4A SO-8
P-CHANNEL 60V - 0.100 Ω - 3A SO-8
StripFET™ MOSFET
Table 1: General Features
Figure 1: Package
TYPE
V
R
I
D
DSS
DS(on)
STS4C3F60L (N-Channel)
STS4C3F60L (P-Channel)
60 V < 0.055 Ω 4 A
60 V < 0.120 Ω 3 A
■ TYPICAL R
■ TYPICAL R
(N-Channel) = 0.045 Ω
(P-Channel) = 0.100 Ω
DS(on)
DS(on)
■ STANDARD OUTLINE FOR EASY
AUTOMATED SURFACE MOUNT ASSEMBLY
■ LOW THRESHOLD DRIVE
DESCRIPTION
SO-8
This MOSFET is the latest development of STMi-
croelectronics unique ”Single Feature Size™”
strip-based process. The resulting transistor
shows extremely high packing density for low on-
resistance, rugged avalanche characteristics and
less critical alignment steps therefore a remark-
able manufacturing reproducibility.
Figure 2: Internal Schematic Diagram
APPLICATIONS
■ DC/DC CONVERTERS
■ BACK LIGHT INVERTER FOR LCD
Table 2: Order Codes
PART NUMBER
MARKING
PACKAGE
PACKAGING
STS4C3F60L
S4C3F60L
SO-8
TAPE & REEL
Rev. 2
September 2004
1/11
STS4C3F60L
Table 3: Absolute Maximum ratings
Symbol
Parameter
Value
N-CHANNEL
Unit
P-CHANNEL
V
Drain-source Voltage (V = 0)
60
60
V
V
V
A
DS
GS
V
DGR
Drain-gate Voltage (R = 20 kΩ)
GS
V
GS
Gate-source Voltage
± 16
I
Drain Current (continuous) at T = 25°C
4
3
D
C
Single Operating
I
Drain Current (continuous) at T = 100°C
Single Operating
2.5
16
1.9
12
A
D
C
I
( )
Drain Current (pulsed)
A
DM
P
TOT
Total Dissipation at T = 25°C
W
2
C
T
T
stg
Operating Junction Temperature
Storage Temperature
j
-55 to 150
°C
( ) Pulse width limited by safe operating area
Note: For the P-CHANNEL MOSFET actual polarity of voltages and current has to be reversed
Table 4: Thermal Data
Rthj-amb (1) Thermal Resistance Junction-ambient
(1) When mounted on 1 inch² pad of 2 oz. copper, t ≤ 10 s
62.5
°C/W
ELECTRICAL CHARACTERISTICS (T
=25°C UNLESS OTHERWISE SPECIFIED)
CASE
Table 5: On/Off
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
Drain-source
I
= 250 µA, V = 0
n-ch
p-ch
60
60
V
V
(BR)DSS
D
GS
Breakdown Voltage
Zero Gate Voltage
I
V
V
= Max Rating
DS
n-ch
1
10
µA
µA
DSS
Drain Current (V = 0)
= Max Rating, T = 125°C p-ch
GS
DS
C
I
V
V
= ± 16V
n-ch
±100
±100
nA
nA
Gate-body Leakage
GSS
GS
Current (V = 0)
= ± 16V
p-ch
DS
GS
V
GS(th)
Gate Threshold Voltage
V
= V , I = 250 µA
n-ch
p-ch
1
1.5
V
V
DS
GS
D
R
Static Drain-source On
Resistance
V
GS
V
GS
V
GS
V
GS
= 10 V, I = 2 A
0.045
0.100
0.050
0.130
0.055
0.120
0.065
0.160
Ω
Ω
Ω
Ω
DS(on)
D
n-ch
p-ch
n-ch
p-ch
= 10 V, I = 1.5 A
D
= 4.5 V, I = 2 A
D
= 4.5 V, I = 1.5 A
D
Table 6: Dynamic
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g
(1)
Forward
Transconductance
V
V
= 30 V I = 2 A
n-ch
p-ch
7
7.2
S
S
fs
DS
, D
= 10 V I = 3 A
DS
,
D
C
Input Capacitance
V
= 25V, f = 1 MHz, V = 0 n-ch
1030
630
pF
pF
iss
DS
GS
p-ch
C
Output Capacitance
n-ch
p-ch
140
121
pF
pF
oss
C
Reverse Transfer
Capacitance
n-ch
p-ch
40
49
pF
pF
rss
(1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
2/11
STS4C3F60L
ELECTRICAL CHARACTERISTICS (CONTINUED)
Table 7: Switching On
Symbol
Parameter
Test Conditions
N-CHANNEL
Min.
Typ.
Max. Unit
t
Turn-on Delay Time
V
= 30 V, I = 2 A,
n-ch
p-ch
15
124
ns
ns
d(on)
DD
D
R = 4.7 Ω, V = 4.5 V
G
GS
P-CHANNEL
Rise Time
n-ch
p-ch
28
54
ns
ns
t
r
V
DD
= 30 V, I = 1.5 A,
D
R = 4.7 Ω, V = 4.5 V
G
GS
(Resistive Load see, Figure 28)
Q
g
Total Gate Charge
N-CHANNEL
V
= 48 V, I = 4 A,
= 4.5 V
n-ch
p-ch
15
11.6
20.4
15.7
nC
nC
DD
D
V
GS
Q
Gate-Source Charge
Gate-Drain Charge
n-ch
p-ch
4
4.5
nC
nC
gs
P-CHANNEL
V
DD
= 48 V, I = 3 A,
D
V
GS
= 4.5 V
Q
gd
n-ch
p-ch
4
4.7
nC
nC
(see, Figure 31)
Table 8: Switching Off
Symbol
Parameter
Test Conditions
N-CHANNEL
Min.
Typ.
Max. Unit
t
Turn-off Delay Time
Fall Time
V
= 30 V, I = 2 A,
n-ch
p-ch
45
39
ns
ns
d(off)
DD
D
R = 4.7 Ω, V = 4.5 V
G
GS
P-CHANNEL
n-ch
p-ch
10
14.5
ns
ns
t
f
V
DD
= 30 V, I = 1.5 A,
D
R = 4.7 Ω, V = 4.5 V
G
GS
(Resistive Load see, Figure 28)
Table 9: Source-Drain Diodef
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Unit
I
SD
n-ch
p-ch
4
3
A
A
Source-drain Current
I
(2)
n-ch
p-ch
16
12
A
A
Source-drain Current (pulsed)
SDM
V
(1) Forward On Voltage
Reverse Recovery Time
I
I
= 4 A, V = 0
GS
n-ch
p-ch
1.2
1.2
V
V
SD
SD
= 3 A, V = 0
SD
GS
t
N-CHANNEL
= 4 A, di/dt = 100 A/µs
n-ch
p-ch
85
44
ns
ns
rr
I
SD
V
= 20V, T = 150°C
j
DD
Q
Reverse Recovery Charge
Reverse Recovery Current
n-ch
p-ch
85
68.2
nC
nC
rr
P-CHANNEL
= 3 A, di/dt = 100 A/µs
I
n-ch
p-ch
2
3.1
A
A
RRM
I
SD
V
DD
= 20V, T = 150°C
j
(see test circuit, Figure 29)
(1) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(2) Pulse width limited by safe operating area.
3/11
STS4C3F60L
Figure 3: .Safe Operating n-channel
Figure 6: Thermal Impedance For Complemen-
tary Pair
Figure 4: Output Characteristics n-channel
Figure 7: Transfer Characteristics n-channel
Figure 5: Transconductance n-channel
Figure 8: Static Drain-Source On Resistance n-
channel
4/11
STS4C3F60L
Figure 9: Gate Charge vs Gate-Source Voltage
n-channel
Figure 12: Capacitance Variations n-channel
Figure 10: Normalized Gate Thereshold Volt-
age vs Temperature n-channel
Figure 13: Normalized On Resistance vs Tem-
perature n-channel
Figure 11: Source-Drain Forward Characteris-
tics n-channel
Figure 14: Normalized BVdss vs Temperature
n-channel
5/11
STS4C3F60L
Figure 15: Safe Operating p-channel
Figure 18: Thermal Impedance for Comple-
mentary Pair
Figure 16: Output Characteristics p-channel
Figure 19: Transfer Characteristics p-channel
Figure 17: Transconductance p-channel
Figure 20: Static Drain-Source On Resistance
p-channel
6/11
STS4C3F60L
Figure 21: Gate Charge vs Gate-Source Volt-
age p-channel
Figure 24: Capacitances Variations p-channel
Figure 22: Normalized Gate Thereshlod Volt-
age vs Temperature p-channel
Figure 25: Normalized On Resistance vs Tem-
perature p-channel
Figure 23: Source-Drain Diode Forward Char-
acteristics p-channel
Figure 26: Normalized BVdss vs Temperature
p-channel
7/11
STS4C3F60L
Figure 27: Unclamped Inductive Load Test
Circuit
Figure 30: Unclamped Inductive Wafeform
Figure 28: Switching Times Test Circuit For
Resistive Load
Figure 31: Gate Charge Test Circuit
Figure 29: Test Circuit For Inductive Load
Switching and Diode Recovery Times
8/11
STS4C3F60L
SO-8 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.75
0.25
1.65
0.85
0.48
0.25
0.5
MIN.
MAX.
0.068
0.009
0.064
0.033
0.018
0.010
0.019
A
a1
a2
a3
b
0.1
0.003
0.65
0.35
0.19
0.25
0.025
0.013
0.007
0.010
b1
C
c1
D
45 (typ.)
4.8
5.8
5.0
6.2
0.188
0.228
0.196
0.244
E
1.27
3.81
e
0.050
0.150
e3
F
3.8
0.4
4.0
1.27
0.6
0.14
0.157
0.050
0.023
L
0.015
M
S
8 (max.)
9/11
STS4C3F60L
Table 10: Revision History
Date
Revision
Description of Changes
16-Sep-2004
2
Complete Version
10/11
STS4C3F60L
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2004 STMicroelectronics - All Rights Reserved
STMicroelectronics group of companies
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11/11
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