STS4DNF30L_06 [STMICROELECTRONICS]
Dual N-channel 30V - 0.039ohm - 4A SO-8 STripFET TM Power MOSFET; 双N沟道30V - 0.039ohm - 4A SO- 8的STripFET TM功率MOSFET![STS4DNF30L_06](http://pdffile.icpdf.com/pdf1/p00106/img/icpdf/STS4DNF30L_572476_icpdf.jpg)
型号: | STS4DNF30L_06 |
厂家: | ![]() |
描述: | Dual N-channel 30V - 0.039ohm - 4A SO-8 STripFET TM Power MOSFET |
文件: | 总12页 (文件大小:331K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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STS4DNF30L
Dual N-channel 30V - 0.039Ω - 4A SO-8
STripFET™ Power MOSFET
General features
Type
VDSS
RDS(on)
ID
STS4DNF30L
30V
<0.050Ω
4A
■ Standard outline for easy automated surface
mount assembly
■ Low threshold drive
S0-8
Description
This Power MOSFET is the second generation of
STMicroelectronics unique “Single Feature
Size™” strip-based process. The resulting
transistor shows extremely high packing density
for low on-resistance, rugged avalanche
characteristics and less critical alignment steps
therefore a remarkable manufacturing
reproducibility.
Internal schematic diagram
Applications
■ Switching application
Order codes
Part number
Marking
Package
Packaging
STS4DNF30L
S4DNF30L
SO-8
Tape & reel
November 2006
Rev 2
1/12
www.st.com
12
Contents
STS4DNF30L
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
STS4DNF30L
Electrical ratings
1
Electrical ratings
Table 1.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VDS
VGS
ID
Drain-source voltage (vgs = 0)
Gate- source voltage
30
16
4
V
V
Drain current (continuos) at TC = 25°C
Drain current (continuos) at TC = 100°C
Drain current (pulsed)
A
ID
2.5
16
2
A
(1)
IDM
A
PTOT
Total dissipation at TC = 25°C dual operating
W
1. Pulse width limited by safe operating area
Table 2.
Rthj-a (1)Thermal resistance junction-ambient Max
TJ Junction temperature
Thermal data
62.5
°C/W
°C
-55 to 150
150
Tstg Storage temperature range
°C
1. Mounted on FR-4 board (t≤10sec)
3/12
Electrical characteristics
STS4DNF30L
2
Electrical characteristics
(T
=25°C unless otherwise specified)
CASE
Table 3.
Symbol
On/off states
Parameter
Test conditions
Min.
Typ.
Max. Unit
Drain-source
V(BR)DSS
ID = 250 µA, VGS = 0
VDS = Max rating
30
V
Breakdown voltage
1
µA
µA
Zero gate voltage
IDSS
VDS=Max rating,
TC=125°C
Drain current (VGS = 0)
10
Gate-body leakage
current (VDS = 0)
IGSS
VGS
=
16V
100
nA
V
VGS(th) Gate threshold voltage
VDS = VGS, ID = 250µA
VGS = 10V, ID = 2A
1
0.039
0.046
Ω
Ω
Static drain-source on
resistance
0.050
0.060
RDS(on)
VGS = 4.5V, ID = 2A
Table 4.
Symbol
Dynamic
Parameter
Test conditions
Min.
Typ. Max. Unit
V
DS > ID(on) x RDS(on)max,,
(1)
gfs
Forward transconductance
1
3
S
ID= 4 A
Ciss
Input capacitance
Output capacitance
330
90
pF
pF
VDS = 25V, f = 1 MHz,
VGS = 0
Coss
Reverse transfer
capacitance
Crss
40
pF
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
6.5
3.6
2
9
nC
nC
nC
VDD = 24V, ID = 4A,
VGS = 10V
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 .
Table 5.
Symbol
Switching times
Parameter
Test conditions
Min. Typ. Max. Unit
V
DD=15 V, ID=2A,
td(on)
tr
Turn-on delay time
Rise time
11
ns
ns
RG=4.7Ω, VGS= 4.5V
(see Figure 12)
100
VDD=15 V, ID=2A,
RG=4.7Ω, VGS= 4.5V
(see Figure 12)
Turn-off Delay Time
Fall Time
25
22
ns
ns
td(off)
tf
4/12
STS4DNF30L
Electrical characteristics
Min Typ. Max Unit
Table 6.
Source drain diode
Parameter
Symbol
Test conditions
ISD
Source-drain current
4
A
A
V
(1)
ISDM
Source-drain current (pulsed)
Forward on voltage
16
1.2
(2)
VSD
ISD = 4A, VGS = 0
ISD = 4A, VDD = 20V
di/dt = 100A/µs,
Tj = 150°C
trr
Reverse recovery time
Reverse recovery charge
Reverse recovery current
30
18
ns
nC
A
Qrr
IRRM
1.2
(see Figure 14)
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
5/12
Electrical characteristics
STS4DNF30L
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
Figure 2. Thermal impedance
Figure 3. Output characterisics
Figure 4. Transfer characteristics
Figure 5. Transconductance
Figure 6. Static drain-source on resistance
6/12
STS4DNF30L
Electrical characteristics
Figure 7. Gate charge vs gate-source voltage Figure 8. Capacitance variations
Figure 9. Normalized gate threshold voltage Figure 10. Normalized on resistance vs
vs temperature
temperature
Figure 11. Source-drain diode forward
characteristics
7/12
Test circuit
STS4DNF30L
3
Test circuit
Figure 12. Switching times test circuit for
resistive load
Figure 13. Gate charge test circuit
Figure 14. Test circuit for inductive load
switching and diode recovery times
Figure 15. Unclamped Inductive load test
circuit
Figure 16. Unclamped inductive waveform
Figure 17. Switching time waveform
8/12
STS4DNF30L
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at : www.st.com
9/12
Package mechanical data
STS4DNF30L
SO-8 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.75
0.25
1.65
0.85
0.48
0.25
0.5
MIN.
MAX.
0.068
0.009
0.064
0.033
0.018
0.010
0.019
A
a1
a2
a3
b
0.1
0.003
0.65
0.35
0.19
0.25
0.025
0.013
0.007
0.010
b1
C
c1
D
45 (typ.)
4.8
5.8
5.0
6.2
0.188
0.228
0.196
0.244
E
1.27
3.81
e
0.050
0.150
e3
F
3.8
0.4
4.0
1.27
0.6
0.14
0.157
0.050
0.023
L
0.015
M
S
8 (max.)
10/12
STS4DNF30L
Revision history
5
Revision history
Table 7.
Date
Revision history
Revision
Changes
11-Sep-2006
15-Nov-2006
1
2
First version
The document has been reformated
11/12
STS4DNF30L
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