AN-9732_技术文档

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AN-9732

LED Application Design Guide Using BCM Power Factor

Correction (PFC) Controller for 200W Lighting System

1. Introduction

This application note presents practical step-by-step design

considerations for a Boundary-Conduction-Mode (BCM)

Power-Factor-Correction (PFC) converter employing

Fairchild PFC controller, FL7930. It includes designing the

inductor and Zero-Current-Detection (ZCD) circuit,

selecting the components, and closing the control loop. The

design procedure is verified through an experimental 200W

prototype converter.

for another power stage controller after PFC stage or be

transferred to the secondary side to synchronize the

operation with PFC voltage condition. This simplifies the

external circuit around the PFC controller and saves total

BOM cost. The internal proprietary logic for detecting input

voltage greatly improves the stability of PFC operation.

Together with the maximum switching frequency clamping

at 300KHz. FL7930 can limit inductor current within pre-

designed value at one or two cycles of the AC-input-absent

test to simulate a sudden blackout. Due to the startup-

without-overshoot design, audible noise from repetitive

OVP triggering is eliminated. Protection functions include

output over-voltage, over-current, open-feedback, and

under-voltage lockout.

Unlike the Continuous Conduction Mode (CCM) technique

often used at this power level, BCM offers inherent zero-

current switching of the boost diodes (no reverse-recovery

losses), which permits the use of less expensive diodes

without sacrificing efficiency.

The FL3930B provides an additional OVP pin that can be

used to shut down the boost power stage when output

voltage exceeds OVP level due to damaged resistors

connected at the INV pin. The FL7930C provides a PFC-

ready pin can be used to trigger other power stages when

PFC output voltage reaches the proper level (with

hysteresis). This signal can be used as the V_CCtrigger signal

An Excel^®-based design tool is available with this

application note and the design result is shown with the

calculation results as an example.

Figure 1. Typical Application Circuit

Rev. 1.0.0 • 3/23/11

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AN-9732

APPLICATION NOTE

2. Operation Principle of BCM Boost PFC Converter

The most widely used operation modes for the boost

converter are Continuous Conduction Mode (CCM) and

Boundary Conduction Mode (BCM). These two descriptive

names refer to the current flowing through the energy

storage inductor of the boost converter, as depicted in

Figure 2. As the names indicate, the inductor current in

CCM is continuous; while in BCM, the new switching

period is initiated when the inductor current returns to zero,

which is at the boundary of continuous conduction and

discontinuous conduction operations. Even though the BCM

operation has higher RMS current in the inductor and

switching devices, it allows better switching condition for

the MOSFET and the diode. As shown in Figure 2, the

diode reverse recovery is eliminated and a fast-recovery

diode is not needed. The MOSFET is also turned on with

zero current, which reduces the switching loss.

A by-product of BCM is that the boost converter runs with

variable switching frequency that depends primarily on the

selected output voltage, the instantaneous value of the input

voltage, the boost inductor value, and the output power

delivered to the load. The operating frequency changes as

the input current follows the sinusoidal input voltage

waveform, as shown in Figure 3. The lowest frequency

occurs at the peak of sinusoidal line voltage.

Figure 3. Operation Waveforms of BCM PFC

The voltage-second balance equation for the inductor is:

(1)

V_IN(t )t_ON





V_OUTV_IN(t ) t_OFF



where V_IN(t)is the rectified line voltage and V_OUTis the

output voltage.

The switching frequency of BCM boost PFC converter is:

V_OUTV_IN(t )

1

f_SW





t_ON t_OFFt_ON

V_OUT

(2)

V_OUTV_IN,PK sin



2  f_LINE t



1





Figure 2. CCM vs. BCM Control

t_ON

V_OUT

The fundamental idea of BCM PFC is that the inductor

current starts from zero in each switching period, as shown

in Figure 3. When the power transistor of the boost

converter is turned on for a fixed time, the peak inductor

current is proportional to the input voltage. Since the current

waveform is triangular; the average value in each switching

period is proportional to the input voltage. In a sinusoidal

input voltage, the input current of the converter follows the

input voltage waveform with very high accuracy and draws

a sinusoidal input current from the source. This behavior

makes the boost converter in BCM operation an ideal

candidate for power factor correction.

where V_IN,PKis the amplitude of the line voltage and f_LINEis

the line frequency.

Figure 4 shows how the MOSFET on time and switching

frequency changes as output power decreases. When the

load decreases, as shown in the right side of Figure 4, the

peak inductor current diminishes with reduced MOSFET on

time and, therefore, the switching frequency increases.

Since this can cause severe switching losses at light-load

condition and too-high switching frequency operation may

occur at startup, the maximum switching frequency of

FL7930 is limited to 300KHz.

Rev. 1.0.0 • 3/23/11

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AN-9732

APPLICATION NOTE

3. Startup without Overshoot and

AC-Absent Detection

Because feedback control speed of the PFC is typically quite

slow, there is a gap between output voltage and feedback

control. Therefore, Over-Voltage Protection (OVP) is

critical at the PFC controller. Voltage dip caused by fast

load change from light to heavy is diminished by a large

bulk capacitor. OVP is easily triggered at startup. Switching

starting and stopping by OVP at startup may cause audible

noise and can increase voltage stress at startup, which may

be higher than normal operation. This is improved if soft-

start time is very long, but too-long start time raises the time

needed for the output voltage to reach the rated value at

light load. FL7930 includes a startup without overshoot

feature. During startup, the feedback loop is controlled by

an internal proportional gain controller and, when the output

voltage reaches the vicinity of the rated value, changed to

the external compensator after an internally fixed transition

time described in the Figure 6. In short, an internal

proportional gain controller prevents overshoot at startup;

external conventional compensator takes over after startup.

Figure 4. Frequency Variation of BCM PFC

Since the design of the filter and inductor for a BCM PFC

converter with variable switching frequency should be at

minimum frequency condition, it is worthwhile to examine

how the minimum frequency of BCM PFC converter

changes with operating conditions.

Figure 5 shows the minimum switching frequency, which

occurs at the peak of line voltage as a function of the RMS

line voltage for three output voltage settings. It is interesting

that, depending on where the output voltage is set, the

minimum switching frequency may occur at the minimum

or at the maximum line voltage. When the output voltage is

approximately 405V, the minimum switching frequency is

the same for both low line (85V_AC) and high line (265V_AC).

150

Vout=385V

Vout=400V

Vout=415V

140

130

Figure 6. Startup Without Overshoot

120

110

100

90

FL7930 eliminates AC input voltage detection to save the

power loss caused by an input-voltage-sensing resistor array

and to optimize THD. Therefore, no information about input

voltage is available at the internal controller. In many cases,

the V_CCof PFC controller is supplied by an independent

power source, like standby power, so when the electric

power is suddenly interrupted during one or two AC line

periods, V_CCis still alive during that time and PFC output

voltage drops. Accordingly, the control loop tries to

compensate output voltage drop and control voltage reaches

its maximum. When AC line input voltage is live, control

voltage allows high switching current and creates stress on

the MOSFET and diode. To protect against this, FL7930

checks if the input AC voltage exists. Once controller

verifies that the input voltage does not exist, soft-start is

reset and waits until AC input voltage is applied again. Soft-

start manages the turn-on time for smooth operation after

detecting that the AC voltage is live and results in less

voltage and current stress during startup.

80

70

60

50

40

30

20

10

85

130

175

Line Voltage [V]

220

265

Figure 5. Minimum Switching Frequency vs. RMS Line

Voltage (L = 200µH, P_OUT= 200W)

Rev. 1.0.0 • 3/23/11

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AN-9732

APPLICATION NOTE

Figure 8. AC-Off Operation with AC-Absent

Detection Circuit

Figure 7. AC-Off Operation without AC-Absent

Detection Circuit

4. Design Considerations

In this section, a design procedure is presented using the

schematic in Figure 9 as a reference. A 200W PFC

application with universal input range is selected as a design

example. The design specifications are:

. Hold-up Time Requirement: Output Voltage Should Not

Drop Below 330V During One Line Cycle

. Output Voltage Ripple: Less than 8V_PP

. Minimum Switching Frequency: Higher than 50kHz

. Control Bandwidth: 5~15Hz

. Line Voltage Range: 90~265V_AC(Universal Input), 50Hz

. Nominal Output Voltage and Current: 400V/0.5A (200W)

. V_CCsupplied from auxiliary power supply.

Figure 9. Reference Circuit for Design Example of BCM Boost PFC

Rev. 1.0.0 • 3/23/11

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AN-9732

APPLICATION NOTE

[STEP-1] Define System Specifications

(Design Example) Input voltage range is universal input,

output load is 500mA, and estimated efficiency is selected

as 0.9.

.

Line Frequency Range (V_LINE,MINand V_LINE,MAX

Line Frequency (f_LINE

Output-Voltage (V_OUT

Output Load Current (I_OUT

)

V_LINE,MIN 90V_AC, V_LINE,MAX 265V_AC

f_LINE 50Hz

)

Output Power (P_OUT=V_OUT I_OUT

)

V_OUT 400V , I_OUT 500mA

  0.9

Estimated Efficiency ()

4 P_OUT

To calculate the maximum input power, it is necessary to

estimate the power conversion efficiency. At universal input

range, efficiency is recommended at 0.9; 0.93~0.95 is

recommended when input voltage is high.

4400V 0.5A

0.9 2 90

I_L,PK



 6.984A

  2 V_LINE,MIN

I_L,PK

6.984A

I_IN,MAX



 3.492A

2

I_IN,MAX

3.492A

When input voltage is set at the minimum, input current

becomes the maximum to deliver the same power compared

at high line. Maximum boost inductor current can be

detected at the minimum line voltage and at its peak.

Inductor current can be divided into two categories; one is

rising current when MOSFET is on and the other is output

diode current when MOSFET is off, as shown in Figure 10.

I_IN,MAXRMS



 2.469A

2

Figure 10. Inductor and Input Current

Because switching frequency is much higher than line

frequency, input current can be assumed to be constant

during a switching period, as shown in Figure 11.

[STEP-2] Boost Inductor Design

The boost inductor value is determined by the output power

and the minimum switching frequency. The minimum

switching frequency must be higher than the maximum

audible frequency band of 20kHz. Minimum frequency near

20kHz can decrease switching loss with the cost of

increased inductor size and line filter size. Too-high

minimum frequency may increase the switching loss and

make the system respond to noise. Selecting in the range of

about 30~60kHz is a common choice; 40~50kHz is

recommended with FL7930.

The minimum switching frequency may appear at minimum

input voltage or maximum input voltage, depending on the

output voltage level. When PFC output voltage is less than

405V, minimum switching appears at the maximum input

voltage, according to application note AN-6086. Inductance

is obtained using the minimum switching frequency:

Figure 11. Inductor and Input Current

With the estimated efficiency, Figure 10 and Figure 11

inductor current peak (I_L,PK), maximum input current

(I_IN,MAX), and input Root Mean Square (RMS) current

(I_IN,MAXRMS) are given as:

2

4  P_OUT

 



2V_LINE



I_L,PK



[ A ]

L 

[ H ]

(3)

  2 V_{LINE ,MIN}







2V_LINE

(6)



4  f_{SW ,MIN} P_OUT 1 









V_OUT



I_IN,MAX I_L,PK/ 2 [ A]

I_IN,MAXRMS I_IN,MAX

(4)

(5)

where L is boost inductance and f_SW,MINis the minimum

switching frequency.

/

2 [ A]

Rev. 1.0.0 • 3/23/11

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AN-9732

APPLICATION NOTE

The maximum on time needed to carry peak inductor

current is calculated as:

I

L,PK

t

 L 

[s]

ON,MAX

(7)

2 V

LINE,MIN

Once inductance and the maximum inductor current are

calculated, the number of turns of the boost inductor should

be determined considering the core saturation. The

minimum number of turns is given as:

Figure 13. A and A_W

e

I_L,PK L[ H ]

A_e[ mm²]  B

N_BOOST



[Turns ]

(Design Example) Since the output voltage is 400V, the

minimum frequency occurs at high-line (265V_AC) and full-

load condition. Assuming the efficiency is 90% and

selecting the minimum frequency as 50kHz, the inductor

(8)

where A_eis the cross-sectional area of core and B is the

maximum flux swing of the core in Tesla. B should be set

below the saturation flux density.

value is obtained _as:

2

  2V_LINE



Figure 12 shows the typical B-H characteristics of ferrite

core from TDK (PC45). Since the saturation flux density

(B) decreases as the temperature increases, the high

temperature characteristics should be considered.

L 







2V_LINE



4 f_SW,MINP_OUT 1







V_OUT





0.9



2 265 ²





199.4[H]

RMS inductor current (I_L,RMS) and current density of the coil

(I_L,DENSITY) can be given as:











2 265

3



45010 200 1



400 2 265



Assuming EER3019N core (PL-7, A =137mm²) is used

and setting B as 0.3T, the primary winding should be:

I_L,PK

e

I_L,RMS



[ A]

I_L,RMS

(9)

6

I_L,PK L[H ]

A_e[mm²] B

6.984  284

137 0.3

I_L,DENSITY



[ A / mm²]

N_BOOST





 34[T]

d







²

(10)

wire

 

N_wire



2



The number of turns (N_BOOST) of the boost inductor is

determined as 34 turns.

where d_WIREis the diameter of winding wire and N_WIREis

the number of strands of winding wire.

When 0.10mm diameter and 50-strand wire is used, RMS

current of inductor coil and current density are:

When selecting wire diameter and strands; current density,

window area (A_W, refer to Figure 13) of selected core, and

fill factor need to be considered. Winding sequence of the

boost inductor is relatively simple compared to a DC-DC

converter, so fill factor can be assumed about 0.2~0.3.

I_L,PK

6.984

I_L,RMS



 2.85[A]

6

I_L,RMS

2.85

0.1/ 2

I_L,DENSITY







 7.3 [A/ mm²]

²

 





²50

d

wire

 

 N_wire





2





Layers cause the skin effect and proximity effect in the coil,

so real current density may be higher than expected.

Figure 12. Typical B-H Curves of Ferrite Core

Rev. 1.0.0 • 3/23/11

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AN-9732

APPLICATION NOTE

Auxiliary winding must give enough energy to trigger ZCD

threshold to detect zero current. Minimum auxiliary winding

turns are given as:

[STEP-3] Inductor Auxiliary Winding Design

Figure 14 shows the application circuit of nearby ZCD pin

from auxiliary winding.

1.5V N_BOOST

N_AUX



[Turns]

(11)

V_OUT 2V_LINE,MAX

where 1.5V is the positive threshold of the ZCD pin.

To guarantee stable operation, auxiliary winding turns are

recommended to add 2~3 turns to the calculation result of

Equation (11). However, too many auxiliary winding turns

raise the negative clamping loss at high line and positive

clamping loss at low line.

(Design Example) 34 turns are selected as boost inductor

turns and auxiliary winding turns are calculated as:

Figure 14. Application Circuit of ZCD Pin

1.5V N_BOOST

V_OUT 2V_LINE,MAX400 2 265

1.534

N_AUX





 2.02[Turns]

The first role of ZCD winding is detecting the zero-current

point of the boost inductor. Once the boost inductor current

becomes zero, the effective capacitor shown at the

MOSFET drain pin (C_eff) and the boost inductor resonate

together. To minimize the constant turn-on time

deterioration and turn-on loss, the gate is turned on again

when the drain source voltage of the MOSFET (V_DS)

reaches the valley point shown in Figure 15. When input

voltage is lower than half of the boosted output voltage,

Zero Voltage Switching (ZVS) is possible if MOSFET turn-

on is triggered at valley point.

Choice should be around 4~5 turns after adding 2~3 turns.

[STEP-4] ZCD Circuit Design

If a transition time when V_AUXILIARYdrops from 1.4V to 0V

is ignored from Figure 15, the needed additional delay by

the external resistor and capacitor is one quarter of the

resonant period. The time constant made by ZCD resistor

and capacitor should be the same as one quarter of the

resonant period:

2 C_effL

(12)

R_ZCDC_ZCD



4

where C_effis the effective capacitor shown at the MOSFET

drain pin; C_ZCDis the external capacitance at the ZCD pin;

and R_ZCDis the external resistance at the ZCD pin.

The second role of R_ZCDis the current limit of the internal

negative clamp circuit when auxiliary voltage drops to

negative due to MOSFET turn on. ZCD voltage is clamped

0.65V and minimum R_ZCDcan be given as:













N_AUX

2V_LINE,MAX0.65V

(13)

N_BOOST

R_ZCD



[ ]

3mA

where 3mA is the clamping capability of the ZCD pin.

The calculation result of Equation (13) is normally higher

than 15k. If 20k is assumed as R_ZCD, calculated C_ZCD

from Equation (12) is around 10pF when the other

components are assumed as conventional values used in the

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Figure 15. ZCD Detection Waveforms

Rev. 1.0.0 • 3/23/11

7

AN-9732

APPLICATION NOTE

field. Because most IC pins have several pF parasitic

capacitance, C_ZCDcan be eliminated when R_ZCDis higher

than 30k. However, a small capacitor would be helpful

when auxiliary winding suffers from operating noise.

The PFC control loop has two conflicting goals: output

voltage regulation and making the input current shape the

same as input voltage. If the control loop reacts to regulate

output voltage smoothly, as shown in Figure 16, control

voltage varies widely with the input voltage variation. Input

current acts to the control loop and sinusoidal input current

shape cannot be attained. This is the reason control response

of most PFC topologies is very slow and turn-on time over

AC period is kept constant. This is also the reason output

voltage ripple is made by input and output power

relationship, not by control-loop performance.

V_IN& V_OUT

Figure 17. Inductor Current at AC Voltage Peak

V_CONTROL

I_ACIN

t

Figure 16. Input Current Deterioration by Fast Control

If on-time is controlled constantly over one AC period,

inductor current peak follows AC input voltage shape and

achieves good power factor. Off-time is basically inductor

current reset time due to the boundary mode and is

determined by the input and output voltage difference.

When input voltage is at its peak, the voltage difference

between input and output voltage is small, and long turn-off

time is necessary. When input voltage is near zero, turn-off

time is short, as shown in Figure 17 and Figure 18. Though

inductor current drops to zero, there is a minor delay,

explained above. The delay can be assumed as fixed when

AC is at line peak and zero. Near AC line peak, the inductor

current decreasing slope is slow and inductor current slope

is also slow during the ZCD delay. The amount of negative

current is not much higher than the inductor current peak.

Near the AC line zero, inductor current decreasing slope is

very high and the amount of negative current is higher than

positive inductor current peak because input voltage is

almost zero.

Figure 18. Inductor Current at AC Voltage Zero

Negative inductor current creates zero current distortion and

degrades the power factor. Improve this by extending turn-

on time at the AC line input near the zero cross.

Negative auxiliary winding voltage, when MOSFET is

turned on, is linearly proportional to the input voltage.

Sourcing current generated by the internal negative

clamping circuit is also proportional to sinusoidal input

voltage. That current is detected internally and added to the

internal sawtooth generator, as shown in Figure 19.

Rev. 1.0.0 • 3/23/11

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AN-9732

APPLICATION NOTE

With the aid of I_ZCD, an internal sawtooth generator slope is

changed and turn-on time varies as shown in Figure 22.

Figure 19. ZCD Current and Sawtooth Generator

When AC input voltage is almost zero, no negative current

is generated from inside, but sourcing current when input

voltage is high is used to raise the sawtooth generator slope

and turn-on time is shorter. As a result, turn-on time when

AC voltage is zero is longer compared to AC voltage, in

peaks shown in Figure 20.

Figure 22. Internal Sawtooth Wave Slope Variation

R_ZCDalso influences control range. Because FL7930 doesn’t

detect input voltage, voltage-mode control value is

determined by the turn-on time to deliver needed current to

boost output voltage. When input voltage increases, control

voltage decreases rapidly. For example, if input voltage

doubles, control voltage drops to one quarter. Making

control voltage maximum when input voltage is low and at

full load is necessary to use the whole control range for the

rest of the input voltage conditions. Matching maximum

turn-on time needed at low line is calculated in Equation (7)

and turn-on time adjustment by R_ZCDguarantees use of the

full control range. R_ZCDfor control range optimization is

obtained as:

Figure 20. THD Improvement

The current that comes from the ZCD pin, when auxiliary

voltage is negative, depends on R_ZCD. The second role of

R_ZCDis also related with the improving the Total Harmonic

Distortion (THD).

2 V_LINE,MIN N_AUX

0.469mA  N_BOOST

28s

t_ON,MAX1 t_ON,MAX

R_ZCD





[ ]

(14)

The third role of R_ZCDis making the maximum turn-on time

adjustment. Depending on sourcing current from the ZCD

pin, the maximum on-time varies as in Figure 21.

where:

_ON,MAXis calculated by Equation (7);

t

t_ON,MAX1is maximum on-time programming 1;

N_BOOSTis the winding turns of boost inductor; and

N_AUXis the auxiliary winding turns.

R_ZCDcalculated by Equation (13) is normally lower than the

value calculated in Equation (14). To guarantee the needed

turn on-time for the boost inductor to deliver rated power,

the R_ZCDfrom Equation (13) is normally not suitable. R_ZCD

should be higher than the result of Equation (14) when

output voltage drops as a result of low line voltage.

Figure 21. Maximum On-Time Variation vs. I_ZCD

Rev. 1.0.0 • 3/23/11

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AN-9732

APPLICATION NOTE

When input voltage is high and load is light, not much input

current is needed and control voltage of V_COMPtouches

switching stop level, such as if FL7930 is 1V. However, in

some applications, a PFC block is needed to operate

normally at light load. To compensate control range

correctly, input voltage sensing is necessary, such as with

Fairchild’s interleaved PFC controller FAN9612, or special

care on sawtooth generator is necessary. Without it,

optimizing R_ZCDis only slightly helpful for control range.

This is explained and depicted in the associated Excel^®

design tool “COMP Range” worksheet. To guarantee

enough control range at high line, clamping output voltage

lower than rated on the minimum input condition can help.

much ripple on the output voltage may cause premature

OVP during normal operation, the peak-to-peak ripple

specification should be smaller than 15% of the nominal

output voltage.

The hold-up time should also be considered when

determining the output capacitor as:

2P_OUTt_HOLD

C_OUT



[f ]

2

(16)



V_OUT0.5V_OUT,RIPPLE



²V_OUT,MIN

where t_HOLDis the required hold-up time and V_OUT,MINis the

minimum output voltage during hold-up time.

I

diode

(Design Example) Minimum R_ZCDfor clamping

capability is calculated as:













N_AUX

2V_LINE,MAX0.65V

N_BOOST

R_ZCD



3mA

5







2 2650.65V





34





18.2k

3mA

I

diode,ave

Minimum R_ZCDfor control range is calculated as:

I

=I_OUT(1-cos(4p.f_L.t))

diode,ave

2 V_LINE,MIN N_AUX

28s

t_ON,MAX1 t_ON,MAX0.469mA N_BOOST

28s 2 90 5

42s 10.9s 0.469mA 34

R_ZCD





I

OUT





 37.2k

I

OUT

V

=

OUT,ripple

2p.f_L.C_OUT

A choice close to the value calculated by the control

range is recommended. 39k is chosen in this case.

V

OUT

t

Figure 23. Output Voltage Ripple

The voltage rating of capacitor can be obtained as:

V_OV

P,MAX

V_ST,COUT



V_OUT[V ]

(17)

V_REF

[STEP-5] Output Capacitor Selection

where V_OVP,MAXand V_REFare the maximum tolerance

specifications of over-voltage protection triggering voltage

and reference voltage at error amplifier.

The output voltage ripple should be considered when

selecting the output capacitor. Figure 23 shows the line

frequency ripple on the output voltage. With a given

specification of output ripple, the condition for the output

capacitor is obtained as:

I_OUT

C_OUT



[F ]

(15)

2 f_LINE V_OUT,RIPPLE

where V_OUT,RIPPLEis the peak-to-peak output voltage ripple

specification.

The output voltage ripple caused by ESR of electrolytic

capacitor is not as serious as other power converters because

output voltage is high and load current is small. Since too

Rev. 1.0.0 • 3/23/11

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AN-9732

APPLICATION NOTE

output diode turns on; a minor voltage peak can be shown at

drain pin, which is proportional to MOSFET turn-off speed.

(Design Example) With the ripple specification of 8V_p-p,

the capacitor should be:

I_OUT

2  f_LINEV_OUT,ripple2 508

0.5

MOSFET loss can be divided into three parts: conduction

loss, turn-off loss, and discharge loss. Boundary mode

guarantees Zero Current switching (ZCS) of MOSFET

when turned on, so turn-on loss is negligible.

C_O





198.9[F]

Since minimum allowable output voltage during one cycle

line (20ms) drop-outs is 330V, the capacitor should be:

2 P_OUTt_HOLD

The MOSFET RMS current and conduction loss are

obtained as:

C_O



2



V_OUT0.5V_OUT,ripple



²V_OUT,MIN

22002010^3

4 2 V

^LINE[A]

9 V_OUT

1

6





167[F]

(19)

I_Q,RMS I_L,PK





4000.58 ²330²



To meet both conditions, the output capacitor must be larger

than 140F. A 240F capacitor is selected for the output

capacitor.

P





I_Q,RMS



² R_DS,ON[W]

(20)

Q,CON

where I_Q,RMSis the RMS value of MOSFET current,

P_Q,CONis the conduction loss caused by MOSFET current,

and R_DS,ONis the ON resistance of the MOSFET.

The voltage stress of selected capacitor is calculated as:

V_OVP

2.730

2.500

,MAX

V_ST,COUT



400 436.8[V]

V_OUT

ON resistance is described as “static ON resistance” and

varies depending on junction temperature. That variation

information is normally supplied as a graph in the datasheet

and may vary by manufacturer. When calculating

conduction loss, generally multiply three with the R_DS,ONfor

more accurate estimation.

V_REF

The precise turn-off loss calculation is difficult because of

the nonlinear characteristics of MOSFET turn off. When

piecewise linear current and voltage of MOSFET during

turn-off and inductive load are assumed, MOSFET turn-off

loss is obtained as:

1

P_Q,SWOFF



V_OUTI_Lt_OFFf_SW[W]

(21)

2

where t_OFFis the turn-off time and f_SWis the switching

frequency.

[STEP-6] MOSFET and DIODE Selection

Boundary mode PFC inductor current and switching

frequency vary at every switching moment. RMS inductor

current and average switching frequency over one AC

period can be used instead of instantaneous values.

Selecting the MOSFET and diode needs extensive

knowledge and calculation regarding loss mechanisms and

gets more complicated if proper selection of a heatsink is

added. Sometimes the loss calculation itself is based on

assumptions that may be far from reality. Refer to industry

resources regarding these topics. This note shows the

voltage rating and switching loss calculations based on the

linear approximation.

Individual loss portions are changed according to the input

voltage; maximum conduction loss appears at low line

because of high input current; and maximum switching off

loss appears at high line because of the high switching

frequency. Thus, resulting loss is always lower than the

summation of the two losses calculated above.

The voltage stress of the MOSFET is obtained as:

V_OV

P,MAX

Capacitive discharge loss made by effective capacitance

V_ST,Q



V_OUTV_DROP,DOUT[V ]

(18)

V_REF

shown at drain and source, which includes MOSFET C_OSS

,

an externally added capacitor to reduce dv/dt and parasitic

capacitors shown at drain pin, is also dissipated at

MOSFET. That loss is calculated as:

where V_DROP,DOUTis the maximum forward-voltage drop of

output diode.

After the MOSFET is turned off, the output diode turns on

and a large output electrolytic capacitor is shown at the

drain pin, thus a drain voltage clamping circuit that is

necessary on other topologies is not necessary in PFC.

During the turn-off transient, boost inductor current changes

the path from MOSFET to output diode and before the

1

P_Q,DISCHG





C_OSSC_EXTC_PAR

V²f_SW[W]

OUT



(22)

2

where:

C_OSSis the output capacitance of MOSFET;

C_EXTis an externally added capacitor at drain and source of

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11

AN-9732

APPLICATION NOTE

MOSFET; and

C_PARis the parasitic capacitance shown at drain pin.

Because the C_OSSis a function of the drain and source

voltage, it is necessary to refer to graph data showing the

relationship between C_OSSand voltage.

Estimate the total power dissipation of MOSFET as the sum

of three losses:

P_Q P_Q,CONP_Q,SWOFFP_Q,DISCHG[W ]

(23)

Diode voltage stress is the same as the output capacitor

stress calculated in Equation (17).

The average diode current and power loss are obtained as:

I_OUT

I_DOUT,AVE



[ A]

(24)

(25)



P_DOUTV_DROP,DOUTI_DOUT,AVE[W]

[STEP-8] Determine Current-Sense Resistor

where V_DROP,DOUTis the forward voltage drop of diode.

It is typical to set pulse-by-pulse current limit level a little

higher than the maximum inductor current calculated by

Equation (3). For 10% margin, the current-sensing resistor is

selected as:

(Design Example) Internal reference at the feedback pin

is 2.5V and maximum tolerance of OVP trigger voltage is

2.730V. If Fairchild’s FDP22N50N MOSFET and

FFPF08H60S diode are selected, V_D,FORis 2.1V at 8A,

25^oC, maximum R_DS,ONis 0.185 at drain current is 11A,

and maximum C_OSSis 50pF at drain-source voltage is

480V.

V_CS,LIM

R_CS



[]

(26)

I_L,PK1.1

Once resistance is calculated, its power loss at low line is

calculated as:

V_OV

^MAXV_OUTV_DROP,DIODE

P_RCS I_Q²_,RMSR_CS[W]

P,

(27)

V_ST,Q



V_REF

2.73

Power rating of the sensing resistor is recommended a twice

the power rating calculated in Equation (27).



4002.1 438.9 [V]

2.50



²



4 2 V_LINE

9 V_OUT

1

6



P

_Q,CON





I_L,PK





 R_DS,ON

(Design Example) Maximum inductor current is 4.889A

and sensing resistor is calculated as:











²



1

6

4 2 90

9 400

V_CS,LIM

0.8



 6.984







0.1853



 3.29[W]

R_CS



 0.104[]





pk

6.9841.1

I

1.1





ind

1

2

Choosing 0.1 as R_CS, power loss is calculated as:

P_RCS,LOSSI_Q²_,RMSR_CS 2.436²0.10.59[W]

Recommended power rating of sensing resistor is 1.19W.

P_Q,SWOFF



V_OUT I_Lt_OFF f_SW

1



4002.46950ns (50k /0.8) 1.54[W ]

2

1

P_Q,DISCHG





C_OSSC_EXTC_PAR

V_O²_UT f_SW



2

1

2



50p400²(50k /0.8)  0.25[W]

Diode average current and forward-voltage drop loss as:

I_OUT

0.5

0.9

I_DOUT,AVE



 0.56[ A]



P_DOUT,LOSSV_DOUT,FORI_DOUT,AVE 2.10.56 1.46[W ]

Rev. 1.0.0 • 3/23/11

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12

AN-9732

APPLICATION NOTE

increase as input voltage increases, and DC gain increases

as load decreases, high input voltage and light load is the

worst condition for feedback loop design.

[STEP-9] Design Compensation Network

The boost PFC power stage can be modeled as shown in

Figure 24. MOSFET and diode can be changed to loss-free

resistor model and then be modeled as a voltage-controlled

current source supplying RC network.

Figure 25. Control-to-Output Transfer Function for

Different Input Voltages

Figure 24. Small Signal Modeling of the Power Stage

Figure 26. Control-to-Output Transfer Function for

Different Loads

By averaging the diode current during the half line cycle,

the low-frequency behavior of the voltage controlled current

source of Figure 24 is obtained as:

Proportional and integration (PI) control with high-

frequency pole is typically used for compensation, as shown

in Figure 27. The compensation zero (f_CZ) introduces phase

boost, while the high-frequency compensation pole (f_CP)

attenuates the switching ripple.

2V

^LINE

4V_OUT

2V_LINE

L

I_DOUT,AVE K_SAW



[ A]

(28)

where:

The transfer function of the compensation network is

obtained as:

L is the boost inductance,

V_OUTis the output voltage; and

_SAWis the internal gain of sawtooth generator

(that of FL7930 is 8.49610^-6).

K

s



1

2 f_I

s

2 f_CZ

s

v_COMP



v_OUT





Then the low-frequency, small-signal, control-to-output

transfer function is obtained as:

1

2 f_CP

2.5

115mho

C_{COMP, LF}C_{COMP, HF}



f_I

f_CZ

f_CP





V

_LINE²R_L



v_OUT



v_COMP

1

V_OUT2 





 K_SAW



(30)

(29)

s

4V_OUTL

1

1

where

2 f_p



2 R_COMPC_{COMP, LF}

2

where

and R_Lis the output load resistance

f_p



1

2 R_LC_OUT















C_{COMP, LF}C_{COMP, HF}

in a given load condition.

2 R_COMP







C_{COMP, LF}C_{COMP, HF}

Figure 25 and Figure 26 show the variation of the control-

to-output transfer function for different input voltages and

different loads. Since DC gain and crossover frequency

If C_COMP,LFis much larger than C_COMP,HF, f_Iand f_CPcan be

simplified as:

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13

AN-9732

APPLICATION NOTE

The procedure to design the feedback loop is:

2.5

115mho

f_I



[Hz]

V_OUT2 C_{COMP, LF}

a. Determine the crossover frequency (f_C) around

1/10~1/5 of line frequency. Since the control-to-

output transfer function of the power stage has

-20dB/dec slope and -90^ophase at the crossover

frequency, as shown in Figure 28; it is required to

place the zero of the compensation network (f_CZ)

around the crossover frequency so 45 phase

margin is obtained. The capacitor C_COMP,LFis

determined as:

(31)

1

f_CP



[Hz]

2 R_COMPC_{COMP, HF}

G

 115mho

M

K_SAW

2V_OUT²LC_OUT



V_LINE



²2.5115mho

C_{COMP, LF}



[f ]

(34)

2



2f_C



To place the compensation zero at the crossover

frequency, the compensation resistor is obtained as:

1

R_COMP



[ ]

(35)

2 f_CC_COMP,LF

b. Place this compensator high-frequency pole (f_CP) at

least a decade higher than f_Cto ensure that it does

not interfere with the phase margin of the voltage

regulation loop at its crossover frequency. It should

also be sufficiently lower than the switching

frequency of the converter for noise to be

effectively attenuated. The capacitor C_COMP,HFis

determined as:

1

C_COMP,HF



[ ]

(36)

2 f_CPR_COMP

Figure 27. Compensation Network

The feedback resistor is chosen to scale down the output

voltage to meet the internal reference voltage:

R_FB1

V_OUT 2.5V

(32)

R_FB1 R_FB2

Typically, high R_FB1is used to reduce power consumption

and, at the same time, C_FBcan be added to raise the noise

immunity. The maximum C_FBcurrently used is several nano

farads. Adding a capacitor at the feedback loop introduces a

pole as:

1

f_FP





2 



R_FB1// R_FB2



C_FB

Figure 28. Compensation Network Design

(33)

1

[Hz]

2 R_FB2C_FB

R

R

FB2

 R

FB2

FB1

where



R

//R_FB2



FB1

R

FB1

Though R_FB1is high, pole frequency made by the

synthesized total resistance and several nano farads is

several kilo hertz and rarely affects control-loop response.

Rev. 1.0.0 • 3/23/11

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14

AN-9732

APPLICATION NOTE

[STEP-10] Line Filter Capacitor Selection

(Design Example) IfR_FB1is 11.7M, then R_FB2is:

It is typical to use small bypass capacitors across the bridge

rectifier output stage to filter the switching current ripple, as

shown in Figure 29. Since the impedance of the line filter

inductor at line frequency is negligible compared to the

impedance of the capacitors, the line frequency behavior of

the line filter stage can be modeled, as shown in Figure 29.

Even though the bypass capacitors absorb switching ripple

current, they also generate circulating capacitor current,

which leads the line voltage by 90^o, as shown in Figure 30.

The circulating current through the capacitor is added to the

load current and generates displacement between line

voltage and current.

2.5V

2.5

R_FB2



R_FB1



11.710⁶ 73.58k

V_OUT 2.5V

400 2.5

Choosing the crossover frequency (control bandwidth) at

15Hz, C_COMP,LFis obtained as:

K_SAW



V_LINE

2V_OUT² L C_OUT

8.49610^^{6 2}2.511510^6

230

2400²19910^624010^6



²2.5115 mho

C_{COMP , LF}



2



2 f_C









 950.13nF

2



2 15



Actual C_COMP,LFis determined as 1000nF since it is the

closest value among the off-the-shelf capacitors. R_COMPis

obtained as:

The displacement angle is given by:





V_LINE



²2 f_LINEC_EQ









  tan^1

(37)

1

R_COMP



11.17k





P

OUT

2 15950.110^9

2  f_CC_COMP,LF





where C_EQis the equivalent capacitance that appears across

the AC line (C_EQ=C_F1+C_F2+C_HF).

Selecting the high-frequency pole as 150Hz, C_COMP,HFis

obtained as:

The resultant displacement factor is:

1

C_COMP,HF



 95.01nF

2 15011.1710³

2  f_CP R_COMP

DF  cos

 



(38)

These components result in a control loop with a bandwidth

of 19.5Hz and phase margin of 45.6. The actual bandwidth

is a little larger than the asymptotic design.

Since the displacement factor is related to power factor, the

capacitors in the line filter stage should be selected

carefully. With a given minimum displacement factor

(DF_MIN) at full-load condition, the allowable effective input

capacitance is obtained as:

P_OUT

C_EA



tan



cos^1



DF_MN



[F]

(39)

 



V_LINE

²2 f_LINE



One way to determine if the input capacitor is too high or

PFC control routine has problems is to check Power Factor

(PF) and Total Harmonic Distortion (THD). PF is the degree

to which input energy is effectively transferred to the load

by the multiplication of displacement factor and THD that is

input current shape deterioration ratio. PFC control loop

rarely has no relation to displacement factor and input

capacitor rarely has no impact on the input current shape. If

PF is low (high is preferable), but THD is quite good (low is

preferable), it can be concluded that input capacitance is too

high and PFC controller is fine.

(Design Example) Assuming the minimum displacement

factor at full load is 0.98, the equivalent input capacitance is

obtained as:

P

OUT

C_EA



tan



cos^1



DF_MN







V_LINE



²2  f_LINE

200



tan



cos^1



0.98



 2.0453F

0.9



264



²2 50

Thus, the sum of the capacitors on the input side should be

smaller than 2.0µF.

Rev. 1.0.0 • 3/23/11

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15

AN-9732

APPLICATION NOTE



Figure 29. Equivalent Circuit of Line Filter Stage

Figure 30. Line Current Displacement

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AN-9732

APPLICATION NOTE

Appendix 1: Use of the RDY Pin for FL7930C

Typically, boosted output voltage from the PFC block is

used as input voltage to the DC-DC conversion block. For

some types of DC-DC converter, it is recommended to

trigger operation after the input voltage raised to some level.

For example, LLC resonant converter or forward

converter’s input voltage is limited to some range to

enhance performance or guarantee the stable operation.

A fast diode, such as 1N4148, is needed to prohibit the

emitter-base breakdown. Without that diode, when RDY

voltage drops to V_RDY,SATafter being pulled up, emitter

voltage maintains operating voltage for LLC controller and

almost all the voltage is applied to the emitter and base.

Breakdown current flows from emitter, base, and drain of

the MOSFET to the source of MOSFET. Because a large

electrolytic capacitor is typically used at the V_CCsupply,

that breakdown current flows high for a long time. In this

case, the internal MOSFET may be damaged since the

external small-signal bipolar junction transistor current

capability is higher than the internal RDY MOSFET.

The FL7930C provides a PFC-ready pin that can be used to

trigger other power stage when PFC output voltage reaches

the proper level.

For that purpose, the PFC RDY pin is assigned and can be

used as a acknowledge signal for the DC-DC conversion

stages. When PFC output voltage rises higher than the

internal threshold, PFC RDY output is pulled HIGH by the

external pull-up voltage and drops to zero with hysteresis.

Once circuit configuration is settled, voltage after

subtracting forward-voltage drop of the diode and voltage

drop (by the multiplication of base current and R_PULLUP

)

from the V_CCof FL7930C is available for the LLC

controller’s V_CCsource.

2.240V

V_OUT,RDYH



V_OUT[V]

2.500V

1.640V

2.500V

Another example is using RDY when the secondary side

needs PFC voltage information. When a Cold Cathode

Fluorescent Lamp (CCFL) is used for the backlight source

of an LCD TV, the inverter stage to ignite CCFL can

receive PFC output voltage directly. For that application,

Figure 32 can be a suitable circuit configuration.

(40)

V_OUT,RDYL



where V_OUT,RDYHis the V_OUTvoltage to trigger PFC RDY

output to pull HIGH and V_OUT,RDYLis the V_OUTvoltage to

trigger PFC ready output to drop to zero.

If rated V_OUTis 400V_DC, then V_OUT,RDYHis 358V_DC, and

V

_OUT,RDYLis 262V_DC.

When LLC resonant converter is assumed to connect at the

PFC output, the RDY pin can control the V_CCfor the LLC

controller, as shown in Figure 31.

Figure 32. RDY Application Circuit Using Opto-Coupler

With this application circuit, the minimum R_PULLUPis given

by Equation (42) and the maximum R_PULLUPis limited by

sufficient current to guarantee stable operation of the opto-

coupler. Assuming 1mA is the typical quantity to drive

opto-coupler, the maximum R_PULLUPis:

V_PULLUPV_OPTO,F

Figure 31. RDY Application Circuit for V_CCDriving

R_PULLUP



[ ]

(42)

1mA

R_PULLUPis chosen based on the current capability of internal

open-drain MOSFET and can be obtained as:

where V_OPTO,Ris the input forward-voltage drop of the opto-

coupler.

V_PULLUPV_RDY,SAT

R_PULLUP



[]

(41)

It may possible that a secondary microcontroller has

authority to give a trigger signal to the CCFL inverter

controller; however, after combining the microcontroller

signal and RDY signal from the primary-side, the inverter

stage is triggered only when the two signals meet the

requirements at the same time.

I_RDY,SK

where V_PULLUPis the pull-up voltage, V_RDY,SATis the

saturation voltage of the internal MOSFET, and I_RDY,SKis

the allowable sink current for the internal MOSFET.

Rev. 1.0.0 • 3/23/11

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AN-9732

APPLICATION NOTE

Appendix 2: Gate Driver Design

FL7930 directly drives the gate of the MOSFET and various

combinations of gate driver circuits are possible. Figure 33

and Figure 31 show the three circuits that are widely used.

The most difficult and uncertain task in direct gate drive is

optimizing circuit layout. Gate driving path from the OUT

pin, resistor, MOSFET gate, and MOSFET source to the

GND pin should be as short as possible to reduce parasitic

inductance; which may make MOSFET on/off speed slow

or introduce unwanted gate oscillation. Using a wider PCB

pattern for this lane reduces parasitic inductance. To damp

unwanted gate oscillation made by the capacitance at the

gate pin and parasitic inductance formed by MOSFET

internal bonding wire and PCB pattern, proper resistance

can match the impedance at the resonant frequency. To meet

EMI regulations or for the redundant system, fast gate speed

can be sacrificed by increasing serial resistance between the

gate driver and gate.

When only one resistor is used, the turn-on and turn-off

paths follow the same routine and turn-on and turn-off speed

cannot be changed simultaneously. To cover this, make

different paths by two resistors and diode if possible. Turn-

off current flows through the diode first, instead of R_ON, and

then R_ONand R_OFFshow together. Accordingly, faster turn

off is possible. However, turn-off path using internal gate

driver’s sinking path and current is limited by sinking

current capability. If a PNP transistor is added between the

gate and source of the MOSFET, the gate is shorted to

source locally without sharing the current path to the gate

driver. This makes the gate discharge to the much smaller

path than that made by the controller. The possibility of

ground bounce is reduced and power dissipation in the gate

driver is reduced. Due to new high-speed MOSFET types

such as SupreMOS^®or SuperFET^™, gate speed is getting

fast. This decreases the switching loss of the MOSFET. At

the same time, power systems suffer from the EMI

deterioration or noise problems, like gate oscillation.

Therefore, sometimes a gate discharge circuit is inevitable

to use high-speed characteristics fully.

An optimal gate driver circuit needs intensive knowledge of

MOSFET turn-on/off characteristics and consideration of

the other critical performance requirements of the system.

This is beyond the scope of this paper and many reference

papers can be found in the industry literature.

Figure 33. Equivalent Circuit of Line Filter Stage

Rev. 1.0.0 • 3/23/11

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18

AN-9732

APPLICATION NOTE

Appendix 3: Experimental Verification

To show the validity of the design procedure presented in

this application note, the converter of the design example

was built and tested. All the circuit components are exactly

as designed in the example.

Figure 34 and Figure 35 show the inductor current and input

current for 115Vac and 230Vac condition. Figure 36 shows

the startup performance for 95V_ACfull-load condition.

Figure 37 (a) and (b) show the PFC output voltage changed

under about 50V when AC input voltage was step changed

from 115V to 235V and from 235V to 115V at full load.

Figure 38 (a) and (b) shows the PFC output voltage changed

about 50V when output load was step changed from no-load

to full-load condition and from full-load to no-load at 235V.

The power factor at full load is 0.988 and 0.968 for 110V_AC

and 230V_AC, respectively.

(a) Input Voltage Change from 115V to 235V

(b) Input Voltage Change from 235V to 115V

Figure 37. Output Dynamic Response at P_O=100W

Figure 34. Inductor Current Waveforms at 115V_AC

(a) Output Load Change from 0W to 160W

Figure 35. Inductor Current Waveforms at 230V_AC

(b) Output Load Change from 160W to 0W

Figure 38. Output Dynamic Response at V_IN=235V_AC

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Figure 36. Startup Performance at 95V_AC, Full Load

Rev. 1.0.0 • 3/23/11

19

AN-9732

APPLICATION NOTE

Definition of Terms

 is the efficiency.

 is the displacement angle.

B is the maximum flux swing of the core at nominal output power in Tesla.

A_eis the cross-sectional area of core.

A_Wis the window area of core.

B_MAXis the maximum flux density of boost inductor at maximum output power in Tesla.

C_COMP,HFis the high-frequency compensation capacitance.

C_COMP,LFis the low-frequency compensation capacitance.

C

is the effective capacitance shown at the MOSFET drain pin.

_EAis the effective input capacitance to meet a given displacement factor.

_EXTis the external capacitance at drain-source to decrease the turn-off slope.

eff

C_EQis the equivalent input capacitance.

C_FBis the feedback capacitance parallel with R_FB2

.

C

_OUTis the output capacitance.

C_OSSis the output capacitance of power MOSFET.

C

_PARis the parasitic capacitance at drain-source of power MOSFET.

_ZCDis the capacitance connected at ZCD pin to improve noise immunity.

d_WIREis the diameter of boost inductor winding wire.

DF is the displacement factor between input voltage and input current.

f_Cis the crossover frequency.

f_CPis the high-frequency compensation pole to attenuate the switching ripple.

f_CZis the compensation zero.

f

_LINEis the line frequency.

f_Iis the integral gain of the compensator.

f_Pis the pole frequency in the PFC power stage transfer function.

f

_SWis the switching frequency.

f_SW,MINis the minimum switching frequency.

I

_CS,LIMis the pulse-by-pulse current limit level determined by sensing resistor.

_DOUT,AVEis the average current of output diode.

I_IN,MAXis the maximum input current from the AC outlet.

_IN,MAXRMSis the maximum RMS (Root Mean Square) input current from the AC outlet.

I

I_Lis the inductor current at the nominal output power.

I_L,PKis the maximum peak inductor current at the nominal output power.

I

_L,RMSis the RMS value of the inductor current at the nominal output power.

_L,DENSITYis the current density of the boost inductor coil.

I_OUTis the nominal output current of the boost PFC stage.

I

K

_Q,RMSis the RMS current at the power switch.

_RDY,SKis the allowable sink current for the internal MOSFET in RDY pin.

_SAWis the internal gain of sawtooth generator (that of FL7930 is 8.49610^-6).

L is the boost inductance.

_AUXis the number of turns of auxiliary winding in boost inductor.

N

N_BOOSTis the number of turns of primary winding in boost inductor.

N_WIREis the number of strands of boost inductor winding wire.

P

_DOUTis the loss of output diode.

P_OUTis the nominal output power of boost PFC stage.

P_Q,CONis conduction loss of the power MOSFET.

P

_Q,SWOFFis turn-off loss of power MOSFET.

P_Q,DISCHRGEis the drain-source capacitance discharge loss and consumed at power MOSFET.

P_Qis the total loss of power MOSFET made by P_Q,CON, P_Q,SWOFF, and P_Q,DISCHARGE

_RCSis the power loss caused by current-sense resistance.

R_COMPis the compensation resistance.

.

P

R_CSis the power MOSFET current-sense resistance.

R_DS,ONis the static drain-source on resistance of the power switch.

R_FB1is the feedback resistance between the INV pin and output voltage.

www.fairchildsemi.com

Rev. 1.0.0 • 3/23/11

20

AN-9732

APPLICATION NOTE

R_FB2is the feedback resistance between the INV pin and ground.

R_Lis the output load resistance in a given load condition.

R_PULLUPis the pull-up resistance between the RDY pin and pull-up voltage.

R_ZCDis the resistor connected at the ZCD pin to optimize THD.

t_HOLDis the required hold-up time.

t

_OFFis the inductor current reset time.

t_ON,MAXis the maximum on time fixed internally.

_ON,MAX1is the programmed maximum on time.

_COMPis compensation pin voltage.

t

V

V_CS,LIMis power MOSFET current-sense limit voltage.

V_DROP,DOUTis the forward-voltage drop of output diode.

V_IN(t) is the rectified line voltage.

V_IN,PKis the amplitude of line voltage.

V

_LINEis RMS line voltage.

V_LINE,MAXis the maximum RMS line voltage.

V_LINE,MINis the minimum RMS line voltage.

V

_LINE,OVPis the line OVP trip point in RMS.

V_OPTO,Fis the input forward voltage drop of opto-coupler.

V_OUTis the PFC output voltage.

V

_OUT,MINis the allowable minimum output voltage during the hold-up time.

V_OUT,RDYHis the V_OUTto trigger PFC RDY out pulls high.

V_OUT,RDYLis the V_OUTto trigger PFC RDY out drops to zero.

V_OUT,RIPPLEis the peak-to-peak output voltage ripple.

V

_PULLUPis the pull-up voltage for RDY pin.

V_RDY,SATis the internal saturation voltage of RDY pin.

V

_REFis the internal reference voltage for the feedback input.

_OVP,MAXis the maximum tolerance of Over-Voltage Protection specification

V_ST,COUTis the voltage stress at the output capacitor.

_ST,Qis the voltage stress at the power MOSFET.

V

Rev. 1.0.0 • 3/23/11

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21

AN-9732

APPLICATION NOTE

References

[1] Fairchild Datasheet FAN9612, Interleaved Dual BCM, PFC Controller

[2] Fairchild Datasheet FL7930 Critical Conduction Mode PFC Controller

[3] Fairchild Application Note AN-6027, Design of Power Factor Correction Circuit Using FAN7530

[4] Fairchild Application Note AN-8035, Design of Power Factor Correction Circuit Using FAN7930

[5] Fairchild Application Note AN-6086, Design Consideration for Interleaved BCM PFC using FAN9612

[6] Robert W. Erikson, Dragan Maksimovic, Fundamentals of Power Electronics, Second Edition, Kluwer Academic

Publishers, 2001.

Related Datasheets

FL7930 — Critical Conduction Mode PFC Controller

FAN9611 / FAN9612 — Interleaved Dual BCM PFC Controllers

1N/FDLL 914/A/B / 916/A/B / 4148 / 4448 Small Signal Diode

PN2222A/MMBT2222A/PZT2222A NPN General Purpose Amplifier

FDP22N50N — 600V N-Channel MOSFET, UniFET^TM

FFPF08H60S — 8A, 600V Hyperfast Rectifier

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS

PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which,

(a) are intended for surgical implant into the body, or (b)

support or sustain life, or (c) whose failure to perform when

properly used in accordance with instructions for use provided

in the labeling, can be reasonably expected to result in

significant injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

Rev. 1.0.0 • 3/23/11

www.fairchildsemi.com

22


型号：	AN-9732
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	LED Application Design Guide Using BCM Power Factor Correction (PFC) Controller for 200W Lighting System LED应用设计指南使用BCM功率因数校正（ PFC）控制器200W照明系统功率因数校正控制器
文件：	总22页 (文件大小：2690K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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