AN-994-1 [INFINEON]

MAXIMIZING THE EFFECTIVENESS OF YOUR SMD ASSEMBLIES; 最大限度地提高您的SMD集的有效性
AN-994-1
型号: AN-994-1
厂家: Infineon    Infineon
描述:

MAXIMIZING THE EFFECTIVENESS OF YOUR SMD ASSEMBLIES
最大限度地提高您的SMD集的有效性

文件: 总7页 (文件大小:121K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
AN-994-1  
Rev. 2.0  
MAXIMIZING THE  
EFFECTIVENESS OF YOUR SMD  
ASSEMBLIES  
Gil Alivio  
John Ambrus  
Tim McDonald  
Richard Dowling  
2 of 7  
IR Application Note –994 (Rev. 2)  
Thermal Resistance was measured according to  
Title: Maximizing the Effectiveness of Your SMD1  
Assemblies  
industry practice by first performing a reference  
temperature estimate; a temperature sensitive  
electrical parameter (TSEP) such as Vsd is measured  
and compared with a calibration value to determine Tj.  
Then a heating pulse of known power is applied  
followed by a second TSEP measurement. That  
measurement was compared to a calibration table to  
estimate junction temperature and calculate the  
temperature rise due to the heating pulse. From the  
familiar equation:  
Topics Covered:  
Section I: How we Measure Rth (JA)  
Section II: Thermal Characterization of  
Surface Mount Packages  
Section III: Attachment to board  
Section IV: Solder Pastes  
Section V: Heat Profiles  
Section VI: Rework  
T = RTH X PD  
And where:  
(equation 1)  
Section I: How we measure Rth (JA)  
Herein is described the device mounting and heat  
sinking used and the test methods employed to  
measure Thermal Resistance of the various packages.  
Standard printed circuit boards were developed to  
which devices were solder-mounted for measuring  
thermal resistance. FR-4 material with 2 oz. Cu was  
used. Board dimension were 4.75 inches by 4.5 inches  
and backside of board had full metal pattern. Three  
different PCB metallization patterns  
T = TJ - TRef Temperature difference (C) between  
junction temperature and reference temperature (here  
ambient, case temperature or package lead),  
RTH = Thermal Resistance (C/W) between junction and  
reference point (again ambient, case temperature or  
package lead),  
PD = Power dissipated (W)  
were tested: one with 1 sq inch of Cu area, the second  
one  
with Cu trace minimized so as to cover only as much  
area  
as taken up by the Device Under Test (DUT) and  
necessary lead mounting pads (described as “modified  
minimum pattern”), and the last one is the “absolute  
minimum” pattern with the metallized area sized only  
as needed to mount each lead. (See the figure 1.)  
We can calculate the thermal resistance by plugging in  
the measured values of temperature rise and power. In  
this way measurements were taken on representative  
samples of all packages listed in the table below.  
Dut placed in the  
middle of this pad  
Dut placed in the  
for Modified Minimum  
Pattern Area Measurements  
middle of this pad  
for Minimum Pattern  
Area Measurements  
Dut placed in the  
middle of this pad  
for 1 Square Inch  
Pattern Area Measurements  
Board size 4.5 inches by 4.75 inches  
Copper layer on the back  
Figure 1.  
1 This application note applies only to surface mountable type devices. Through-hole  
devices such as TO-220, TO-247, Fulpak, etc are excluded and not covered by this note.  
3 of 7  
Based on the Max Rth (JA) values in Table 1 please see  
in Figures 2-4 the graphs of power dissipation vs.  
ambient temperature for each type of PCB pattern.  
Note that generally the larger packages with exposed  
heat sinks (D2-Pak, D-Pak & SOT-223) have the  
highest Power Dissipation capabilities.  
Section II: Thermal Characterization of Surface  
Mount Packages  
Table 1 shows typical and Maximum Rth (JA) and typical  
R
th (JL) values of the SMD packages presently offered  
Note also that the larger the metallized PCB pattern  
area, the lower will be the thermal resistance.  
Measurements at 3 different PCB pattern Areas reflect  
this sensitivity.  
by International Rectifier. For Rth (JC) values, please  
refer to the appropriate data sheet.  
Measurements are provided for devices mounted on  
three different PCB patterns: 1 square inch (“1 sq”),  
modified minimum area, and minimum area, as  
described graphically in Figure 1.  
R (Sample Size 3 pc/package type)  
th  
Package type  
1sq"  
Modified Minimum  
Minimum  
Typ R  
*
th(JL)  
Typ R  
Typ R  
Typ R  
th(JA)  
Max R  
Max R  
Max R  
th(JA)  
th(JA)  
th(JA)  
th(JA)  
th(JA)  
342.6  
222.0  
152.1  
162.4  
163.9  
154.0  
123.1  
86.0  
230.0  
125.0  
83.0  
75.0  
70.0  
62.5  
62.5  
60.0  
58.0  
50.0  
45.0  
308.2  
175.1  
138.3  
146.3  
133.2  
145.6  
95.1  
u-3  
TSOP6 (Dual)  
TSSOP8  
169.2  
237.1  
263.6  
139.3  
35.5  
35.5  
14.7  
17.0  
17.0  
28.7  
4.9  
NA  
10.6  
NA  
2.0  
1.6  
73.4  
60.9  
47.1  
39.9  
47.3  
54.5  
27.2  
32.1  
33.5  
32.3  
20.2  
18.0  
134.7  
106.4  
112.5  
102.4  
112.0  
73.1  
170.7  
117.0  
124.9  
126.1  
118.5  
94.7  
u-6  
u-8  
TSOP6 (Single)  
SO-8 (Dual)  
SOT-223  
63.7  
49.0  
66.1  
64.0  
88.5  
Small-can DirectFET  
SO-8  
Mid-can DirectFET  
D-Pak  
49.2  
68.1  
86.2  
91.8  
66.3  
70.6  
72.3  
80.9  
55.6  
62.2  
26.3  
23.3  
54.6  
43.7  
77.3  
47.7  
42.0  
33.6  
59.5  
36.7  
D2-Pak  
Table 1: Rth typical and max values for various SMD packages  
.
NOTES:  
1. * The Rth (JL) & the Rth (JA) 1sq" were measured at the same time. Rth reference to drain lead.  
2. See Section I for details of measurement conditions.  
3. The PCB contributes greatly to the total Rth. If PCB material properties or dimensions vary significantly  
from those used by IR, actual Rth (actual) results may also vary.  
4 of 7  
Figure 2: Mod Min Power Dissipation (T_ambient)  
Power Dissipation vs. Ambient Temperature Modified  
Minimum PCB footprint  
3.50  
3.00  
2.50  
2.00  
1.50  
1.00  
0.50  
0.00  
D2-Pak **  
D-Pak **  
SOT-223  
small-can DirectFET **  
mid-can DirectFET **  
SO-8  
SO-8 (Dual)  
u-8  
TSSOP8  
TSOP6 (Single)  
u-6  
TSOP6 (Dual)  
u-3  
0
25  
50  
75  
100  
125  
150  
175  
T_ambient(°C)  
Figure 3: 1 sq" Power Dissipation (T ambient)  
Power Dissipation vs. Ambient Temperature  
D2-Pak **  
1"square Cu area on PCB  
D-Pak **  
6.00  
mid-can DirectFET **  
SO-8  
5.00  
4.00  
3.00  
2.00  
1.00  
0.00  
small-can DirectFET **  
SOT-223  
SO-8 (Dual)  
TSOP6 (Single)  
u-8  
u-6  
0
25  
50  
75 100 125 150 175  
TSSOP8  
T_ambient(°C)  
TSOP6 (Dual)  
u-3  
5 of 7  
Figure 4: Absolute Min Power Dissipation (T ambient)  
Power Dissipation vs. Ambient Temperature  
Absolute Minimum PCB footprint  
D2-Pak **  
D-Pak **  
3.00  
2.50  
2.00  
1.50  
1.00  
0.50  
0.00  
mid-can DirectFET **  
SOT-223  
small-can DirectFET **  
SO-8  
SO-8 (Dual)  
TSSOP8  
TSOP6 (Single)  
u-6  
0
25  
50  
75  
100  
125  
150  
175  
u-8  
T_ambient(°C)  
TSOP6 (Dual)  
u-3  
Section IV: Solder Pastes:  
Section III: Attachment to board:  
Most designers and technicians in the electronic industry are  
familiar with printed circuits that are provided with holes to  
support leaded components during the soldering process.  
Surface mount components on the other hand are by  
definition leadless and rely on the strength of the solder joint  
alone for mechanical as well as electrical connection. Many  
PCB assemblies require the mounting of devices on both  
sides of the board. The reflow process is typically performed  
once. Both sides of the board are pasted at the same time.  
Components are then placed on the topside only. An  
adhesive is then applied to the topside to hold the  
components in place. The board is then inverted 180  
degrees and the second side is populated with components.  
At that point the populated board is ready for the thermal  
process that will melt the solder paste and attach the  
components to the board. After the mounting process is  
complete the adhesive serves no further purpose.  
There are a wide variety of solder pastes available for  
surface mounting applications. Typical solder pastes  
are composed of a homogeneous mixture of pre  
alloyed solder powder with a specific grain size.  
Fluxes are also provided in the solder paste mixture as  
a necessary component of the surface mounting  
process.  
In today’s densely populated assemblies, pin spacing  
of SMD components has significantly been reduced.  
Pin spacing of less than 0.4mm is common which  
poses problem such as solder bridging, insufficient  
solder on the lead and device placement accuracy.  
Solder stencil thickness, dimension and registration  
accuracy, solder paste composition and particle size  
are all critical to successful soldering of these  
assemblies.  
The adhesives used must provide sufficient tenacity to  
prevent component movement during handling and soldering.  
At the same time, the adhesive should provide a bond that  
can be broken with minimal disturbance to the populated  
board in order to replace incorrect components before  
soldering. It must also be capable of maintaining adhesion  
during the preheat cycle and it should not become a deterrent  
to solder flow during the reflow or wave soldering process.  
Typical adhesives of this type are made from non-activated  
resins (R), which can be used in forming gas atmosphere to  
reduce oxides. Some are mildly activated resin (RMA), which  
can be used in normal factory environment. The activation in  
this case is used to reduce small amounts of oxidation of the  
solderable surfaces and the solder particles in the paste.  
With the advanced state of the art of fine pitch device  
technology, a simple guideline for the choice of solder  
paste is outside the scope of this document. The  
customer should seek expert guidance from the solder  
paste vendor and PCB board fabricator for detailed,  
application specific recommendations.  
6 of 7  
Section V: Heat profiles  
In addition to the over temperature considerations,  
Reflow Soldering Heat Profiles  
under temperature conditions can in turn result in a  
failure of the mechanical attachment of the device  
during the reflow profile. A carefully controlled preheat  
and post-cooling sequence is necessary. Properly  
controlling the preheat cycle will remove any volatile  
component of the solder paste such as alcohol or  
water by evaporation prior to the solder fusing cycle.  
This will reduce the chances of forming void or solder  
ball.  
A major problem associated with surface mounting of  
electronic components, especially those with  
mismatched internal expansion coefficients is the  
thermal shock of the soldering process. The advent of  
lead free assemblies has driven the requirement to  
develop and implement new handling techniques for  
surface mounting devices. Typical lead free solders  
have higher melting point temperatures than the  
traditional Pb based solders. Whereas previously,  
assemblies could be mounted at peak reflow  
temperatures in the range of 220°C to 245°C, Pb free  
assemblies require reflow temperatures in the range of  
245°C to 260°C. The higher peak reflow temperatures  
require careful control of the reflow environment to  
prevent over temperature conditions that can severely  
degrade the reliability of surface mount devices.  
Caution must be taken when choosing the reflow  
profile in order to optimize the thermal stresses that are  
applied to either Pb based or Pb free assemblies.  
This thermal conditioning can be applied in several  
ways such as using Infrared/Convection ovens, Vapor  
Phase, or Wave Solder equipments. The  
recommended thermal conditioning method is the  
Infrared/Convection Soldering Temp / Time Profile  
described below:  
Infrared/Convection Soldering Temp/Time Profile.  
The critical parameters shown below are defined in  
table 2 by solder paste type and device volume.  
Temperature  
Ramp up  
tp  
TP  
TL  
Ramp down  
tL  
TSmax  
TSmin  
ts preheat  
t 25°C to peak  
Time  
Figure 5: Soldering & Test Profile  
7 of 7  
Table 2  
Profile Feature  
Sn-Pb Eutectic Assembly  
Pb Free2 Assembly  
*Large Body  
*Large Body  
**Small Body  
**Small Body  
Ave ramp up rate  
(TL to Tp)  
3°C/Sec maximum  
3°C/Sec maximum  
Preheat  
Temp Min (Tsmin)  
Temp Max (Tsmax)  
Time (min to max) ts  
100°C  
150°C  
60 – 120 sec  
150°C  
200°C  
60 - 180 sec  
Tsmax to TL  
Ramp up rate  
-
3°C/Sec maximum  
Time maintained above:  
Temp (TL)  
Time (tL)  
183°C  
60 – 150 sec  
217°C  
60 – 150 sec  
Peak Temperature (Tp)  
225°C +0/-5°C  
10 – 30 sec  
240°C +0/-5°C  
260°C +0/-5°C3  
Time within 5°C of actual peak  
temperature (tp)  
10 – 30 sec  
10 – 30 sec  
Ramp-down rate  
6°C/sec maximum  
6 minute minimum  
6°C/sec maximum  
8 minute minimum  
Time 25°C to Peak temperature  
Section VI: Rework  
Large Body: TO-220, D2pak and larger  
(Package Thickness 2.5 mm or Package  
Volume 350 mm3  
The primary problem in replacing soldered SMDs  
on substrates is how to apply sufficient heat to  
simultaneously fuse all the connections on the  
component to be replaced without overheating the  
adjacent components on the substrate itself.  
Soldering irons with specially shaped tips are  
usually used for this purpose and because of the  
multiplicity of SMD package styles a  
corresponding variety of soldering tips is required.  
These tips also must have a gripping function so  
that when the solder is reflowed the device can be  
extracted from the board assembly.  
Small Body: Dpak, Ipak and smaller (Package  
Thickness < 2.5 mm or Package Volume <  
350 mm3))  
Table 2  
2 Devices that are lead free have the suffix “Pbf” in the  
part number. If unsure of the status of a device,  
contact the Sales Representative or the factory.  
3 The recommended peak reflow temperature for some  
large body packages (i.e. PLCC-44 / MQFP64) is  
250°C +0/-5°C. If unsure, contact the sales  
representative for details.  
When a new device is to be mounted into an SMD  
assembly, the tool must perform the reverse  
procedure. The new part must be fluxed prior to  
local reflow as described.  

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