AN-9736 [FAIRCHILD]
Design Guideline of AC-DC Converter Using FL6961, FL6300A for 70W LED Lighting; 的AC -DC转换器的设计准则采用FL6961 ， FL6300A为70W的LED照明
| 型号： | AN-9736 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Design Guideline of AC-DC Converter Using FL6961, FL6300A for 70W LED Lighting |
| 文件： | 总13页 (文件大小：465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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AN-9736
Design Guideline of AC-DC Converter Using FL6961 &
FL6300A for 70W LED Lighting
switching (ZVS) or near-ZVS (also called valley switching)
of boost switch. The QR flyback converter for the DC-DC
conversion achieves higher efficiency than the conventional
hard-switching converter with valley switching.
Summary
This application note describes a design strategy for a Power
Factor Correction (PFC) circuit and higher-power
conversion efficiency using FL6961 and FL6300A. Based
on this design guideline and several functions of each
controller for LED lighting applications, a design example
with detailed parameters demonstrates the performance.
The FL6961 provides a controlled on-time to regulate the
output DC voltage and achieves natural power factor
correction. The maximum on-time of the switch is
programmable to ensure safe operation during AC
brownouts. The FL6300A ensures
thepower system
Introduction
operates in quasi-resonant operation in wide range line
voltage and reduces switching loss to minimize switching
voltage in drain of the power MOSFET. To minimize
standby power consumption and improve light-load
efficiency, a proprietary Green-Mode provides off-time
modulation to decrease switching frequency and perform
extended valley voltage switching to keep to a minimum
switching voltage.
Figure 1 shows the typical application circuit, with the BCM
PFC converter in the front end and the Quasi-resonant (QR)
flyback converter in the back end. FL6961 and FL6300A
achieve high efficiency with relatively low cost for
75~200W applications where BCM and QR operation with
a single switch shows best performance. BCM boost PFC
converter can achieve better efficiency with lower cost than
Continuous Conduction Mode (CCM) boost PFC converter.
These benefits result from the elimination of the reverse-
recovery losses of the boost diode and zero-voltage
Figure 1. Typical Application Circuit
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/8/11
www.fairchildsemi.com
AN-9736
APPLICATION NOTE
and output capacitor CO. The inductor current IL can be
expressed as:
1. Basin Operation of BCM Boost
PFC Converter
The typical boost converter and its operational waveforms
are shown in Figure 2, Figure 3, and Figure 4.
VꢁꢉVꢅꢀtꢃ
(2)
ILꢀtꢁꢈꢈꢃ ꢄ
ꢆꢇ
The on-time of the power MOSFET Q is determined by the
output of the error amplifier that monitors the pre-regulator
output voltage. With a low-bandwidth error amplifier, the
feedback signal is almost constant during a half AC cycle,
resulting a fixed on-time of the power MOSFET at a
specific AC voltage and some certain output power level.
Therefore, the peak inductor current ILpk automatically
follows the input voltage Vg(t), achieving a natural power
factor correction mechanism. Figure 5 shows the typical
inductor current waveform during a half AC cycle.
vL (t)
D
Lb
iL (t)
Vo
vg (t)
Q
Co
Ro
Figure 2. Boost Converter
vL (t)
iL (t)
vL (t)
iL (t)
Lb
Lb
vo
vg (t)
vg (t)
Q
Ro
Co
(a) Switch Q is ON
(b) Switch Q is OFF
Figure 3. Switching Sequences of the Boost Converter
vL (t)
vg (t)
vo vg (t)
vg (t) vo vg (t)
iL (t)
Lb
Lb
Figure 5. Controlled On-Time Inductor Current Waveform
iL,avg (t)
Referring to Figure 4, considering one switching period the
average inductor current, IL,ave(t) can be calculated by the
average area of triangle waveform of inductor current:
Q
tꢁꢂ
ton
toff
ꢌ
ꢏꢎ
ꢀ ꢃꢎ
Vꢅ t
Tꢑ
(3)
ꢀ ꢃ
ꢀ ꢃ
IL,ꢊꢋꢅ t ꢄ ꢌVꢅ t ꢍ
ꢏ ꢐ
ꢀ ꢃ
· Tꢑ
VꢁꢉVꢅ t
2 · ꢆꢇ
Figure 4. One-Cycle Waveform of the Boost Converter
1.1. Operation Principle
When Q turns on, the rectifier diode D is reverse-biased and
output capacitor CO supplies load current. The rectified AC
line input voltage Vg(t) is applied to the inductor Lb so that
inductor current IL ramps up linearly and can be expressed
as:
Vꢅꢀtꢃ
(1)
ILꢀtꢁꢂꢃ ꢄ
ꢆꢇ
When Q turns off, the voltage VO-Vg(t) is applied to
inductor Lb and the polarity on the inductor Lb is reversed.
The diode D is forward-biased in this stage. The energy
stored in the inductor Lb is delivered to supply load current
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/8/11
www.fairchildsemi.com
2
AN-9736
APPLICATION NOTE
2. Operation Principle of Quasi-
Resonant Flyback Converter
QR flyback converter topology can be derived from a
conventional square wave, Pulse-Width Modulated (PWM),
flyback converter without additional components. Figure 6
and Figure 7 show the simplified circuit diagram of a quasi-
resonant flyback converter and its typical waveforms.
Figure 7. Typical Waveforms of QR Flyback Converter
Figure 6. Schematic of QR Flyback Converter
2.1. Operation Principle
3. Design Considerations
.
During the MOSFET on time (tON), input voltage
(VIN) is applied across the primary-side inductor
(Lm). MOSFET current (IDS) increases linearly
from zero to the peak value (Ipk). During this time,
the energy is drawn from the input and stored in
the inductor.
This design procedure uses the schematic in Figure 1 as a
reference. A 70W PFC application with universal input
range is selected as a design example. The design
specifications are:
.
.
.
.
.
.
Line Voltage Range: 90~277VAC (60Hz)
Output of DC-DC Converter: 24V/2.9A (70W)
PFC Output Voltage for Line Voltage: 420V
Minimum PFC Switching Frequency: > 58kHz
Minimum QR flyback Switching Frequency: > 50kHz
Overall Efficiency: 90% (PFC: 95%, QR: 95%)
.
When the MOSFET is turned off, the energy stored
in the inductor forces the rectifier diode (D) to turn
on. During the diode ON time (tD), the output
voltage (Vo) is applied across the secondary-side
inductor and the diode current (ID) decreases
linearly from the peak value to zero. At the end of
tD, all the energy stored in the inductor has been
delivered to the output. During this period, the
output voltage is reflected to the primary side as
VO NP/NS. Then, the sum of input voltage (VIN)
and the reflected output voltage (Vo NP/NS) is
imposed across the MOSFET.
3.1. PFC Section
3.1.1. Boost Inductor Design
The boost inductor value is determined by the output power
and the minimum switching frequency. The voltage-second
balance equation for the inductor is:
.
When the diode current reaches zero, the drain-to-
source voltage (VDS) begins to oscillate by the
resonance between the primary-side inductor (Lm)
and the MOSFET output capacitor (COSS) with an
amplitude of VO NP/NS on the offset of VIN, as
depicted in Figure 7. Quasi-resonant switching is
achieved by turning on the MOSFET when VDS
reaches its minimum value. This reduces the
MOSFET turn-on switching loss caused by the
capacitance loading between the drain and source
of the MOSFET.
(4)
(5)
V ꢀtꢃ · tON ꢄ ꢀVO.PFC ꢉ V ꢀtꢃꢃ · tOFF
ꢒN
ꢒN
1
1
VO.PFC ꢉ 2V
√
LꢒNE
fSW,
ꢄ
ꢄ
·
MꢒN
t
ON ꢍ tOFF tON
VO.PFC
where VIN(t) is the rectified line voltage.
LINE is RMS line voltage;
ON is the MOSFET conduction time; and
VO.PFC is the PFC output voltage.
V
t
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/8/11
www.fairchildsemi.com
3
AN-9736
APPLICATION NOTE
The MOSFET conduction time with a given line voltage at a
nominal output power is given as:
(Design Example) Since the output voltage is 420V for line
voltage, the minimum frequency occurs at high-line
(277VAC) and full-load condition. Assuming the overall
efficiency is 90% and selecting the minimum frequency as
58kHz, the inductor value is obtained as:
2 · ꢓOUꢔ · ꢆ
tON
ꢄ
(6)
ꢎ
η · VLꢒNE
where:
is the overall efficiency;
L is the boost inductance; and
POUT is the nominal output power.
ꢎ
η · VLꢒNE MAX
VO.PFC ꢉ 2V
√
LꢒNE MAX
ꢆ ꢄ
·
2 · ꢓOUꢔ · fSW. MꢒN
VO.PFC
0.9 · 277 ꢎ
420 ꢉ 2 · 277
√
Using Equation 5, the minimum switching frequency of
Equation 6 can be expressed as:
·
ꢄ 570µH
2 · 70 · 58 ꢐ 10ꢛ
420
The maximum peak inductor current at nominal output
power is calculated as:
ꢎ
η · VLꢒNE
VO.PFC ꢉ 2V
√
LꢒNE
fSW.
ꢄ
·
(7)
MꢒN
2 · ꢓOUꢔ · ꢆ
VO.PFC
2 2 · ꢓ
2 2 · 70
√
√
OUꢔ
IL.PK
ꢄ
ꢄ
ꢄ 2.44 ꢘ
As shown in Figure 5, considering one AC line voltage
cycle, the minimum switching frequency occurs at peak of
the AC line voltage. Also, the minimum switching
frequency may occur in AC maximum or minimum input
voltage, depending on the output voltage. Therefore,
calculate both the maximum and the minimum input voltage
and choose the lower inductance value. Once the output
voltage and minimum switching frequency are set, the
inductor value is given as:
η · VLꢒNE.MꢒN 0.9 ꢐ 90
2 · ꢓOUꢔ · ꢆ
2 · 70 · 570 ꢐ 10ꢜꢝ
0.9 ꢐ 90 ꢎ
MAX
tON
ꢄ
ꢄ
ꢎ
η · VLꢒNE MꢒN
ꢄ 10.9µs ꢕ 20µs
Assuming RM10 core (PC40, Ae=85mm2) is used and
setting B as 0.25T, the primary winding should be:
I
L.PK · ꢆ 2.44 · 570 ꢐ 10ꢜꢝ
ꢄ ꢄ 65.8 turns
ꢖBOOSꢔ
ꢗ
85 ꢐ 10ꢜꢝ ꢐ 0.25
ꢎ
ꢘꢙ · Δꢚ
η · VLꢒNE MAX
VO.PFC ꢉ 2V
√
LꢒNE MAX
(8)
ꢆ ꢄ
·
2 · ꢓOUꢔ · fSW. MꢒN
VO.PFC
Thus, the number of turns (NBOOST) of boost inductor is
determined as 65.
where VLINE,MAX is the maximum line voltage.
As the minimum frequency decreases, the switching loss is
reduced, while the inductor size and line filter size increase.
Thus, the minimum switching frequency should be
determined by the trade-off between efficiency and the size
of magnetic components. The minimum switching
frequency must be above 20kHz to prevent audible noise.
3.1.2. Auxiliary Winding Design
Figure 9 shows the internal block for Zero-Current
Detection (ZCD) for the PFC. FL6961 indirectly detects the
inductor zero-current instant using an auxiliary winding of
the boost inductor. The auxiliary winding should be
designed such that the voltage of the ZCD pin rises above
2.1V when the boost switch is turned off to trigger internal
comparator as:
Once the inductance value is decided, the maximum peak
inductor current at the nominal output power is obtained at
low-line condition as:
ꢖZCD
ꢀVO.PFC ꢉ 2VLꢒNE.MAXꢃ ꢞ 2.1V
√
(12)
ꢖBOOSꢔ
2 2 · ꢓ
√
OUꢔ
IL.PK
ꢄ
(9)
η · VLꢒNE.MꢒN
The ZCD pin has upper voltage clamping and lower voltage
clamping at 10V and 0.3V, respectively. When the ZCD pin
voltage is clamped at 0.3V, the maximum sourcing current
is 1.5mA and, therefore, the resistor RZCD should be
properly designed to limit the current of the ZCD pin below
1.5mA in the worst case as:
where VLINE,MIN is the minimum line voltage.
Since the maximum on time is internally limited at 25µs, it
should be smaller than 25µs, as calculated by:
2 · ꢓOUꢔ · ꢆ
MAX
tON
ꢄ
ꢕ 20µs
(10)
V
ꢖAUX
2V
ꢖAUX
√
ꢎ
ꢒN
LꢒNE.MAX
η · VLꢒNE MꢒN
(13)
RZCD
ꢞ
·
ꢄ
·
1.5mꢘ ꢖBOOSꢔ
1.5mꢘ
ꢖBOOSꢔ
The number of turns of the boost inductor should be
determined considering the core saturation. The minimum
number is given as:
I
L.PK · ꢆ
ꢖBOOSꢔ
ꢗ
(11)
ꢘꢙ · Δꢚ
where is Ae is the cross-sectional area of core and B is
the maximum flux swing of the core in Tesla. B should
be set below the saturation flux density.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/8/11
www.fairchildsemi.com
4
AN-9736
APPLICATION NOTE
3.1.3. Current-Sensing Resistor for PFC
FL6961 has pulse-by-pulse current limit function. It is
typical to set the pulse-by-current limit level at 20~30%
higher than the maximum inductor current:
0.82
RCSꢟ
ꢄ
(14)
I
L.PKꢀ1 ꢍ ꢠMAꢡGꢒNꢃ
where KMARGIN is the margin factor and 0.85V is the
pulse-by-pulse current limit threshold.
(Design Example) Choosing the margin factor as 35%, the
sensing resistor is selected as:
0.85
0.82
RCSꢟ
ꢄ
ꢄ
ꢄ 0.25Ω
IL.PKꢀ1 ꢍ ꢠMAꢡGꢒN
ꢃ
2.44ꢀ1 ꢍ 0.35ꢃ
Figure 8. Internal Block for ZCD
3.1.4. Output Capacitor Selection
For a given minimum PFC output voltage during the hold-
up time, the PFC output capacitor is obtained as:
2ꢓOUꢔ · tꢣOLD
VO.PFC ꢎ ꢉ VO.PFC.ꢣLD
ꢢO.PFC
ꢞ
(15)
ꢎ
where:
OUT is total nominal output power;
tHOLD is the required holdup time; and
VO.PFC,HLD is the allowable minimum output voltage
during the hold-up time.
P
NZCD
(VO.PFC VIN
)
NBOOST
NZCD
VIN
For PFC output capacitor, it is typical to use 0.5~1µF per
1W output power for 420V PFC output. Meanwhile, it is
reasonable to use about 1µF per 1W output power for
variable output PFC due to the larger voltage drop during
the hold-up time than 420V output.
NBOOST
(Design Example) Assuming the minimum allowable PFC
output voltage during the hold-up time is 160V, the
capacitor should be:
Figure 9. ZCD Waveforms
2ꢓOUꢔ · tꢣOLD
VO.PFC ꢎ ꢉ VO.PFC.ꢣLD
2 · 80 · 20 ꢐ 10ꢜꢛ
420 ꢎ ꢉ 350 ꢎ
(Design Example) The number of turns for the auxiliary
ZCD winding is obtained as:
ꢢO.PFC
ꢞ
ꢄ
ꢎ
ꢄ 60µꢤ
2.1ꢖBOOSꢔ
ꢖZCD
ꢞ
ꢄ 4.83 turn
ꢀVO.PFC ꢉ 2VLꢒNE.MAXꢃ
√
A 68F capacitor is selected for the output capacitor.
With a margin, NAUX is determined as 6 turns.
ZCD is selected from:
2V
3.1.5. Design Compensation Network
The feedback loop bandwidth must be lower than 20Hz for
the PFC application. If the bandwidth is higher than 20Hz,
the control loop may try to reduce the 120Hz ripple of the
output voltage and the line current is distorted, decreasing
power factor. A capacitor is connected between COMP and
GND to attenuate the line frequency ripple voltage by 40dB.
If a capacitor is connected between the output of the error
amplifier and the GND, the error amplifier works as an
integrator and the error amplifier compensation capacitor
can be calculated by:
R
ꢖAUX
2 · 277
√
6
√
LꢒNE.MAX
RZCD
ꢞ
·
ꢄ
·
ꢄ 24kΩ
1.5mꢘ
ꢖBOOSꢔ 1.5 ꢐ 10ꢜꢛ 65
as 30k.
100 · gM
25
ꢢCOMP
ꢞ
·
(16)
2π · 2fLꢒNE VO.PFC
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/8/11
www.fairchildsemi.com
5
AN-9736
APPLICATION NOTE
To improve the power factor, CCOMP must be higher than the
calculated value. However, if the value is too high, the
output voltage control loop may become slow.
(Design Example)
100 · gM
2.5
ꢢCOMP
ꢞ
·
2π · 2fLꢒNE VO.PFC
100 · 125 ꢐ 10ꢜꢝ 2.5
·
ꢄ
ꢄ 100nꢤ.
2π · 2 · 60
420
470nF is selected for better power factor.
3.2. DC-DC Section
3.2.1. Determine the Reflected Output Voltage (VRO
)
Figure 10 shows the typical operation waveforms of a quasi-
resonant flyback converter. When the MOSFET is turned
off, the input voltage (PFC output voltage), together with
the output voltage reflected to the primary (VRO), is imposed
on the MOSFET. When the MOSFET is turned on, the sum
of input voltage reflected to the secondary side and the
output voltage is applied across the diode. Thus, the
maximum nominal voltage across the MOSFET (VDS.nom
)
and diode are given as:
ꢂꢁꢥ
ꢀ ꢃ
ꢄ VO.PFC ꢍ n VO ꢍ VF ꢄ VO.PFC ꢍ VꢡO
(17)
VDS
where:
VꢡO
Figure 10.Typical Waveforms of QR Flyback Converter
(18)
n ꢄ
VO ꢍ VF
(Design Example) Assuming 650V MOSFET and 150V
Diode are used for primary side and secondary side,
respectively, with 18% voltage margin:
VO.PFC
n
V
O.PFC ꢀ
ꢃ
ꢂꢁꢥ
VD
ꢄ VO ꢍ
ꢄ VO ꢍ VO ꢍ VF
(19)
VꢡO
ꢂꢁꢥ
By increasing VRO (i.e. the turns ratio, n), the capacitive
switching loss and conduction loss of the MOSFET are
reduced. This also reduces the voltage stress of the
secondary-side rectifier diode. However, this increases the
voltage stress on the MOSFET. Therefore, VRO should be
determined by a trade-off between the voltage stresses of the
MOSFET and diode. It is typical to set VRO such that
0.82 · 650V ꢞ VDS
ꢄ VO.PFC ꢍ VꢡO
ꢦ VꢡO ꢕ 0.82 · 650 ꢉ VO.PFC ꢄ 133V
V
O.PFC ꢀ
ꢃ
VO ꢍ VF
ꢂꢁꢥ
0.82 · 150 ꢞ VDS
ꢄ VO ꢍ
VꢡO
VO.PFC
ꢂꢁꢥ
ꢀ ꢃ
VO ꢍ VF ꢄ 106V
ꢦ VꢡO ꢞ VDS
ꢄ
0.82 · 150 ꢉ VO
V
DS.nom and VD.nom are 75~85% of their voltage ratings.
V
RO is determined as 130V.
3.2.2. Transformer Design
Figure 11 shows the typical switching timing of a quasi-
resonant converter. The sum of MOSFET conduction time
(tON), diode conduction time (tD), and drain voltage falling
time (tF) is the switching period (tS). To determine the
primary-side inductance (Lm), the following parameters
should be determined first.
Minimum Switching Frequency (fS.QRmin
)
The minimum switching frequency occurs at the minimum
input voltage and full-load condition, which should be
higher than 20kHz to avoid audible noise. By increasing
fS.QRmin, the transformer size can be reduced. However, this
results in increased switching losses. Determine fS.QRmin by a
trade-off between switching losses and transformer size.
Typically fS.QRmin is set to around 50kHz.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/8/11
www.fairchildsemi.com
6
AN-9736
APPLICATION NOTE
Falling Time of the MOSFET Drain Voltage (tF)
As shown in Figure 11, the MOSFET drain voltage fall time
is half of the resonant period of the MOSFET’s effective
output capacitance and primary-side inductance. The typical
value for tF is 0.6~1.2µs.
Non-Conduction Time of the MOSFET (tOFF
)
FL6300A has a minimum non-conduction time of MOSFET
(8µs), during which turning on the MOSFET is prohibited.
To maximize the efficiency, it is necessary to turn on the
MOSFET at the first valley of MOSFET drain-to-source
voltage at heavy-load condition. Therefore, the MOSFET
non-conduction time at heavy load condition should be
larger than 8µs.
Although QR flyback is operated in PFC end for normal
operation; when Dmax is calculated to meet all input
conditions, it should take into account the minimum input
voltage of VLINE due to the start sequence between PFC and
QR flyback at startup.
After determining fS.QRmin and tF, the maximum duty cycle is
calculated as:
Figure 11.Switching Timing of QR Flyback Converter
When designing the transformer, the maximum flux density
(B) swing in normal operation as well as the maximum flux
density (Bmax) in transient should be considered. The
maximum flux density swing in normal operation is related
to the hysteresis loss in the core, while the maximum flux
density in transient is related to the core saturation.
VꢡO
ꢥꢪꢂ
ꢧꢥꢊꢨ
ꢄ
ꢩ1 ꢉ fS.Qꢡ
· tFꢫ
(20)
VLꢒNE ꢍ VꢡO
The minimum number of turns for the transformer primary
side to avoid over temperature in the core is given by:
The primary-side inductance is obtained as:
PK
ꢆꢥ · IDS
ꢥꢪꢂ
(25)
ꢖP
ꢄ
ηQꢡ · ꢀVLꢒNE · ꢧꢥꢊꢨꢃꢎ
ꢘꢙ · Δꢚ
(21)
ꢆꢥ
ꢄ
ꢥꢪꢂ
2 · fS.Qꢡ
· ꢓOUꢔ
where B is the maximum flux density swing in Tesla. If
there is no reference data, use B =0.25~0.30T.
Once Lm is determined, the maximum peak current and
RMS current of the MOSFET in normal operation are
obtained as:
Once the minimum number of turns for the primary side is
determined, calculate the proper integer for NS so that the
min
resulting NP is larger than NP
as:
V
LꢒNE · ꢧꢥꢊꢨ
PK
IDS
ꢄ
(22)
(23)
ꢥꢪꢂ
ꢆꢥ · fS.Qꢡ
ꢥꢪꢂ
(26)
ꢖP ꢄ n · ꢖS ꢞ ꢖP
ꢧꢥꢊꢨ
3
ꢡMS
PKꢬ
ꢄ IDS
The number of turns of the auxiliary winding for VDD is
given as:
IDS
VDDꢂꢁꢥ ꢍ V
The MOSFET non-conduction time at heavy load is
obtained as:
ꢖAUX
ꢄ
FA · ꢖS
(27)
ꢀ
ꢃ
VO ꢍ VF
nom
ꢀ1 ꢉ ꢧꢥꢊꢨꢃ
where VDD is the nominal VDD voltage, typically 18V,
and VFA is forward-voltage drop of VDD diode.
tOFF
ꢄ
(24)
ꢥꢪꢂ
fS.Qꢡ
Once the number of turns of the primary winding is
determined, the maximum flux density when the drain
current reaches its pulse-by-pulse current limit level should
be checked to guarantee the transformer is not saturated
during transient or fault condition.
To guarantee the first valley switching at heavy-load
condition, tOFF should be larger than 8µs.
The maximum flux density (Bmax) when drain current
reaches IDS PK is given as:
PK
ꢆꢥ · IDS
(28)
ꢚꢥꢊꢨ
ꢄ
ꢕ ꢚꢑꢊꢭ
ꢘꢙ · ꢖP
Bmax should be smaller than the saturation flux density. If
there is no reference data, use Bsat =0.35~0.40T.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/8/11
www.fairchildsemi.com
7
AN-9736
APPLICATION NOTE
(Design Example) Setting the minimum frequency is
50kHz and the falling time is 0.8µs:
VꢡO
ꢥꢪꢂ
ꢧꢥꢊꢨ
ꢄ
ꢩ1 ꢉ fS.Qꢡ
· tFꢫ
ꢜꢝꢃ
VLꢒNE ꢍ VꢡO
130
127 ꢍ 130
ꢛ
ꢀ
ꢄ
ꢆꢥ
1 ꢉ 50 ꢐ 10 · 0.8 ꢐ 10
ꢄ 0.48
ηQꢡ · ꢀVLꢒNE · ꢧꢥꢊꢨꢃꢎ
ꢄ
Figure 12. Detection Pin Section
ꢥꢪꢂ
2 · fS.Qꢡ
· ꢓOUꢔ
First, determine the ratio of the voltage divider resisters. The
ratio of the divider determines what output voltage level to
stop gate. In Figure 13, the sampling voltage VS is:
0.95 · ꢀ127 · 0.48ꢃꢎ
2 · 50 ꢐ 10ꢛ · 70
ꢄ
ꢄ 500μꢤ
127 · 0.48
500 ꢐ 10ꢜꢝ · 50 ꢐ 10ꢛ
PK
ꢖ
RA
VS ꢄ A · VO ·
ꢕ 2.5V
(29)
IDS
ꢄ
ꢄ 2.52ꢘ
ꢖS
RDEꢔ ꢍ RA
ꢀ1 ꢉ ꢧꢥꢊꢨ
ꢃ
1 ꢉ 0.48
50 ꢐ 10ꢛ
where NA is the number of turns for the auxiliary winding
and NS is the number of turns for the secondary winding.
tOFF
ꢄ
ꢄ
ꢄ 10µs
ꢥꢪꢂ
fS.Qꢡ
Assuming EER3124 (Ae=102mm2) core is used and the
flux swing is 0.29T
Figure 14 shows the internal valley detection block and the
output voltage OVP detection block of FL6300A using
auxiliary winding to detect VO. The internal timer
(minimum tOFF time) prevents the system frequency from
being too high. First valley switching is activated after
minimum tOFF time of 8μs.
PK
ꢆꢥ · IDS
ꢘꢙ · Δꢚ
500 ꢐ 10ꢜꢝ · 2.52
102 ꢐ 10ꢜꢝ · 0.29
ꢥꢪꢂ
ꢖP
ꢄ
ꢄ
ꢄ 41.8
ꢥꢪꢂ
ꢖP ꢄ n · ꢖS ꢄ 5.3 · 8 ꢄ 42.4 ꢞ ꢖP
The nominal voltage of VS is designed around 80% of the
reference voltage 2.5V; thus, the recommended value for VS
is 1.9V~2.1V. The output over-voltage protection works by
the sampling voltage after the switching-off sequence. A
4μs blanking time ignores the leakage inductance ringing. If
the DET pin OVP is triggered, the power system enters latch
mode until AC power is removed.
VDDꢂꢁꢥ ꢍ V
18 ꢍ 1.2
24.5
ꢖAUX
ꢄ
FA · ꢖS ꢄ
· 8 ꢄ 6.3
ꢀ
ꢃ
VO ꢍ VF
Assuming the pulse-by-pulse current limit for PFC output
voltage is 120% of peak drain current at heavy load:
PK
ꢆꢥ · IDS
ꢘꢙ · ꢖP
500 · 2.52 · 1.2
102 · 42
ꢚꢥꢊꢨ
ꢄ
ꢄ
ꢄ 0.34T
3.2.3. Design the Valley Detection Circuit
Figure 12 shows the DET pin circuitry. The DET pin is
connected to an auxiliary winding by RDET and RA. The
voltage divider is used for the following purposes:
.
Detect the valley voltage of the switching waveform for
valley voltage switching. This ensures QR operation,
minimizes switching losses, and reduces EMI.
.
Produce an offset to compensate the threshold voltage
of the peak current limit to provide a constant power
limit. The offset is generated in accordance with the
input voltage with the PWM signal enabled.
Figure 13.Voltage Sampled After 4µs Blanking Time
After Switch-Off Sequence
.
A voltage comparator and a 2.5V reference voltage
provide output OVP. The ratio of the divider
determines the output voltage level to stop the gate.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/8/11
www.fairchildsemi.com
8
AN-9736
APPLICATION NOTE
(Design Example) Choosing the margin factor as 35%, the
sensing resistor is selected as:
0.8
0.8
RCSꢟ
ꢄ
ꢄ
ꢄ 0.23Ω
IDSPKꢀ1 ꢍ ꢠMAꢡGꢒN
ꢃ
2.52ꢀ1 ꢍ 0.35ꢃ
3.2.5. Design the Feedback Circuit
Figure 15 is a typical feedback circuit mainly consisting of a
op-amp and a photo-coupler. RH and RL form a voltage
divider for output voltage regulation. RF and CF are adjusted
for control-loop compensation. A small-value RC filter (e.g.
RFB = 100, CFB = 1nF) placed from the FB pin to GND can
increase stability substantially. The maximum source
current of the FB pin is about 1.2mA. The phototransistor
must be capable of sinking this current to pull the FB level
down at no load. The value of the biasing resistor, RBIAS, is
determined as:
V
OP ꢉ VOPD
· ꢢTR ꢞ 1.2 ꢐ 10ꢜꢛ
(31)
RBꢒAS
where VOPD is the drop voltage of photodiode, about
1.2V; VOP is the output voltage of operational amplifier
(assuming about 2.5V); and CTR is the current transfer
rate of the opto-coupler.
Figure 14. Output Voltage Detection Block
Once the secondary-side switching current discharges to
zero, a valley signal is generated on the DET pin. It detects
the valley voltage of the switching waveform to achieve the
valley voltage switching. When the voltage of auxiliary
winding VAUX is negative (as defined in Figure 12), the DET
pin voltage is clamped to 0.3V. RDET is recommended as
150kΩ to 220kΩ to achieve valley voltage switching. After
the platform voltage VS in Figure 13 is determined, RA can
be calculated by Equation 14.
(Design Example) Setting RDET is 200kΩ and VS is around
80% of the reference voltage 2.5V:
Figure 15. Feedback Circuit
The constant voltage and current output is adapted by
measuring the actual output voltage and current with some
external passive components and op-amp in the reference
board. Because the output load, the High Bright LED (HB
LED), and some passive components effect the ambient
temperature, use the feedback path for stable operation.
ꢖ
RA
VS ꢄ A · VO ·
ꢄ 2.1V
ꢖS
RDEꢔ ꢍ RA
2.1 ꢐ RDEꢔ
RA ꢄ
ꢄ 26.4kΩ
ꢖ
ꢖS
A ꢐ VO ꢉ 2.1
3.2.4. Current-Sensing Resistor for PFC
FL6300A has pulse-by-pulse current limit function. It is
typical to set the pulse-by-current limit level at 20~30%
higher than the maximum inductor current:
0.8
RCSꢟ
ꢄ
(30)
IDSPKꢀ1 ꢍ ꢠMAꢡGꢒN
ꢃ
where KMARGIN is the margin factor and 0.8V is the cycle-
by-cycle current limit threshold.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/8/11
www.fairchildsemi.com
9
AN-9736
APPLICATION NOTE
Vo
R
1 1
VOCꢮ ꢄ Vꢑꢙꢂ_Cꢮ
ꢍ
ꢯ ꢀVꢑꢙꢂ_Cꢮ ꢉ Vꢰꢙꢈꢃ ꢍ
ꢱꢀVꢑꢙꢂ_Cꢮ ꢉ Vꢰꢙꢈꢃ dt
(32)
Do
C1
Rꢝ
ꢢꢎ Rꢝ
C2
Vsen_CC
where the Vsen_CV means the sensing output voltage from
the output stage and is divided by R4 and R8 resistor.
R1
Sensing resistor R4 and its value directly effect the CC
control block output.
R2
C1
R4
R3
Normally, the CC block is more dominate than the CV
block in steady state and the CV block acts as the Over-
Voltage Protection (OVP) at transient or abnormal mode,
such as no load condition.
VOCC
VRef
CC Control Part
C2
R7
R5
R8
The output signal of CC block is determined as:
Vsen_CV
R6
VOCV
V
V
1
V
V
VOCC ꢄ Rꢲꢀ ꢑꢙꢂ_CC ꢉ ꢰꢙꢈꢃ ꢍ ꢱꢀ ꢑꢙꢂ_CC ꢉ ꢰꢙꢈꢃ dt (33)
CV Control Part
VRef
Rꢎ
Rꢛ
ꢢꢟ
Rꢎ
Rꢛ
Figure 16. Feedback Circuit for CC/CV
Operation
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/8/11
www.fairchildsemi.com
10
AN-9736
APPLICATION NOTE
3.3. Schematic of the Evaluation Board
5
1
6
10
4
2
3
1
Figure 17. Evaluation Board Schematic
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/8/11
www.fairchildsemi.com
11
AN-9736
APPLICATION NOTE
3.4. Bill of Materials
Item No.
Part Reference
Value
Qty.
Description (Manufacturer)
1
2
3
4
U101
U102
Q101
Q102
FL6961
FL6300A
1
1
1
1
CRM PFC Controller (Fairchild Semiconductor)
QR PWM Controller (Fairchild Semiconductor)
600V/20A MOSFET (Fairchild Semiconductor)
800V/8A MOSFET (Fairchild Semiconductor)
FCPF20N60
FQPF8N80
Ultra-Fast Recovery Power Rectifier
(Fairchild Semiconductor t)
5
6
7
D201,D202
D103
FFPF20UP30DN
EGP30J
2
1
4
600V/3A Ultra-Fast Recovery Diode (Fairchild Semiconductor)
1000V/1A Ultra-Fast Recovery Diode
(Fairchild Semiconductor)
D104,D106,D107,D108
RS1M
8
D101
Q201
U202
U203
U201
ZD103
ZD201
KBL06
MMBT2222A
LM2904
FOD817
KA431S
24B 1W
15B
1
1
1
1
1
1
1
Bridge Diode (Fairchild Product)
General-Purpose Transistor (Fairchild Semiconductor)
Dual Op Amp (Fairchild Semiconductor)
Opto-Coupler (Fairchild Semiconductor)
Shunt Rregulator (Fairchild Semiconductor)
Zener Diode (Fairchild Semiconductor)
Zener Diode (Fairchild Semiconductor)
9
10
11
12
13
14
D102,D105,D203,D204,
D205
15
LL4148
5
General-Purpose Diode (Fairchild Semiconductor)
16
17
18
19
20
21
22
23
24
25
26
C101
C102
684/275V
334/275V
224/275V
472(Y)
1
1
1
2
1
3
4
3
1
1
2
X – Capacitor
X – Capacitor
C105
X – Capacitor
C103,C104
C211
Y – Capacitor
222(Y)
Y – Capacitor
C106,C114,C206
C107,C113,C116,C207
C108,C109, C210
C110
33µF/50V
104/2012
105/2102
68µF/450V
222 1kV
Electrolytic Capacitor, 105°C
SMD Capacitor 2012
SMD Capacitor 2012
Electrolytic Capacitor, 105°C
Ceramic-Capacitor
SMD Capacitor 2012
C111
C112,C117
200/2012
C201,C202,C203,C204,
C205
27
1000µF/35V
5
Electrolytic Capacitor, 105°C
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
C208,C209
C212,C213
F101
474/2012
102/3216
220V/2A
EI2820
2
2
1
1
1
2
4
1
4
3
2
2
2
3
1
2
SMD Capacitor 2012
SMD Capacitor 3216
Fuse
L101
PFC Inductor (V10P), 450µH
Stick Inductor
L201
10µH
LF101,LF102
R101,R102,R103,R104
R128
45mH
Line Filter
104/3216
393/3216
433/3216
203/3216
100/3216
4R7/3216
0R2 2W
394/3216
682/3216
153/3216
SMD Resistor 3216
SMD Resistor 3216
SMD Resistor 3216
SMD Resistor 3216
SMD Resistor 3216
SMD Resistor 3216
Metal Film Resistor 2W
SMD Resistor 3216
SMD Resistor 3216
SMD Resistor 3216
R105,R106,R107,R131
R108,R124,R127
R109,R118
R110,R119
R111,R122
R112,R113,R114
R115
R213,R214
44
R116,R117
2
Metal Oxide Film Resistor 2W
150K/2W
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/8/11
www.fairchildsemi.com
12
AN-9736
APPLICATION NOTE
Bill Of Materials (Continued)
Item No.
Part Reference
Value
Qty.
Description (Manufacturer)
45
46
47
48
49
50
51
52
53
54
R120
R123
151/3216
224/3216
430/3216
103/3216
0.1/5W
1
1
2
2
1
1
1
1
1
1
SMD Resistor 3216
SMD Resistor 3216
SMD Resistor 3216
SMD Resistor 3216
MPR Resistor 5W
SMD Resistor 2012
SMD Resistor 2012
SMD Resistor 2012
SMD Resistor 2012
SMD Resistor 2012
R125,R126
R129,R130
R201
R202
152/2012
513/2012
753/2012
392/2012
133/2012
R203
R204
R205
R206
55
56
57
58
59
60
61
62
63
R207,R209
R208
473/2012
302/2012
432/2012
153/2012
223/2012
20k
2
1
1
1
1
1
2
1
1
SMD Resistor 2012
SMD Resistor 2012
SMD Resistor 2012
SMD Resistor 2012
SMD Resistor 2012
Variable Resistor
NTC
R212
R210
R216
R211
RT1,RT2
T2
5D-9
EER3124
10D471
QR Transformer(V10P), 500µH
VARISTOR
RV1
4.0 Related Datasheets
FL6961 - Single Stage Flyback and Boundary Mode PFC Controller for Lighting –
FL6300A -Quasi-Resonant Current Mode PWM Controller for Lighting
Application Note - AN-6300 FAN6300/A/H - Highly Integrated Quasi-Resonant PWM Controller
Application Note - AN-6961- Critical Conduction Mode PFC Controller
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b)
support or sustain life, or (c) whose failure to perform when
properly used in accordance with instructions for use provided
in the labeling, can be reasonably expected to result in
significant injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/8/11
www.fairchildsemi.com
13
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