AN-9741 [FAIRCHILD]
Design Guideline for LED Lamp Control Using Primary-Side Regulated Flyback Converter, FL103M; 设计指南LED灯控制使用初级侧稳压反激式转换器， FL103M
| 型号： | AN-9741 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Design Guideline for LED Lamp Control Using Primary-Side Regulated Flyback Converter, FL103M |
| 文件： | 总12页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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AN-9741
Design Guideline for LED Lamp Control Using Primary-
Side Regulated Flyback Converter, FL103M
circuitry. This facilitates a higher efficiency power supply
design without incurring tremendous costs. Fairchild’s
Introduction
Many LED lamp systems use the flyback converter
topology. In applications where precise output current
regulation is required, current sensing in the secondary side
is always necessary, which results in additional sensing loss.
For power supply designers struggling to meet increasing
regulatory pressures, the output current sensing is a daunting
design challenge.
PWM PSR controller FL103M simplifies meeting tighter
efficiency requirements with few external components.
This application note presents design considerations for
LED lamp systems employing Fairchild Semiconductor
components. It includes designing the transformer and
output filter, selecting the components, and implementing
constantꢀcurrent control. The stepꢀbyꢀstep procedure
completes a power supply design. The design is verified
through an experimental prototype converter using FL103.
Figure 1 shows the typical application circuit for an LED
lamp using FL103M.
PrimaryꢀSide Regulation (PSR) for power supplies can be
an optimal solution for compliance and cost in LED lamp
systems. Primaryꢀside regulation controls the output voltage
and current precisely with information in the primary side of
the LED lamp controller only. This removes the output
current sensing loss and eliminates secondaryꢀfeedback
Figure 1. Typical Application Circuit
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 6/27/11
www.fairchildsemi.com
ANꢀ9741
APPLICATION NOTE
decreases linearly from the peak value to zero. At the end of
tDIS, all the energy stored in the inductor has been delivered
to the output.
Principle of Primary-Side Regulation
Figure 2 shows typical waveforms of a flyback converter.
Generally, Discontinuous Conduction Mode (DCM)
operation is preferred for primaryꢀside regulation since it
allows better output regulation. The key of primaryꢀside
regulation is how to obtain output voltage and current
information without directly sensing them. Once these
values are obtained, the control can be accomplished by the
conventional feedback compensation method.
Stage III
When the diode current reaches zero, the transformer
auxiliary winding voltage (VA) begins to oscillate by the
resonance between the primaryꢀside inductor (Lm) and the
output capacitor of MOSFET.
Design Procedure
In this section, a design procedure is presented using the
schematic in Figure 3 as a reference.
Stage III Stage I
Stage I
IPK
VO
Constant Voltage
Operation
N
VO
A
IDS
Constant Current
Operation
fS = 50kHz
fS = 33kHz
N
P
×
N
N
S
0.5*VO
B
C
IO = IF_AVG
UVLO
Protection
IO
IF
O
N
IO
N A
VF
×
Figure 3. CV and CC Operation Area
N S
[STEP-1] Estimate the Efficiencies
Figure 3 shows the Constant Voltage (CV) and Constant
Current (CC) operation area. To optimize the power stage
design, the efficiencies and input powers should be
specified for operating point A (nominal output voltage
and current), B (50% of nominal output voltage), and C
(minimum output voltage).
VA
tON
1. Estimated overall efficiency (η) for operating points
A, B, and C: The overall power conversion efficiency
should be estimated to calculate the input power. If
no reference data is available, set η = 0.7 ~ 0.75 for
lowꢀvoltage output applications and η = 0.8 ~ 0.85
for highꢀvoltage output applications.
Figure 2. Key Waveforms of PSR Flyback Converter
The operation principles of DCM flyback converter are:
Stage I
2. Estimated primaryꢀside efficiency (ηP) and
secondaryꢀside efficiency (ηS) for operating points A,
B, and C. Figure 4 shows the definition of primaryꢀ
side and secondaryꢀside efficiencies, where the
primaryꢀside efficiency is for the power transfer from
AC line input to the transformer primary side, while
the secondaryꢀside efficiency is for the power transfer
from the transformer primary side to the power
supply output.
During the MOSFET on time (tON), input voltage (VDL) is
applied across the primaryꢀside inductor (Lm). Then
MOSFET current (IDS) increases linearly from zero to the
peak value (IPK). During this time, the energy is drawn from
the input and stored in the inductor.
Stage II
When the MOSFET is turned off, the energy stored in the
inductor forces the rectifier diode (DF) to turn on. During
the diode conduction time (tDIS), the output voltage (VO),
together with diode forwardꢀvoltage drop (VF), are applied
across the secondaryꢀside inductor and the diode current (IF)
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 6/27/11
www.fairchildsemi.com
2
ANꢀ9741
APPLICATION NOTE
The typical values for the primaryꢀside and secondaryꢀside
efficiencies are given as:
The secondaryꢀside efficiency at 50% of nominal output
voltage (operating point B) can be approximated as:
N
N
1
η 3
2
η 3
2
0.5×VO
VO +VF
(1)
(2)
ηS @ B
≅
ηS
×
×
(6)
ηP
ηP
≅
≅
,ηS
≅
≅
η
η
3 ;VO <10V
1
3 ;VO >10V
N
N
0.5×VO +VF
VO
Then, the power supply input power and transformer input
power at 50% nominal output voltage (operating point B)
are given as:
,ηS
N
0.5×VO N × IO
P
=
(7)
(8)
IN @ B
η@ B
0.5×VO N × IO
N
P
=
IN _T @ B
ηS @ B
The overall efficiency at the minimum output voltage
(operating point C) can be approximated as:
min
N
VO
VO +VF
η@C
≅
η
×
×
(9)
min
N
VO +VF
VO
Figure 4. Primary- and Secondary-Side Efficiency
where, Vomin is the minimum output voltage.
With the estimated overall efficiency, the input power at
nominal output is given as:
The secondaryꢀside efficiency at minimum output voltage
(operating point C) can be approximated as:
N
VO N × IO
min
N
VO
VOmin +VF
VO +VF
(3)
P =
IN
η@C
≅
ηS
×
×
(10)
η
N
VO
N
N
where VO and IO are the nominal output voltage and
current, respectively.
Then, the power supply input power and transformer input
power at the minimum output voltage (operating point C)
are given as:
The input power of the transformer at nominal output is
given as:
N
VOmin × IO
N
VO N × IO
P
=
(11)
(12)
IN @C
P
=
(4)
η@C
IN _T
ηS
VOmin × IO
N
When the output voltage drops below 50% of its nominal
value, the frequency is reduced to 33kHz to prevent CCM
operation. Thus, the transformer should be designed for
DCM both at 50% of nominal output voltage and minimum
output voltage.
P
=
IN _T @B
ηS @C
[STEP-2] Determine the DC Link Capacitor
(CDL) and the DC Link Voltage Range
As output voltage reduces in CC Mode, the efficiency also
drops. To optimize the transformer design, it is necessary to
estimate the efficiencies properly at 50% of nominal output
voltage and minimum output voltage conditions.
It is typical to select the DC link capacitor as 2ꢀ3ꢁF per watt
of input power for universal input range (90 ~ 265VRMS) and
1ꢁF per watt of input power for European input range (195
~ 265VRMS). With the DC link capacitor chosen, the
minimum DC link voltage is obtained as:
The overall efficiency at 50% of nominal output voltage
(operating point B) can be approximated as:
N
N
0.5×VO
VO +VF
P (1− Dch )
CDL × fL
min
min
VDL = 2×(VLINE )2 −
IN
η@ B
≅
η
×
×
(5)
(13)
N
N
0.5×VO +VF
VO
min
where VF is diode forwardꢀvoltage drop.
where VLINE is the minimum line voltage, CDL is the
DC link capacitor, fL is the line frequency, and Dch is the
DC link capacitor charging duty ratio defined as shown in
Figure 5 (typically about 0.2).
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 6/27/11
www.fairchildsemi.com
3
ANꢀ9741
APPLICATION NOTE
voltage should be also considered. The maximum voltage
stress of MOSFET is given as:
max
VDS =VDLmax +VRO +VOS
(20)
T1
T2
Dch
=
For reasonable snubber design, voltage overshoot (VOS) is
typically 1~1.5 times the reflected output voltage. It is also
typical to have a margin of 15~20% of breakdown voltage
for maximum MOSFET voltage stress.
Figure 5. DC Link Voltage Waveforms
The maximum DC link voltage is given as:
max
max
(14)
VDL = 2 ×VLINE
where VLINEmax is the maximum line voltage.
NP
(VO + VF ) ×
NS
The minimum input DC link voltage at 50% nominal output
voltage is given as:
P
@B (1− Dch )
CDL × fL
IN
min
min
VDL@ B = 2×(VLINE )2 −
(15)
The minimum input DC link voltage at minimum output
voltage are given as:
Figure 6. Voltage Stress of MOSFET
The transformer turns ratio between the auxiliary winding
and secondary winding (NA/NS) should be determined by
considering the permissible IC supply voltage (VDD) range
and minimum output voltage in constant current. When the
LED operates in constant current, VDD is changed, together
with the output voltage, as seen Figure 7. The overshoot of
auxiliary winding voltage caused by the leakage inductance
also affects the VDD. At lightꢀload condition, where the
overshoot of auxiliary winding voltage is negligible, VDD
voltage is given as:
P
@C (1− Dch )
CDL × fL
IN
min
min
VDL@C = 2×(VLINE )2 −
(16)
[STEP-3] Determine Transformer Turns Ratio
Figure 6 shows the MOSFET drainꢀtoꢀsource voltage
waveforms. When the MOSFET is turned off, the sum of
the input voltage (VDL) and the output voltage reflected to
the primary is imposed across the MOSFET as:
NA
min1
nom
max
VDD
=
×
(
VO +VF −VFA
)
(21)
(17)
VDS = VDL +VRO
NS
The actual VDD voltage at heavy load is higher than
Equation (21) due to the overshoot by the leakage
inductance, which is proportional to the voltage overshoot
of MOSFET drainꢀtoꢀsource voltage shown in Figure 7.
Considering the effect of voltage overshoot, the VDD
voltages for nominal output voltage and minimum output
voltage are given as:
where VRO is reflected output voltage defined as:
NS
VRO
=
×
(VO +VF
)
(18)
NP
where VF is the diode forward voltage drop and NP and NS
are number of turns for the primary side and secondary
side, respectively.
NA
NS
NS
NP
max
When the MOSFET is turned on; the output voltage,
together with input voltage reflected to the secondary, are
imposed across the diode as:
VDD
VDD
≅
× VO +VF +
×VOS −VFA
(22)
(23)
NA
NS
NS
NP
min 2
min
≅
× VO +VF +
×VOS −VFA
NS
max
VF =VO +
×VDL
(19)
NP
where VFA is the diode forwardꢀvoltage drop of auxiliary
winding diode.
As observed in Equations (5) and (6), increasing the
transformer turns ratio (NP/NS) results in increased voltage
of MOSFET, while it leads to reduced voltage stress of
rectifier diode. Therefore, the transformer turns ratio
(NP/NS) should be determined by the compromise between
MOSFET and diode voltage stresses. When determining the
transformer turns ratio, the voltage overshoot (VOS) on drain
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 6/27/11
www.fairchildsemi.com
4
ANꢀ9741
APPLICATION NOTE
Transformer primaryꢀside inductance can be calculated as:
(VDL@B min ×tON @ B )2 × fS
(26)
Lm =
2× P
IN _T @ B
The maximum peakꢀdrain current can be obtained at the
nominal output condition as:
2× P
PK
IN _T
IDS
=
(27)
Lm × fS
The MOSFET conduction time at the nominal output
condition is obtained as:
Lm
PK
tON = IDS
×
(28)
min
VDL
The minimum number of turns for the transformer primary
side to avoid the core saturation is given by:
Figure 7. VDD and Winding Voltage
PK
Lm × IDS
min
NP
=
(29)
[STEP-4] Design the Transformer
Bsat × Ae
where Ae is the crossꢀsectional area of the core in m2 and
sat is the saturation flux density in Tesla.
Figure 8 shows the definition of MOSFET conduction time
(tON), diode conduction time (tDIS), and nonꢀconduction time
(tOFF). The sum of MOSFET conduction time and diode
conduction time at 50% of nominal output voltage is
obtained as:
B
Figure 9 shows the typical characteristics of ferrite core
from TDK (PC40). Since the saturation flux density (Bsat)
decreases as the temperature rises, the highꢀtemperature
characteristics should be considered for a charger in an
enclosed case. If there is no reference data, use
min
VDL@ B
NS
tON @ B + tDIS @ B = t
1+
×
(24)
ON @ B
NP 0.5×VO +VF
B
sat =0.25~0.3T.
The first step in transformer design is to determine how much
nonꢀconduction time (tOFF) is allowed in DCM operation.
Once the turns ratio is obtained, determine the proper
integer for NS so that the resulting NP is larger than NP
min
obtained from Equation (29).
Once the tOFF is determined, by considering the frequency
variation caused by frequency hopping and its own
tolerance, the MOSFET conduction time is obtained as:
1
− tOFF @ B
fS
tON @ B
=
(25)
min
VDL@ B
NS
1+
×
NP 0.5×VO +VF
IDS
tON
IF
t
tOFF
tDIS
tS
Figure 8. Definition of tON, tDIS, and tOFF
Figure 9. Typical B-H Curves of Ferrite Core (TDK/PC40)
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 6/27/11
www.fairchildsemi.com
5
ANꢀ9741
APPLICATION NOTE
DCM operation at minimum output voltage should be also
checked. The MOSFET conduction time at minimum output
voltage is given as:
[STEP-6] Output Voltage and Current Setting
The nominal output current is determined by the sensing
resistor value and transformer turns ratio as:
2
× PIN _T @C × Lm
1
NP
tON @C
=
×
(30)
RSense
=
min
(36)
NS × IO N ×8.5
fSR
VDL@C
where fSR is the reduced switching frequency to prevent
CCM operation.
The voltage divider R1 and R2 should be determined such
that VS is 2.5V at the end of diode current conduction time,
as shown in Figure 8.
Then, the nonꢀconduction time at minimum output voltage
is given as:
N
R1 VO
NA
=
×
−1
(37)
min
VDL@C
1
NP
NS
R2 Vref NS
tOFF @C
=
−tON @C (1+
×
)
(31)
min
fSR
VO +VF
Select 1% tolerance resistor for better output regulation.
It is recommended to place a bypass capacitor of 22~68pF
closely between the VS pin and the GND pin to bypass the
switching noise and keep the accuracy of the sampled
voltage for CV regulation. The value of the capacitor affects
the load regulation and constantꢀcurrent regulation. Figure
10 illustrates the measured waveform on the VS pin with a
different VS capacitor. If a higherꢀvalue VS capacitor is
used, the charging time becomes longer and the sampled
voltage is higher than the actual value.
The nonꢀconduction time should be larger than 3ꢁs (10% of
the switching period), considering the tolerance of the
switching frequency.
[STEP-5] Calculate the Voltage and Current of
the Switching Devices
Primary-Side MOSFET
The voltage stress of the MOSFET was discussed when
determining the turns ratio in STEPꢀ3. Assuming that drainꢀ
voltage overshoot is the same as the reflected output
voltage, maximum drain voltage is given as:
max
VDS =VDLmax +VRO +VOS
(32)
The RMS current though the MOSFET is given as:
tON × fS
rms
PK
(33)
IDS = IDS
×
3
Secondary-Side diode
The maximum reverse voltage and the RMS current of the
rectifier diode are obtained, respectively, as:
NS
N
max
VF =VO
+
×VDL
(34)
(35)
NP
Figure 10.Sampling Voltage with Different VS Capacitors
min
VDL
NP
NS
FL103 is able to control brownout voltage by VS resistors.
When the current through VS (IVS) is typically 175ꢁA, the
FL103 triggers brownout protection. At that time, VS is
1.13V. The brownout voltage is obtained, respectively, as:
rms
rms
IF = IDS
×
×
VRO
N
A
VA =VDL × −
(38)
NP
VS VS −VA
IVS
=
+
(39)
R2
R1
When input voltage is low line & output load is heavy, IVS
should be larger than 227ꢁA.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 6/27/11
www.fairchildsemi.com
6
ANꢀ9741
APPLICATION NOTE
voltage does not change significantly during one switching
cycle. The snubber capacitor should be ceramic or a
material that offers low ESR. Electrolytic or tantalum
capacitors are unacceptable for these reasons.
[STEP-7] Determine the Output Filter Stage
The peak to peak ripple of capacitor current is given as:
NP
PK
ꢀICO
=
× IDS
(40)
The snubber capacitor voltage at fullꢀload condition (VSN) is
given as:
NS
The voltage ripple on the output is given by:
VSN = VRO +VOS
(42)
N
2
ꢀICO ×tDIS
2×CO
ꢀICO − IO
ꢀICO
(41)
ꢀVO =
×
+ ꢀICO × RC
The power dissipated in the snubber network is obtained as:
2
VSN
VSN
1
2
PK
Sometimes it is impossible to meet the ripple specification
with a single output capacitor (CO) due to the high ESR (RC)
of the electrolytic capacitor. Additional LC filter stages
(post filter) can be used. When using post filters, do not to
place the corner frequency too low as this may make the
system unstable or limit the control bandwidth. It is typical
to set the corner frequency of the post filter at around 1/10 ~
1/5 of the switching frequency.
P
=
=
× Llk ×(IDS )2 ×
× fS
(43)
SN
RSN
VSN −VOS
PK
where IDS is peakꢀdrain current at full load, Llk is the
leakage inductance, VSN is the snubber capacitor voltage
at full load, and RSN is the snubber resistor.
The leakage inductance is measured at the switching
frequency on the primary winding with all other windings
shorted. Then, the snubber resistor with proper rated
wattage should be chosen based on the power loss. The
maximum ripple of the snubber capacitor voltage is
obtained as:
[STEP-8] Design the RCD Snubber in the
Primary Side
When the power MOSFET is turned off, there is a highꢀ
voltage spike on the drain due to the transformer leakage
inductance. This excessive voltage on the MOSFET may
lead to an avalanche breakdown and, eventually, failure of
the device. Therefore, it is necessary to use an additional
network to clamp the voltage. The RCD snubber circuit and
MOSFET drainꢀvoltage waveform are shown in Figure 6.
The RCD snubber network absorbs the current in the
leakage inductance by turning on the snubber diode (DSN)
once the MOSFET drain voltage exceeds the voltage of
cathode of DSN. In the analysis of snubber network, it is
assumed that the snubber capacitor is large enough that its
VSN
ꢀVSN
=
(44)
CSN × RSN × fS
In general, 5~20% ripple of the selected capacitor voltage is
reasonable.
In the snubber design in this section, neither the lossy
discharge of the inductor nor stray capacitance is
considered. In the actual converter, the loss in the snubber
network is less than the designed value due to this effect.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 6/27/11
www.fairchildsemi.com
7
ANꢀ9741
APPLICATION NOTE
Design Example Using FL103M
Table 1. Cable Compensation
Application
Device
Input
Output
8.4W (24V/0.36A)
LED Bulb
FL103M
85VAC ~ 265VAC (50Hz/60Hz)
Description
Symbol
Value
Unit
System Specifications
min
Minimum Line Input Voltage
Maximum Line Input Voltage
Line Frequency
VLINE
85
265
60
VAC
VAC
Hz
V
max
VLINE
fL
N
Setting Output Voltage
Output Voltage at Point B
Minimum Output Voltage
Normal Output Current
Second Diode Voltage Drop
Normal Switching Frequency
VO
24
VO@B
12
V
Input
min
VO
10
V
N
IO
0.35
1.1
50
A
VF
fS
V
kHz
kHz
Switching Frequency between Point B and Point C
Estimated Efficiency
fSR
33
Input
Efficiency
η
0.80
0.93
10.50
9.05
0.77
0.89
5.48
4.72
0.75
0.87
4.64
4.00
SecondaryꢀSide Efficiency
Input Power
ηS
PIN
Input Power of Transformer
Overall Efficiency at Point B
SecondaryꢀSide Efficiency at Point B
Input Power at Point B
PIN_T
η@B
ηS@B
PIN@B
PIN_T@B
η@C
W
Output
Input Power of Transformer at Point B
Overall Efficiency at Point C
Secondary Side Efficiency at Point C
Input Power at Point C
ηS@C
PIN@C
PIN_T@C
Input Power of Transformer at Point C
Determine DC Link Capacitor & DC Link Voltage Range
Input
DC Link Capacitor
CDL
20
86
ꢁF
V
min
Minimum DC Link Voltage
VDL
max
Maximum DC Link Voltage
Minimum DC Link Voltage at Point B
Minimum DC Link Voltage at Point C
VDL
375
104
107
Output
min
VDL@B
min
VDL@C
Determine the Transformer Turn Ratio
Maximum VDD
max
VDD
24.0
8.0
V
min
Minimum VDD
VDD
ripple
VDD Ripple in Burst Mode
Input
VDD
3.8
VPꢀP
V
VDD Diode Drop Voltage
VFA
0.7
Determine NP/NS Ratio
Determine NA/NS Ratio
NP/NS
NA/Ns
3.20
0.68
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 6/27/11
www.fairchildsemi.com
8
ANꢀ9741
APPLICATION NOTE
Description
Symbol
Value
Unit
Maximum Rectifier Output Voltage
NA/NS Ratio 1
VRO
80
V
1
NA/NS
0.50
0.24
0.49
Output
2
NA/NS Ratio 2
NA/NS
3
NA/NS Ratio 3
NA/NS
Transformer Design
NonꢀConduction Time at Point B
tOFF@B
Ae
4.00
31.0
0.30
23
us
mm2
T
Transformer Core CrossꢀSectional Area
Maximum Flux Density
Input
Bsat
Determine Secondary Side Turns
MOSFET Conduction Time at Point A
Inductor Discharge Time at Point A
NonꢀConduction Time at Point A
MOSFET Conduction Time at Point B
Inductor Discharge Time at Point B
MOSFET Conduction Time at Point C
Inductor Discharge Time at Point C
NonꢀConduction Time at Point C
Transformer PrimaryꢀSide Inductance
Peak Drain Current
NS
Turns
us
tON
7.66
8.24
4.10
4.60
11.40
5.08
15.25
9.98
1.21
0.55
71.13
74
tDIS
us
tOFF
us
tON@B
tDIS@B
tON@C
tDIS@C
tOFF@C
Lm
us
us
us
us
Output
us
mH
A
PK
IDS
min
Minimum PrimaryꢀSide Turns
PrimaryꢀSide Turns
Np
Turns
Turns
Turns
Np
NA
Auxiliary Winding Turns
16
Final NP/NS Ratio
NP/NS
NA/Ns
3.22
0.70
Final NA/NS Ratio
Selection Switching Device
Input
MOSFET Overshoot Voltage
MOSFET Maximum DrainꢀSource Voltage
MOSFET RMS Current
VOS
40
V
V
A
V
A
max
VDS
495
0.20
140
0.65
rms
IDS
Output
Maximum Second Diode Voltage
Second Diode RMS Current
VF
rms
IF
Setting Output Voltage and Current
Determine VS HighꢀSide Resistor
R1
R2
91
16
Kꢂ
Kꢂ
ꢂ
Determine VS LowꢀSide Resistor
Determine CurrentꢀSensing Resistor 1
Determine CurrentꢀSensing Resistor 2
Calculate VS HighꢀSide Resistor
Auxiliary Voltage at Low Line
Input
Rsense1
Rsense2
R1cal
2.4
2.2
ꢂ
90.85
ꢀ27.52
379.59
38.83
1.08
Kꢂ
V
1
VA
low
Output
Auxiliary Current at 90VAC
IVS
uA
V
BO
DC Link Voltage at Brownout
VDL
Calculate CurrentꢀSensing Resistor
Rsense
ꢂ
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 6/27/11
www.fairchildsemi.com
9
ANꢀ9741
APPLICATION NOTE
Design Summary Using FL103M
Figure 11.Schematic for LED Bulb
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 6/27/11
www.fairchildsemi.com
10
ANꢀ9741
APPLICATION NOTE
Transformer for LED Bulb
Core: EFD-20 (Material: PC-40)
Bobbin: 10-Pin
3mm
3mm
Tape 3T
1
Na
2
5
Tape 3T
Tape 3T
Np2
Ns
3
9
10
Tape 3T
3
4
Np1
Primary
Secondary
Figure 12.Transformer Specifications and Construction
Table 2. Winding Specifications
No.
Winding
Pin (S ꢀ F)
4 ꢀ 3
Wire
Turns
Winding Method
1
2
3
4
5
6
7
8
Np1
0.20 Φ * 1
62
Solenoid Winding
Insulation: Polyester Tape t = 0.05mm, 3 Layers
0.32 Φ (TEX) * 1 23
Insulation: Polyester Tape t = 0.05mm, 3 Layers
0.20 Φ * 1 12
Insulation: Polyester Tape t = 0.05mm, 3 Layers
0.20 Φ * 1 16
Ns
Np2
Na
10 ꢀ 9
3 ꢀ 5
2 ꢀ 1
Solenoid Winding
Center Solenoid Winding
Center Solenoid Winding
Outer Insulation: Polyester Tape t = 0.05mm, 3 Layers
Table 3. Electrical Characteristics
Pin
Specification
1.2mH ±7%
Remark
1kHz, 1V
Inductance
Leakage
4 ꢀ 5
4 ꢀ 5
Maximum 20ꢁH
Short all output pins
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 6/27/11
www.fairchildsemi.com
11
ANꢀ9741
APPLICATION NOTE
Related Datasheets
FL103 — Primary-Side Regulation PWM Controller Datasheet
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