AN-9738_技术文档

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AN-9738

Design Guideline on 150W Power Supply for LED

Street Lighting Design Using FL7930B and FAN7621S

Introduction

This application note describes a 150W rating design

guideline for LED street lighting. The application design

consists of CRM PFC and LLC SRC with high power factor

and high power conversion efficiency using FL7930B and

FAN7621S. To verify the validity of the application board

and scheme, a demonstration board 150W (103V/1.46A)

ACꢀDC converter was implemented and its results are

presented in this application note. In CRM active PFC, the

most popular topology is a boost converter. This is because

boost converters can have continuous input current that can

be manipulated with peak current mode control techniques

to force peak current to track changes in line voltage. The

FAN7930B is an active Power Factor Correction (PFC)

controller for boost PFC applications that operate in critical

conduction mode (CRM). Since it was first introduced in

early 1990s, LLCꢀSRC (series resonant converter) has

became a most popular topology because of its outstanding

performance in areas such as the output regulation of

switching frequency, ZVS capability for entire load range,

low turnꢀoff current, small resonant components using the

integrated transformer, zero current switching (ZCS), and no

reverse recovery loss on secondary rectifier. Figure 1 shows

the typical application circuit, with the CRM PFC converter

in the front end and the LLC SRC DCꢀDC converter in the

back end. FL7930B and FAN7621S achieve high efficiency

with medium power for 150W rating applications where

CRM and LLC SRC operation with a twoꢀstage shows best

performance. CRM boost PFC converters can achieve better

efficiency with light and medium power rating than

Continuous Conduction Mode (CCM) boost PFC

converters. These benefits result from the elimination of the

reverseꢀrecovery losses of the boost diode and ZeroꢀCurrent

Switching (ZCS). The LLC SRC DCꢀDC converter achieves

higher efficiency than the conventional hard switching

converter. The FL7930B provides a controlled onꢀtime to

regulate the output DC voltage and achieves natural power

factor correction. The FAN7621S includes a highꢀside gate

driver circuit, accurate currentꢀcontrolled oscillator,

frequency ꢀlimit circuit, softꢀstart, and builtꢀin protections.

The highꢀside gate drive circuit has a commonꢀmode noise

cancellation capability, which guarantees stable operation

with excellent noise immunity. Using Zero Voltage

Switching (ZVS) dramatically reduces switching losses and

significantly improves efficiency. ZVS also reduces

switching noise noticeably, which allows a smallꢀsized

Electromagnetic Interference (EMI) filter.

Figure 1. Typical Application Circuit

Rev. 1.0.0 • 4/20/11

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ANꢀ9738

APPLICATION NOTE

1. Basic Operation of BCM PFC Pre-Regulator

The most widely used operation modes for the boost

converter are Continuous Conduction Mode (CCM) and

Boundary Conduction Mode (BCM). These two descriptive

names refer to the current flowing through the energy

storage inductor of the boost converter, as depicted in

Figure 2. As the names indicate, the inductor current in

CCM is continuous; while in BCM, the new switching

period is initiated when the inductor current returns to zero,

which is at the boundary of continuous conduction and

discontinuous conduction operations. Even though the BCM

operation has higher RMS current in the inductor and

switching devices, it allows better switching condition for

the MOSFET and the diode. As shown in Figure 2, the

diode reverse recovery is eliminated and a fastꢀrecovery

diode is not needed. The MOSFET is also turned on with

zero current, which reduces the switching loss.

A side effect of BCM is that the boost converter runs with

variable switching frequency that depends primarily on the

selected output voltage, the instantaneous value of the input

voltage, the boost inductor value, and the output power

delivered to the load. The operating frequency changes as

the input current follows the sinusoidal input voltage

waveform, as shown in Figure 3. The lowest frequency

occurs at the peak of sinusoidal line voltage.

I_D

I_L

L

V_OUT

V_LINE

I_DS

V_IN

Line Filter

Figure 3. Operation Waveforms of BCM PFC

The voltageꢀsecond balance equation for the inductor is:

(1)

V_IN(t )⋅t_ON

=

(

V_OUT−V_IN(t ) ⋅t_OFF

)

where V_IN(t)is the rectified line voltage and V_OUTis the

output voltage.

The switching frequency of BCM boost PFC converter is:

1

V_OUT−V_IN(t )

f_SW

=

⋅

t_ON+ t_OFFt_ON

V_OUT

(2)

V_OUT−V_{IN ,PK}⋅ sin

(2

π ⋅ f_LINE⋅t

)

1

t_ON

=

⋅

V_OUT

Figure 2. CCM vs. BCM Control

where V_IN,PKis the amplitude of the line voltage and f_LINEis

the line frequency.

The fundamental idea of BCM PFC is that the inductor

current starts from zero in each switching period, as shown

in Figure 3. When the power transistor of the boost

converter is turned on for a fixed time, the peak inductor

current is proportional to the input voltage. Since the current

waveform is triangular; the average value in each switching

period is proportional to the input voltage. In a sinusoidal

input voltage, the input current of the converter follows the

input voltage waveform with very high accuracy and draws

a sinusoidal input current from the source. This behavior

makes the boost converter in BCM operation an ideal

candidate for power factor correction.

Figure 4 shows how the MOSFET onꢀtime and switching

frequency change as output power decreases. When the load

decreases, as shown in the right side of Figure 4, the peak

inductor current diminishes with reduced MOSFET onꢀtime

and, therefore, the switching frequency increases. Since this

can cause severe switching losses at lightꢀload condition and

tooꢀhigh switching frequency operation may occur at

startup, the maximum switching frequency of FL7930B is

limited to 300kHz.

Rev. 1.0.0 • 4/20/11

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ANꢀ9738

APPLICATION NOTE

I_L

Average of input

current

V_GS

Figure 5. Half-Bridge, LC Series Resonant Converter

f_SW

To overcome the limitation of series resonant converters, the

LLC resonant converter has been proposed. The LLC

resonant converter is a modified LC series resonant

converter implemented by placing a shunt inductor across

the transformer primary winding, as depicted in Figure 6.

When this topology was first presented, it did not receive

much attention due to the counterintuitive concept that

increasing the circulating current in the primary side with a

shunt inductor can be beneficial to circuit operation.

However, it can be very effective in improving efficiency

for highꢀinput voltage applications where the switching loss

is more dominant than the conduction loss.

t

Figure 4. Frequency Variation of BCM PFC

Since the design of the filter and inductor for a BCM PFC

converter with variable switching frequency should be at

minimum frequency condition, it is worthwhile to examine

how the minimum frequency of BCM PFC converter

changes with operating conditions.

In most practical designs, this shunt inductor is realized

using the magnetizing inductance of the transformer. The

circuit diagram of LLC resonant converter looks much the

same as the LC series resonant converter: the only

difference is the value of the magnetizing inductor. While

the series resonant converter has a magnetizing inductance

larger than the LC series resonant inductor (L_r), the

magnetizing inductance in an LLC resonant converter is just

3~8 times L_r, which is usually implemented by introducing

an air gap in the transformer.

2. Consideration of LLC Resonant

Converter

The attempt to obtain everꢀincreasing power density in

switchedꢀmode power supplies has been limited by the size

of passive components. Operation at higher frequencies

considerably reduces the size of passive components, such

as transformers and filters; however, switching losses have

been an obstacle to highꢀfrequency operation. To reduce

switching losses and allow highꢀfrequency operation,

resonant switching techniques have been developed. These

techniques process power in a sinusoidal manner and the

switching devices are softly commutated. Therefore, the

switching losses and noise can be dramatically reduced.

Figure 6. Half-Bridge LLC Resonant Converter

Among various kinds of resonant converters, the simplest and

most popular is the LC series resonant converter, where the

rectifierꢀload network is placed in series with the LC resonant

network, as depicted in Figure 5. In this configuration, the

resonant network and the load act as a voltage divider. By

changing the frequency of driving voltage V_d, the impedance

of the resonant network changes. The input voltage is split

between this impedance and the reflected load. Since it is a

voltage divider, the DC gain of a LC series resonant converter

is always <1. At lightꢀload condition, the impedance of the

load is large compared to the impedance of the resonant

network; all the input voltage is imposed on the load. This

makes it difficult to regulate the output at light load.

Theoretically, frequency should be infinite to regulate the

output at no load.

An LLC resonant converter has many advantages over a

series resonant converter. It can regulate the output over

wide line and load variations with a relatively small

variation of switching frequency. It can achieve zero voltage

switching (ZVS) over the entire operating range. All

essential parasitic elements; including the junction

capacitances of all semiconductor devices, the leakage

inductance, and magnetizing inductance of the transformer;

are utilized to achieve soft switching.

Rev. 1.0.0 • 4/20/11

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ANꢀ9738

APPLICATION NOTE

This application note presents design considerations for an

LLC resonant halfꢀbridge converter employing Fairchild’s

FAN7621S. It includes explanation of the LLC resonant

converter operation principles, designing the transformer

and resonant network, and selecting the components. The

stepꢀbyꢀstep design procedure, explained with a design

example, helps design the LLC resonant converter. 0 shows

a simplified schematic of a halfꢀbridge LLC resonant

converter, where L_mis the magnetizing inductance that acts

as a shunt inductor, L_ris the series resonant inductor, and C_r

is the resonant capacitor. Figure 8 illustrates the typical

waveforms of the LLC resonant converter. It is assumed that

the operation frequency is the same as the resonance

frequency, determined by the resonance between L_rand C_r.

Since the magnetizing inductor is relatively small, a

considerable amount of magnetizing current (I_m) exists,

which freewheels in the primary side without being

involved in the power transfer. The primaryꢀside current (I_p)

is the sum of the magnetizing current and the secondaryꢀside

current referred to the primary.

Figure 7. Schematic of Half-Bridge LLC

Resonant Converter

I_p

I_m

In general, the LLC resonant topology consists of the three

stages shown in 0; squareꢀwave generator, resonant

network, and rectifier network.

I_DS1

ꢀ

The squareꢀwave generator produces a squareꢀwave

voltage, V_d, by driving switches Q₁and Q₂alternately

with 50% duty cycle for each switch. A small dead time

is usually introduced between the consecutive

transitions. The squareꢀwave generator stage can be

built as a fullꢀbridge or halfꢀbridge type.

I_D

V_IN

V_d

ꢀ

The resonant network consists of a capacitor, leakage

inductances, and the magnetizing inductance of the

transformer. The resonant network filters the higher

harmonic currents. Essentially, only sinusoidal current

is allowed to flow through the resonant network even

though a squareꢀwave voltage is applied. The current

(I_p) lags the voltage applied to the resonant network

(that is, the fundamental component of the squareꢀwave

voltage (V_d) applied to the halfꢀbridge totem pole),

which allows the MOSFETs to be turned on with zero

voltage. As shown in Figure 8, the MOSFET turns on

while the voltage across the MOSFET is zero by

flowing current through the antiꢀparallel diode.

V_gs1

V_gs2

Figure 8. Typical Waveforms of Half-Bridge LLC

Resonant Converter

The filtering action of the resonant network allows the use

of the fundamental approximation to obtain the voltage gain

of the resonant converter, which assumes that only the

fundamental component of the squareꢀwave voltage input to

the resonant network contributes to the power transfer to the

output. Because the rectifier circuit in the secondary side

acts as an impedance transformer, the equivalent load

resistance is different from actual load resistance. Figure 9

shows how this equivalent load resistance is derived. The

primaryꢀside circuit is replaced by a sinusoidal current

source, I_ac, and a square wave of voltage, V_RI, appears at the

input to the rectifier. Since the average of |I_ac| is the output

current, I_o, I_ac, is obtained as:

ꢀ

The rectifier network produces DC voltage by

rectifying the AC current with rectifier diodes and a

capacitor. The rectifier network can be implemented as

a fullꢀwave bridge or a centerꢀtapped configuration with

capacitive output filter.

π ⋅ I_o

2

I_ac

=

sin(ωt)

(3)

Rev. 1.0.0 • 4/20/11

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4

ANꢀ9738

APPLICATION NOTE

and V_RIis given as:

C_r

L_r

V_d

+

V_O

+

V_RI= +V_oif sin(

ω

t) > 0

V_IN

(4)

(5)

V_RI

L_m

V_RI= −V_oif sin(

ω

t) < 0

R_o

-

where V_ois the output voltage.

N_p:N_s

The fundamental component of V_RIis given as:

8n²

π ²

R_ac

=

R_o

n=N_p/N_s

4V_o

F

V_RI

=

sin(ωt)

π

F

C_r

L_r

V_Ro

Since harmonic components of V_RIare not involved in the

power transfer, AC equivalent load resistance can be

calculated by dividing V_RI^Fby I_acas:

F

R_ac

V_d

F

(nV_RI

)

L_m

F

Figure 10. AC Equivalent Circuit for LLC

Resonant Converter

V_RI

I_ac

8 V_o

8

R_ac=

=

R_o

(6)

π ²I_oπ ²

With the equivalent load resistance obtained in Equation 7,

the characteristics of the LLC resonant converter can be

derived. Using the AC equivalent circuit of Figure 10, the

voltage gain, M, is obtained as:

Considering the transformer turns ratio (n=N_p/N_s), the

equivalent load resistance shown in the primary side is

obtained as:

8n²

π ²

4n ⋅V

π

^osin(

ωt)

F

V_RO

n ⋅V_RI

V_d

2n ⋅V_o

V_in

(7)

R_ac=

R_o

M =

=

F

4 V

V_d

ⁱⁿsin(

ωt)

π

2

By using the equivalent load resistance, the AC equivalent

circuit is obtained, as illustrated in Figure 10, where V_d^Fand

V_RO^Fare the fundamental components of the driving voltage,

V_dand reflected output voltage, V_RO(nV_RI), respectively.

(8)

ω

ω_o

(

)²(m −1)

=

ω²

ω

ω²

(

−1) + j

(

−1)(m −1)Q

2

ω_p

ω_oω_o

pk

I_ac

where:

L_p= L_m+ L_r, R_ac

8n²

L_p

R_o, m =

L_r

=

π ²

L_r

1

Q =

,

ω_o

, ω_p=

C_rR_ac

L_rC_r

L_pC_r

As can be seen in Equation (8), there are two resonant

frequencies. One is determined by L_rand C_r, while the other

is determined by L_pand C_r.

Equation (8) shows the gain is unity at resonant frequency

(ω_o), regardless of the load variation, which is given as:

π

=

⋅I

2

I_ac

=

^osin(wt)

2

(m −1) ⋅ω_p

2n ⋅V_o

M =

=

=1 atω = ω_o

(9)

2

V

ω_o−ω_p

in

4V

F

V_RI

^osin(wt)

The gain of Equation (8) is plotted in Figure 11 for different

Q values with m=3, f_o=100kHz, and f_p=57kHz. As observed

in Figure 11, the LLC resonant converter shows gain

characteristics that are almost independent of the load when

the switching frequency is around the resonant frequency, f_o.

This is a distinct advantage of LLCꢀtype resonant converter

over the conventional series resonant converter. Therefore,

it is natural to operate the converter around the resonant

frequency to minimize the switching frequency variation.

π

Figure 9. Derivation of Equivalent Load Resistance R_ac

Rev. 1.0.0 • 4/20/11

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ANꢀ9738

APPLICATION NOTE

The operating range of the LLC resonant converter is

limited by the peak gain (attainable maximum gain), which

is indicated with ‘Q’ in Figure 11. Note that the peak

voltage gain does not occur at f_oor f_p. The peak gain

frequency, where the peak gain is obtained, exists between

f_pand f_o, as shown in Figure 11. As Q decreases (as load

decreases), the peak gain frequency moves to f_pand higher

peak gain is obtained. Meanwhile, as Q increases (as load

increases), the peak gain frequency moves to f_oand the peak

gain drops; the fullꢀload condition should be worst case for

the resonant network design.

be divided into two categories; rising current when the

MOSFET is on and output diode current when the MOSFET

is off, as shown in Figure 12.

1

f_o

=

f_p

=

2

π L_rC_r

2π

L_pC_r

Figure 12. Inductor and Input Current

L_r/ C_r

Q =

Because switching frequency is much higher than line

frequency, input current can be assumed to be constant

during a switching period, as shown in Figure 133.

R_ac

M_{@ f}=1

o

Figure 11. Typical Gain Curves of LLC Resonant

Converter (m=3)

3. Design Considerations

Figure 13. Inductor and Input Current

This design procedure uses the schematic in Figure 1 as a

reference. A 150W street lighting application with universal

input range is selected as a design example. The design

specifications are:

With the estimated efficiency, Figure 12 and Figure 13,

inductor current peak (I_L,PK), maximum input current

(I_IN,MAX), and input Root Mean Square (RMS) current

(I_IN,MAXRMS) are given as:

ꢀ

Line Voltage Range: 85V_A~277V_AC(50Hz)

Output of Converter: 103V/1.46A (150W)

PFC Output Voltage: 430V

4

⋅ P_OUT

I _{L ,PK}

=

[ A ]

(10)

η ⋅

2

⋅V_{LINE ,MIN}

I_IN,MAX= I_L,PK

/

2

[ A]

2 [ A]

(11)

(12)

Overall Efficiency: 90% (PFC: 95%, LLC: 95%)

I_IN,MAXRMS= I_IN,MAX

/

3.1 PFC Section

STEP-1] Define System Specification

(Design Example) Input voltage range is universal input,

output load is 465mA, and estimated efficiency is selected

as 0.9.

[

ꢀ

Line Frequency Range (V_LINE,MINand V_LINE,MAX

Line Frequency (f_LINE

OutputꢀVoltage (V_OUT

Output Load Current (I_OUT

Output Power (P_OUT=V_OUT× I_OUT

Estimated Efficiency (

)

V_{LINE ,MIN}= 85V_AC, V_LINE,MAX= 277V_AC

f_LINE= 50Hz

)

V_OUT= 430V , I_OUT= 465mA

)

η

= 0.9

η

)

4⋅ P

4⋅430V ⋅0.465A

0.9⋅ 2 ⋅85

OUT

To calculate the maximum input power, it is necessary to

estimate the power conversion efficiency. At universal input

range, efficiency is recommended at 0.9; 0.93~0.95 is

recommended when input voltage is high. When input

voltage is set at the minimum, input current becomes the

maximum to deliver the same power compared at high line.

Maximum boost inductor current can be detected at the

minimum line voltage and at its peak. Inductor current can

I_L,PK

=

= 7.392A

η

=

⋅ 2 ⋅V_LINE,MIN

I_L,PK

7.392A

I_IN,MAX

=

= 3.696A

2

I_IN,MAX

3.696A

I_IN,MAXRMS

=

= 2.613A

2

Rev. 1.0.0 • 4/20/11

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6

ANꢀ9738

APPLICATION NOTE

When selecting wire diameter and strands; current density,

window area (A_W, refer to Figure 14) of the selected core,

and fill factor need to be considered. The winding sequence

of the boost inductor is relatively simple compared to a DCꢀ

DC converter, so fill factor can be assumed about 0.2~0.3.

[STEP-2] Boost Inductor Design

The boost inductor value is determined by the output power

and the minimum switching frequency. The minimum

switching frequency must be higher than the maximum

audible frequency band of 20kHz. Minimum frequency near

20kHz can decrease switching loss with the cost of

increased inductor size and line filter size. Tooꢀhigh

minimum frequency may increase the switching loss and

make the system respond to noise. Selecting in the range of

about 30~60kHz is a common choice; 40~50kHz is

recommended with FL7930B.

Layers cause the skin effect and proximity effect in the coil,

so real current density may be higher than expected.

The minimum switching frequency may appear at minimum

input voltage or maximum input voltage, depending on the

output voltage level. When PFC output voltage is less than

430V, minimum switching appears at the maximum input

voltage (see Fairchild application note ANꢀ6086). Inductance

is obtained using the minimum switching frequency:

2

η⋅

(

2

V_LINE

)

L =

[ H ]







2

V_LINE

(13)



4

⋅ f_SW,MIN⋅ P_OUT

⋅

1

+

Figure 14. Typical B-H Curves of Ferrite Core







V_OUT

− 2V_LINE



where L is boost inductance and f_SW,MINis the minimum

switching frequency.

The maximum onꢀtime needed to carry peak inductor

current is calculated as:

I _L,PK

t_ON,MAX= L ⋅

[s]

(14)

2 ⋅V_{LINE, MIN}

Once inductance and the maximum inductor current are

calculated, the turn number of the boost inductor should be

determined considering the core saturation. The minimum

number of turns is given as:

Figure 15. A and A_W

e

I_L,PK⋅ L[ ꢁH ]

A_e[ mm²] ⋅ ꢀB

(Design Example) Since the output voltage is 430V, the

minimum frequency occurs at highꢀline (277V_AC) and fullꢀ

load condition. Assuming the efficiency is 90% and

selecting the minimum frequency as 50kHz, the inductor

value is obtained as:

N_BOOST

≥

[Turns ]

(15)

where A_eis the crossꢀsectional area of the core and ꢀB is

the maximum flux swing of the core in Tesla. ꢀB should be

set below the saturation flux density.

2

η⋅

⋅ f_{SW ,MIN}⋅ P

(

2

V_LINE

)

L =

Figure 14 shows the typical BꢀH characteristics of a ferrite

core from TDK (PC45). Since the saturation flux density

(ꢀB) decreases as the temperature increases, the highꢀ

temperature characteristics should be considered.











2

−

V_LINE



4

⋅

1

+

OUT





V_OUT

2

V_LINE

2

0

.

9

⋅

(

2

×

277

)

=

= 307.2[ꢁH ]







2

−

⋅277



4

⋅

50

⋅

10³

⋅

200

⋅

1

+







RMS inductor current (I_L,RMS) and current density of the coil

(I_L,DENSITY) can be given as:

430

2

⋅

277



Assuming EER3019N core (PLꢀ7, A_e=137mm²) is used and

setting ꢀB as 0.3T, the primary winding should be:

I_L,PK

I_L,RMS

=

[ A]

I_L,RMS

(16)

(17)

6

I_L,PK⋅ L[ ꢁH ]

A_e[ mm²] ⋅ ꢀB

7.392 ⋅ 307

137 ⋅ 0.3

N_BOOST

≥

=

= 55[T ]

I_L,DENSITY

=

[ A / mm²

]

d







²

wire

The number of turns (N_BOOST) of the boost inductor is

determined as 55 turns.

π⋅

⋅ N_wire



2



where d_WIREis the diameter of winding wire and N_WIREis

the number of strands of winding wire.

When 0.10mm diameter and 50ꢀstrand wire is used, RMS

current of inductor coil and current density are:

Rev. 1.0.0 • 4/20/11

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7

ANꢀ9738

APPLICATION NOTE

I_L,PK

Auxiliary winding must give enough energy to trigger ZCD

threshold to detect zero current. Minimum auxiliary winding

turns are given as:

7

.

392

I_L,RMS

=

3.017 [ A]

6

I_L,RMS

3.017

I_L,DENSITY

=

=7. ]

68 [ A/ mm²







²

1.5

V ⋅ N_BOOST

2

π⋅

(0.1

/

2

)

⋅50

d

wire

π⋅

⋅ N_wire



N_AUX

≥

[Turns]

2

(18)



V_OUT

− 2V_LINE,MAX

where 1.5V is the positive threshold of the ZCD pin.

[STEP-3] Inductor Auxiliary Winding Design

To guarantee stable operation, it is recommended to add 2~3

turns to the auxiliary winding turns calculated in Equation

(18). However, too many auxiliary winding turns raise the

negative clamping loss at high line and positive clamping

loss at low line.

Figure 16 shows the application circuit of the nearby ZCD

pin from auxiliary winding.

(Design Example) 55 turns are selected as boost inductor

turns and auxiliary winding turns are calculated as:

1

.

5

V ⋅N_BOOST

V_LINE,MAX430− 2 ⋅277

1.5 ⋅55

N_AUX

≥

=

=2.15[Turns]

V_OUT

−

2

Choice should be around 4~5 turns after adding 2~3 turns.

[STEP-4] ZCD Circuit Design

Figure 16. Application Circuit of ZCD Pin

If a transition time when V_AUXILIARYdrops from 1.4V to 0V

is ignored from Figure 17, the necessary additional delay by

the external resistor and capacitor is one quarter of the

resonant period. The time constant made by ZCD resistor

and capacitor should be the same as one quarter of the

resonant period:

The first role of ZCD winding is detecting the zeroꢀcurrent

point of the boost inductor. Once the boost inductor current

becomes zero, the effective capacitance (C_eff) at the

MOSFET drain pin and the boost inductor resonate

together. To minimize the constant turnꢀon time

deterioration and turnꢀon loss, the gate is turned on again

when the drain source voltage of the MOSFET (V_DS)

reaches the valley point shown in Figure 17. When input

voltage is lower than half of the boosted output voltage,

Zero Voltage Switching (ZVS) is possible if MOSFET turnꢀ

on is triggered at valley point.

2

π C_eff⋅ L

(19)

R_ZCD⋅C_ZCD

=

4

where C_effis the effective capacitance at the MOSFET drain

pin; C_ZCDis the external capacitance at the ZCD pin; and

R_ZCDis the external resistance at the ZCD pin.

The second role of R_ZCDis the current limit of the internal

negative clamp circuit when auxiliary voltage drops to

negative due to MOSFET turn on. ZCD voltage is clamped

0.65V and minimum R_ZCDcan be given as:













N_AUX

2

V_LINE,MAX

mA

−0.65V

N_BOOST

(20)

R_ZCD

≥

[ꢂ]

3

where 3mA is the clamping capability of the ZCD pin.

The calculation result of Equation (20) is normally higher

than 15kꢂ. If 20kꢂ is assumed as R_ZCD, calculated C_ZCD

from Equation (19) is around 10pF when the other

components are assumed as conventional values used in the

field. Because most IC pins have several pF of parasitic

capacitance, C_ZCDcan be eliminated when R_ZCDis higher

than 30kꢂ. However, a small capacitor would be helpful

when auxiliary winding suffers from operating noise.

The PFC control loop has two conflicting goals: output

voltage regulation and making the input current shape the

same as input voltage. If the control loop reacts to regulate

output voltage smoothly, as shown in Figure 18, control

www.fairchildsemi.com

Figure 17. ZCD Detection Waveforms

Rev. 1.0.0 • 4/20/11

8

ANꢀ9738

APPLICATION NOTE

voltage varies widely with the input voltage variation. Input

current acts to the control loop and sinusoidal input current

shape cannot be attained. This is the reason control response

of most PFC topologies is very slow and turnꢀon time over

AC period is kept constant. This is also the reason output

voltage ripple is made by input and output power

relationship, not by controlꢀloop performance.

Figure 18. Input Current Deterioration by Fast Control

Figure 20. Inductor Current at AC Voltage Zero

If onꢀtime is controlled constantly over one AC period, the

inductor current peak follows AC input voltage shape and

achieves good power factor. Offꢀtime is basically inductor

current reset time due to Boundary Mode and is determined

by the input and output voltage difference. When input

voltage is at its peak, the voltage difference between input

and output voltage is small and long turnꢀoff time is

necessary. When input voltage is near zero, turnꢀoff time is

short, as shown in Figure 19 and Figure 20. Though

inductor current drops to zero, the minor delay is explained

above. The delay can be assumed as fixed when AC is at

line peak and zero. Near AC line peak, the inductor current

decreasing slope is slow and inductor current slope is also

slow during the ZCD delay. The amount of negative current

is not much higher than the inductor current peak. Near the

AC line zero, inductor current decreasing slope is very high

and the amount of negative current is higher than positive

inductor current peak because input voltage is almost zero.

Negative inductor current creates zeroꢀcurrent distortion and

degrades the power factor. Improve this by extending turnꢀ

on time at the AC line input near the zero cross.

Negative auxiliary winding voltage, when the MOSFET is

turned on, is linearly proportional to the input voltage.

Sourcing current generated by the internal negative

clamping circuit is also proportional to sinusoidal input

voltage. That current is detected internally and added to the

internal sawtooth generator, as shown in Figure 21.

Figure 21. ZCD Current and Sawtooth Generator

When the AC input voltage is almost zero, no negative

current is generated from inside, but sourcing current when

input voltage is high is used to raise the sawtooth generator

slope and turnꢀon time is shorter. As a result, turnꢀon time

when AC voltage is zero is longer compared to AC voltage,

in peaks shown in Figure 22.

Figure 19. Inductor Current at AC Voltage Peak

Rev. 1.0.0 • 4/20/11

www.fairchildsemi.com

9

ANꢀ9738

APPLICATION NOTE

control voltage decreases rapidly. For example, if input

voltage doubles, control voltage drops to one quarter.

Making control voltage maximum when input voltage is low

and at full load is necessary to use the whole control range

for the rest of the input voltage conditions. Matching

maximum turnꢀon time needed at low line is calculated in

Equation (14) and turnꢀon time adjustment by R_ZCD

guarantees use of the full control range. R_ZCDfor control

range optimization is obtained as:

2

0

⋅V_LINE,MIN⋅ N _AUX

.469 mA⋅ N_BOOST

28 ꢁs

t_{ON ,MAX}− t_{ON ,MAX}

R_ZCD

≥

⋅

[ꢂ]

(21)

1

Figure 22. THD Improvement

The current that comes from the ZCD pin, when auxiliary

voltage is negative, depends on R_ZCD. The second role of

R_ZCDis also related to improving the Total Harmonic

Distortion (THD).

where:

t_ON,MAXis calculated by Equation (14)

t_ON,MAX1is maximum onꢀtime programming 1;

N_BOOSTis the winding turns of boost inductor; and

N_AUXis the auxiliary winding turns.

;

The third role of R_ZCDis making the maximum turnꢀon time

adjustment. Depending on sourcing current from the ZCD

pin, the maximum onꢀtime varies as in Figure 23.

R_ZCDcalculated by Equation (20) is normally lower than the

value calculated in Equation (21). To guarantee the needed

turn onꢀtime for the boost inductor to deliver rated power,

the R_ZCDfrom Equation (20) is normally not suitable. R_ZCD

should be higher than the result of Equation (21) when

output voltage drops as a result of low line voltage.

When input voltage is high and load is light, not much input

current is needed and control voltage of V_COMPtouches

switching stop level, such as if FL7930B is 1V. However, in

some applications, a PFC block is needed to operate

normally at light load. To compensate control range

correctly, input voltage sensing is necessary, such as with

Fairchild’s interleaved PFC controller FAN9612, or special

care on sawtooth generator is necessary. To guarantee

enough control range at high line, clamping output voltage

lower than rated on the minimum input condition can help.

Figure 23. Maximum On-Time Variation vs. I_ZCD

With the aid of I_ZCD, an internal sawtooth generator slope is

changed and turnꢀon time varies as shown in Figure 24.

(Design Example) Minimum R_ZCDfor clamping capability

is calculated as:













N_AUX

2

V_LINE,MAX−0.65V

N_BOOST

R_ZCD

≥

3

mA

5

34









2

⋅

277

−

0.65

V





=

=18.9 kꢂ

3

mA

Minimum R_ZCDfor control range is calculated as:

2

⋅V_LINE,MIN⋅ N _AUX

.469 mA⋅ N_BOOST

28 ꢁs

t_{ON ,MAX}−t_ON,MAX

R_ZCD

≥

⋅

0

1

28 ꢁs 85

42 ꢁs−10.9 ꢁs 0.469 mA⋅55

2

⋅

⋅5

=

⋅

= 20.97 kꢂ

Figure 24. Internal Sawtooth Wave Slope Variation

A choice close to the value calculated by the control range is

recommended. 39kꢂ is chosen in this case.

R_ZCDalso influences control range. Because FL7930B

doesn’t detect input voltage, voltageꢀmode control value is

determined by the turnꢀon time to deliver the needed current

to boost output voltage. When input voltage increases,

Rev. 1.0.0 • 4/20/11

www.fairchildsemi.com

10

ANꢀ9738

APPLICATION NOTE

[STEP-5] Output Capacitor Selection

(Design Example) With the ripple specification of 8V_pꢀp

,

the capacitor should be:

The output voltage ripple should be considered when

selecting the output capacitor. Figure 25 shows the line

frequency ripple on the output voltage. With a given

specification of output ripple, the condition for the output

capacitor is obtained as:

I_OUT

0

π⋅50

.

465

C_O

≥

=

=185 [ꢁF ]

2

π⋅ f_LINE⋅ꢀV_OUT,ripple

2

⋅8

Since minimum allowable output voltage during one cycle

line (20ms) dropꢀouts is 330V, the capacitor should be:

2

× P_OUT⋅ t_HOLD

I_OUT

C_O

≥

C_OUT

≥

[ f ]

(22)

2

(

V_OUT

−

⋅

0

.

5

⋅ ꢀV_{OUT ,ripple}

)

− V_{OUT ,MIN}

2

π ⋅ f_LINE⋅ ꢀV_{OUT ,RIPPLE}

−

3

2

⋅

200

20 ×10

where V_OUT,RIPPLEis the peakꢀtoꢀpeak output voltage ripple

specification.

=

= 110 [ ꢁF ]

2

(430

−

0

.

5

⋅

8

)

− 330

To meet both conditions, the output capacitor must be

larger than 140ꢁF. A 240ꢁF capacitor is selected for the

output capacitor.

The output voltage ripple caused by the ESR of the

electrolytic capacitor is not as serious as other power

converters because output voltage is high and load current is

small. Since too much ripple on the output voltage may

cause premature OVP during normal operation, the peakꢀtoꢀ

peak ripple specification should be smaller than 15% of the

nominal output voltage.

The voltage stress of selected capacitor is calculated as:

2.730

2.500

V_OVP

^,MAX⋅V_OUT

V_ST,COUT

=

⋅430 =469.5 [V ]

V_REF

The holdꢀup time should also be considered when

determining the output capacitor as:

[STEP-6] MOSFET and DIODE Selection

Selecting the MOSFET and diode requires extensive

knowledge and calculation regarding loss mechanisms and

gets more complicated if proper selection of a heatsink is

added. Sometimes the loss calculation itself is based on

assumptions that may be far from reality. Refer to industry

resources regarding these topics. This note shows the

voltage rating and switching loss calculations based on a

linear approximation.

2

⋅ P_OUT⋅t_HOLD

C_OUT

≥

[ f ]

(23)

2

(

V_OUT

−

0

.

5

⋅ꢀV_OUT,RIPPLE

)

−V_OUT,MIN

where t_HOLDis the required holdꢀup time and V_OUT,MINis the

minimum output voltage during holdꢀup time.

I

diode

The voltage stress of the MOSFET is obtained as:

V_OV

P,MAX

V_{ST ,Q}

=

⋅V_OUT+V_DROP,DOUT[V ]

(25)

V_REF

where V_DROP,DOUTis the maximum forwardꢀvoltage drop of

output diode.

I

diode,ave

I

=I_OUT(1ꢀcos(4p.f_L.t))

diode,ave

After the MOSFET is turned off, the output diode turns on

and a large output electrolytic capacitance is shown at the

drain pin; thus a drain voltage clamping circuit that is

necessary on other topologies is not necessary in PFC.

During the turnꢀoff transient, boost inductor current changes

the path from MOSFET to output diode. Before the output

diode turns on; a minor voltage peak can be shown at drain

pin, which is proportional to MOSFET turnꢀoff speed.

I

OUT

I

OUT

2p.f_L.C_OUT

V

=

OUT,ripple

V

OUT

t

MOSFET loss can be divided into three parts: conduction

loss, turnꢀoff loss, and discharge loss. Boundary mode

guarantees Zero Current Switching (ZCS) of the MOSFET

when turned on, so turnꢀon loss is negligible.

Figure 25. Output Voltage Ripple

The voltage rating of capacitor can be obtained as:

V_OV

P,MAX

V_{ST ,COUT}

=

⋅V_OUT[V ]

The MOSFET RMS current and conduction loss are

obtained as:

(24)

V_REF

where V_OVP,MAXand V_REFare the maximum tolerance

specifications of overꢀvoltage protection triggering voltage

and reference voltage at error amplifier, respectively.

4 2 ⋅V_LINE

1

6

(26)

(27)

I_Q,RMS= I_L,PK

⋅

−

[ A]

9

π⋅V_OUT

2

P_Q,CON

=

(

I_Q,RMS

)

⋅ R_DS,ON[W ]

Rev. 1.0.0 • 4/20/11

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11

ANꢀ9738

APPLICATION NOTE

The average diode current and power loss are obtained as:

I_OUT

where I_Q,RMSis the RMS value of MOSFET current,

P_Q,CONis the conduction loss caused by MOSFET current,

and R_DS,ONis the ON resistance of the MOSFET.

I_DOUT,AVE

=

[ A]

(31)

η

On resistance is described as “static on resistance” and

varies depending on junction temperature. That variation

information is normally supplied as a graph in the datasheet

and may vary by manufacturer. When calculating

conduction loss, generally multiply three by the R_DS,ONfor

more accurate estimation.

P_DOUT=V_DROP,DOUT⋅I_DOUT,AVE[W]

(32)

where V_DROP,DOUTis the forward voltage drop of diode.

(Design Example) Internal reference at the feedback pin is

2.5V and maximum tolerance of OVP trigger voltage is

2.730V. If Fairchild’s FDPF17N60NT MOSFET and

FFPF08H60S diode are selected, V_D,FORis 2.1V at 8A,

25°C, maximum R_DS,ONis 0.34ꢂ at drain current is 17A,

and maximum C_OSSis 32pF at drainꢀsource voltage is 480V.

The precise turnꢀoff loss calculation is difficult because of

the nonlinear characteristics of MOSFET turnꢀoff. When

piecewise linear current and voltage of MOSFET during

turnꢀoff and inductive load are assumed, MOSFET turnꢀoff

loss is obtained as:

V_OV

^MAX⋅V_OUT+V_DROP,DIODE

1

2

P,

V_ST,Q

=

P

=

⋅V_OUT⋅I_L⋅t_OFF⋅ f_SW[W]

(28)

Q,SWOFF

V_REF

2.73

2.50

=

⋅

430

+

2

.

1

=

471

.

6

[V ]

where t_OFFis the turnꢀoff time and f_SWis the switching

frequency.





²



1

6

4

9

2

⋅V_LINE

Boundary Mode PFC inductor current and switching

frequency vary at every switching moment. RMS inductor

current and average switching frequency over one AC

period can be used instead of instantaneous values.

P

=

(

)

I_L,PK

⋅

−

⋅ R_DS,ON

Q,CON





π⋅V_OUT









²

1

6

4

9

2

⋅85



=

7.

392

⋅

−

⋅

(

0

.

34

)

=

2

.23[W ]





π⋅430





Individual loss portions are changed according to the input

voltage; maximum conduction loss appears at low line

because of high input current; and maximum switching off

loss appears at high line because of the high switching

frequency. The resulting loss is always lower than the

summation of the two losses calculated above.

1

2

P_Q,SWOFF

=

⋅V_OUT⋅ I _L⋅t_OFF⋅ f_SW

1

2

=

⋅

430

⋅

2

.613

⋅

50 ns⋅(50 k /

0.

8

) =

1.755 [W ]

1

P_Q,DISCHG

=

⋅

(

C_OSS+C_EXT+C_PAR

)

⋅V_O²_UT⋅ f_SW

2

Capacitive discharge loss made by effective capacitance

1

2

=

⋅32 p⋅430²⋅(50k / 0.8 ) =0.184[W ]

shown at drain and source, which includes MOSFET C_OSS

,

an externally added capacitor to reduce dv/dt and parasitic

capacitance shown at drain pin, is also dissipated at

MOSFET. That loss is calculated as:

Diode average current and forwardꢀvoltage drop loss as:

I_OUT

0.5

I_DOUT,AVE

=

=0.56[ A]

η

0.9

1

2

P

=

(

C_OSS+C_EXT+C_PAR

)

⋅V_O²_UT⋅ f_SW[W]

(29)

P_DOUT,LOSS=V_DOUT,FOR⋅ I_DOUT,AVE

= 2.1 ⋅0.56 =1.46[W ]

Q,DISCHG

where:

C_OSSis the output capacitance of MOSFET;

C_EXTis an externally added capacitance at drain and source

of MOSFET; and

[STEP-7] Determine Current-Sense Resistor

It is typical to set pulseꢀbyꢀpulse current limit level a little

higher than the maximum inductor current calculated by

Equation (10). For 10% margin, the currentꢀsensing resistor

is selected as:

C_PARis the parasitic capacitance shown at drain pin.

Because the C_OSSis a function of the drain and source

voltage, it is necessary to refer to graph data showing the

relationship between C_OSSand voltage.

V_CS,LIM

R_CS

=

[ꢂ]

(33)

I_L,PK⋅1.1

Estimate the total power dissipation of MOSFET as the sum

of three losses:

Once resistance is calculated, its power loss at low line is

calculated as:

P = P_Q,CON+P_Q,SWOFF+P_Q,DISCHG[W]

(30)

Q

P

_RCS=I_Q²_,RMS⋅R_CS[W]

(34)

Diode voltage stress is the same as the output capacitor

stress calculated in Equation (24).

Power rating of the sensing resistor is recommended a twice

the power rating calculated in Equation (34).

Rev. 1.0.0 • 4/20/11

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12

ANꢀ9738

APPLICATION NOTE

∧

(

V_LINE

²R_L

)

v_OUT

∧

v_COMP

1

(Design Example) Maximum inductor current is 4.889A

and sensing resistor is calculated as:

= K_SAW

⋅

(36)

s

4

V_OUT⋅L

1

+

2

π f _p

V_CS,LIM

pk

0.8

7.392 ⋅1.1

R_CS

=

= 0.098[ꢂ]

2

where

and R_Lis the output load resistance in a

f _p

=

I

⋅1.1

ind

2

π⋅ R_LC_OUT

given load condition.

Choosing 0.1ꢂ as R_CS, power loss is calculated as:

P_RCS,LOSS= I_Q²_,RMS⋅R_CS436²

=2. ⋅0.098 =0.58[W]

Figure 27 and Figure 28 show the variation of the controlꢀ

toꢀoutput transfer function for different input voltages and

different loads. Since DC gain and crossover frequency

increase as input voltage increases, and DC gain increases

as load decreases, high input voltage and light load is the

worst condition for feedback loop design.

Recommended power rating of sensing resistor is 1.19W.

[STEP-8] Design Compensation Network

The boost PFC power stage can be modeled as shown in

Figure 26 MOSFET and diode can be changed to lossꢀfree

resistor model and then modeled as a voltageꢀcontrolled

current source supplying RC network.

Figure 27. Control-to-Output Transfer Function for

Different Input Voltages

Figure 28. Control-to-Output Transfer Function for

Different Loads

Figure 26. Small Signal Modeling of the Power Stage

Proportional and integration (PI) control with highꢀ

frequency pole is typically used for compensation, as shown

in Figure 29. The compensation zero (f_CZ) introduces phase

boost, while the highꢀfrequency compensation pole (f_CP)

attenuates the switching ripple.

By averaging the diode current during the half line cycle,

the lowꢀfrequency behavior of the voltage controlled current

source of Figure 26 is obtained as:

2

V_LINE

2

V_LINE

L

I_DOUT,AVE= K_SAW

⋅

[ A]

(35)

4V_OUT

The transfer function of the compensation network is

obtained as:

where:

L is the boost inductance;

V_OUTis the output voltage; and

s

∧

1

+

v_COMP

∧

v_OUT

2

π

s

f_I

2

π f_CZ

s

=

⋅

K_SAWis the internal gain of sawtooth generator (that of

(37)

FL7930B is 8.496×10^ꢀ6).

π f_CP

Then the lowꢀfrequency, smallꢀsignal, controlꢀtoꢀoutput

transfer function is obtained as:

Rev. 1.0.0 • 4/20/11

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13

ANꢀ9738

APPLICATION NOTE

2

V_OUT

.

5

115ꢁmho

C_{COMP, LF}+C_{COMP, HF}

Typically, high R_FB1is used to reduce power consumption

and C_FBcan be added to raise the noise immunity. The

maximum C_FBcurrently used is several nano farads. Adding

a capacitor at the feedback loop introduces a pole as:

f_I=

f_CZ

f_CP

⋅

2

π⋅

(

)

1

where

=

2

π⋅R_COMP⋅C_{COMP, LF}

1

f_FP

=

2

π⋅

(

R_FB// R_FB⋅C_FB

)









C_{COMP, LF}⋅C_{COMP, HF}

1

2

(40)

π⋅R_COMP

⋅

1







C_{COMP, LF}+C

≅

[Hz]

^{COMP, HF}

2

π⋅ R_FB⋅C_FB

2

If C_COMP,LFis much larger than C_COMP,HF, f_Iand f_CPcan be

simplified as:

R_FB⋅ R_FB

1

2

where

(

R_FB// R_FB

)

=

1

2

R_FB+ R_FB

1

2

.

2

.

5

115ꢁmho

π⋅C_{COMP, LF}

f_I

≅

⋅

[ Hz]

Though R_FB1is high, pole frequency made by the

synthesized total resistance and several nano farads is

several kilo hertz and rarely affects controlꢀloop response

V_OUT

2

(38)

1

f_CP

≅

[Hz]

2

π⋅R_COMP⋅C_{COMP, HF}

The procedure to design the feedback loop is:

a. Determine the crossover frequency (f_C) around 1/10 ~

1/5 of line frequency. Since the controlꢀtoꢀoutput

transfer function of the power stage has ꢀ20dB/dec

slope and ꢀ90^ophase at the crossover frequency; it is

required to place the zero of the compensation network

(f_CZ) around the crossover frequency so 45° phase

margin is obtained. The capacitor C_COMP,LFis

determined as:

G

= 115ꢁmho

M

K_SAW

(

V_LINE

2

)

²2

⋅V_OUT⋅ L⋅C_OUT

.5 ⋅115ꢁmho

C_{COMP, LF}

≅

[ f ]

(41)

2

(

2

π f_C

)

To place the compensation zero at the crossover

frequency, the compensation resistor is obtained as:

1

R_COMP

=

[ꢂ]

(42)

2π⋅ f_C⋅C_COMP,LF

b. Place this compensator highꢀfrequency pole (f_CP) at

least a decade higher than f_Cto ensure that it does not

interfere with the phase margin of the voltage

regulation loop at its crossover frequency. It should also

be sufficiently lower than the switching frequency of

the converter for noise to be effectively attenuated. The

capacitor C_COMP,HFis determined as:

1

C_COMP,HF

=

[ꢂ]

Figure 29. Compensation Network

(43)

2π⋅ f_CP⋅ R_COMP

The feedback resistor is chosen to scale down the output

voltage to meet the internal reference voltage:

R_FB

1

⋅V_OUT

= 2.5V

(39)

R_FB+ R_FB

1

2

Rev. 1.0.0 • 4/20/11

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14

ANꢀ9738

APPLICATION NOTE

[STEP-9] Line Filter Capacitor Selection

(Design Example) If R_FB1is 11.7Mꢂ, then R_FB2is:

It is typical to use small bypass capacitors across the bridge

rectifier output stage to filter the switching current ripple, as

shown in Figure 30. Since the impedance of the line filter

inductor at line frequency is negligible compared to the

impedance of the capacitors, the line frequency behavior of

the line filter stage can be modeled, as shown in Figure 30.

Even though the bypass capacitors absorb switching ripple

current, they also generate circulating capacitor current,

which leads the line voltage by 90^o, as shown in Figure 31.

The circulating current through the capacitor is added to the

load current and generates displacement between line

voltage and current.

2.5V

2.5

R_FB2

=

R_FB1

=

11.7×10⁶= 68kꢂ

V_OUT− 2.5V

430− 2.5

Choosing the crossover frequency (control bandwidth) at

15Hz, C_COMP,LFis obtained as:

K_SAW

2⋅V_OUT²⋅ L ⋅C_OUT

(

V_LINE

)

²2.5⋅115

ꢁ

mho

C_COMP

≅

,

LF

2

(

2

π

f_C

)

6

2

6

8.496 ×10⁻

2⋅430²⋅199 ×10⁻⁶⋅240 ×10⁻

(

230

)

2.5⋅115×10⁻

=

= 823nF

2

6

(

2π

15

)

Actual C_COMP,LFis determined as 1000nF since it is the

closest value among the offꢀtheꢀshelf capacitors. R_COMPis

obtained as:

The displacement angle is given by:

2









1

η⋅

(

V_LINE

)

⋅2π⋅ f_LINE⋅C_EQ

θ =tan⁻¹

R_COMP

=

=12.8kꢂ

(44)









2π

⋅ f_C⋅C_COMP,LF

2π

⋅15⋅823×10⁻⁹

P

OUT

Selecting the highꢀfrequency pole as 150Hz, C_COMP,HFis

obtained as:

where C_EQis the equivalent capacitance that appears across

the AC line (C_EQ=C_F1+C_F2+C_HF).

1

The resultant displacement factor is:

C_COMP,HF

=

= 82nF

2π

⋅ f_CP⋅ R_COMP

2π

⋅150⋅12.8×10³

( )

DF=cosθ

(45)

These components result in a control loop with a bandwidth

of 19.5Hz and phase margin of 45.6°. The actual bandwidth is

a little larger than the asymptotic design.

Since the displacement factor is related to power factor, the

capacitors in the line filter stage should be selected

carefully. With a given minimum displacement factor

(DF_MIN) at fullꢀload condition, the allowable effective input

capacitance is obtained as:

P

cos⁻¹

(

DF_MN

)

[F]

OUT

C_EA

<

⋅tan

(

2

η⋅

(

V_LINE

)

⋅2π⋅ f_LINE

(46)

One way to determine if the input capacitor is too high or

PFC control routine has problems is to check Power Factor

(PF) and Total Harmonic Distortion (THD). PF is the degree

to which input energy is effectively transferred to the load

by the multiplication of displacement factor and THD that is

input current shape deterioration ratio. PFC control loop

rarely has no relation to displacement factor and input

capacitor rarely has no impact on the input current shape. If

PF is low (high is preferable), but THD is quite good (low is

preferable), it can be concluded that input capacitance is too

high and PFC controller is fine.

(Design Example) Assuming the minimum displacement

factor at full load is 0.98, the equivalent input capacitance is

obtained as:

P

1

OUT

C_EA

<

⋅tan

(

cos⁻

(

DF_MN

)

2

η⋅

(

V_LINE

)

⋅2 π⋅ f_LINE

200

1

<

⋅tan

(

cos⁻

(0

.

98

))

=

1.6

ꢁF

2

0

.

9

⋅

(277

)

⋅2 π⋅50

Thus, the sum of the capacitors on the input side should be

smaller than 2.0ꢁF.

Rev. 1.0.0 • 4/20/11

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15

ANꢀ9738

APPLICATION NOTE

[STEP-10] Define System Specifications

Estimated Efficiency (E_ff): The power conversion

efficiency must be estimated to calculate the maximum

input power with a given maximum output power. If no

reference data is available, use E_ff= 0.88~0.92 for lowꢀ

voltage output applications and E_ff= 0.92~0.96 for highꢀ

voltage output applications. With the estimated efficiency,

the maximum input power is given as:

P

o

P =

(47)

in

E_ff

min

Input Voltage Range (V_in

and V_in^max): The maximum

input voltage would be the nominal PFC output voltage as:

max

V_in

= V_O.PFC

(48)

Even though the input voltage is regulated as constant by

PFC preꢀregulator, it drops during the holdꢀup time. The

minimum input voltage considering the holdꢀup time

requirement is given as:

Figure 30. Equivalent Circuit of Line Filter Stage

2P T_HU

min

2

in

V

= V_O.PFC−

(49)

in

C_DL

where V_O.PFCis the nominal PFC output voltage, T_HUis a

holdꢀup time, and C_DLis the DC link bulk capacitor.

(Design Example) Assuming the efficiency is 92%,

P

150

o

P =

=

= 163W

in

E_ff0.92

2P T_HU

min

2

in

V_in= V_O.PFC

−

C_DL

2⋅163⋅30×10⁻³

240×10⁻⁶

= 430²−

= 379V

[STEP-11] Determine Maximum and Minimum

Voltage Gains of the Resonant Network

As discussed in the previous section, it is typical to operate

the LLC resonant converter around the resonant frequency

(f_o) to minimize switching frequency variation. Since the

input of the LLC resonant converter is supplied from PFC

output voltage, the converter should be designed to operate

at f_ofor the nominal PFC output voltage.

θ

Figure 31. Line Current Displacement

3.2 LLC SRC Section

In this section, a design procedure is presented using the

schematic in Figure 1 as a reference. An integrated

transformer with center tap, secondary side is used and input

is supplied from Power Factor Correction (PFC) preꢀ

regulator. A DCꢀDC converter with 150W/103V output is

selected as a design example. The design specifications are:

As observed in Equation (9), the gain at f_ois a function of m

(m=L_p/L_r). The gain at f_ois determined by choosing that

value of m. While a higher peak gain can be obtained with a

small m value, too small m value results in poor coupling of

the transformer and deteriorates the efficiency. It is typical

to set m to be 3~7, which results in a voltage gain of 1.1~1.2

at the resonant frequency (f_o).

ꢀ

Nominal input voltage: 400V_DC(output of PFC stage)

Output: 103V/1.46A (150W)

Holdꢀup time requirement: 30ms (50Hz line freq.)

DC link capacitor of PFC output: 240ꢁF

With the chosen m value, the voltage gain for the nominal

PFC output voltage is obtained as:

Rev. 1.0.0 • 4/20/11

www.fairchildsemi.com

16

ANꢀ9738

APPLICATION NOTE

8

n²V_o²

m

M ^min

=

(53)

R_ac=

(50)

π ²

P

o

m −1

@f=f_o

(Design Example)

8n²(V_o+V_F)²8⋅1.93²⋅103.9²

which would be the minimum gain because the nominal

PFC output voltage is the maximum input voltage (V_in^max).

R_ac

=

= 217ꢂ

π ²

P

π ²⋅150

o

The maximum voltage gain is given as:

[STEP-14] Design the Resonant Network

max

V

M ^max

=

M ^min

in

(51)

min

With the m value chosen in STEPꢀ11, read the proper Q

value from the peak gain curves in Figure 33 that allows

enough peak gain. Considering the load transient and stable

zeroꢀvoltageꢀswitching (ZVS) operation, 10~20% margin

should be introduced on the maximum gain when

determining the peak gain. Once the Q value is determined,

the resonant parameters are obtained as:

V

in

(Design Example) The ratio (m) between L_pand L_ris

chosen as 5. The minimum and maximum gains are

obtained as:

V

m

5

min

RO

M

=

=1.12

max

1

m −1

5−1

V

in

C_r=

(54)

2

2πQ⋅ f_o⋅ R_ac

max

min

V_in

400

M ^max

=

m^min

=

⋅1.12 = 1.31

341

1

L_r=

(55)

(2π

f_o)²C_r

Gain (M)

Peak Gain

(Available Maximum Gain)

L_p= m ⋅ L_r

(56)

1.31

min

M^max

for V_IN

(Design Example)

As calculated in STEPꢀ11, the maximum voltage gain

^max) for the minimum input voltage (V_in^min) is 1.31. With

15% margin, a peak gain of 1.51 is required. has been

chosen as 5 in STEPꢀ11 and is obtained as 0.38 from the

for

V_IN

( V_O.PFC

max

(

M

1.12

M^min

m

)

Q

peak gain curves in Figure 33. By selecting the resonant

frequency as 100kHz, the resonant components are

determined as:

m

M =

= 1.12

m −1

1

f_s

C

=

=19 nF

r

f_o

3

2

πQ ⋅ f ⋅ R

2

π ⋅

0.38

⋅

100

×

10

⋅

217

o

ac

Figure 32. Maximum Gain / Minimum Gain

1

L_r=

=

=133 ꢁH

9

2

(

2

πf_o)²C_r

(

2

π×100

×

10 ³

)

⋅19

×

10 ⁻

[STEP-12] Determine the Transformer Turns

Ratio (n=N_p/N_s)

L_p= m⋅ L_r= 665 ꢁH

With the minimum gain (M^min) obtained in STEPꢀ11, the

transformer turns ratio is given as:

max

N_p

V

n =

=

⋅ M ^min

in

(52)

N_s2(V_o+V_F

)

where V_Fis the secondaryꢀside rectifier diode voltage drop.

(Design Example) assuming V_Fis 0.9V:

max

N_p

V_in

430

n =

=

⋅ M_min

=

⋅1.12 = 2.06

N_s2(V_O+V_F)

2(103+ 0.9)

[STEP-13] Calculate Equivalent Load

Resistance

Figure 33. Resonant Network Design Using the

Peak Gain (Attainable Maximum Gain) Curve for m=5

With the transformer turns ratio obtained from Equation

(52), the equivalent load resistance is obtained as:

Rev. 1.0.0 • 4/20/11

www.fairchildsemi.com

17

ANꢀ9738

APPLICATION NOTE

[STEP-15] Design the Transformer

The worst case for the transformer design is the minimum

switching frequency condition, which occurs at the

minimum input voltage and fullꢀload condition. To obtain

the minimum switching frequency, plot the gain curve using

gain Equation (8) and read the minimum switching

frequency. The minimum number of turns for the

transformer primaryꢀside is obtained as:

n(V_o+V_F)

min

N_p

=

(57)

2 f_s^min⋅ M_V⋅ꢀB ⋅ A

e

where A_eis the crossꢀsectional area of the transformer

core in m²and ꢀB is the maximum flux density swing in

Tesla, as shown in Figure 34. If there is no reference data,

use ꢀB =0.3~0.4 T.

n (V_o+V_F)/M_V

Figure 35. Gain Curve

V_RI

1/(2f_s)

[STEP-16] Transformer Construction

ꢀn (V_o+V_F)/M_V

Parameters L_pand L_rof the transformer were determined in

STEPꢀ14. L_pand L_rcan be measured in the primary side

with the secondaryꢀside winding open circuited and short

circuited, respectively. Since LLC converter design requires

a relatively large L_r, a sectional bobbin is typically used, as

shown in Figure 36, to obtain the desired L_rvalue. For a

sectional bobbin, the number of turns and winding

configuration are the major factors determining the value of

L_r, while the gap length of the core does not affect L_rmuch.

L_pcan be controlled by adjusting the gap length. Table 1.

shows measured L_pand L_rvalues with different gap lengths.

A gap length of 0.05mm obtains values for L_pand L_rclosest

to the designed parameters.

ꢀB

B

Figure 34. Flux Density Swing

Choose the proper number of turns for the secondary side

that results in primaryꢀside turns larger than N_p^minas:

min

N_p= n⋅ N_s> N_p

(58)

N p

(Design Example) EER3542 core (A_e=107mm²) is selected

for the transformer. From the gain curve of Figure 35, the

minimum switching frequency is obtained as 82KHz. The

minimum primaryꢀside turns of the transformer is given as:

N _s2

N _s1

n(V_o+V_F)

min

N_p

=

2 f_s^minꢀB⋅1.11⋅ A_e

1.93×103.9

=

= 26turns

2×82×10³⋅0.4⋅1.11⋅107×10⁻⁶

min

Figure 36. Sectional Bobbin

Choose N_sso that the resultant N_pis larger than N_p

:

min

N _p= n ⋅ N_s=1.93×14 = 27 < N _p

Table 1. Measured L_pand L_rwith Different Gap

Lengths

min

N _p= n ⋅ N_s=1.93×15 = 29 < N _p

Gap Length

L_p

L_r

min

N _p= n ⋅ N_s=1.93×16 = 31> N _p

0.0mm

0.05mm

0.10mm

0.15mm

0.20mm

0.25mm

2,295ꢁH

943ꢁH

630ꢁH

488ꢁH

419ꢁH

366ꢁH

123ꢁH

122ꢁH

min

N _p= n ⋅ N_s=1.93×17 = 33 > N _p

min

N _p= n ⋅ N_s=1.93×18 = 35 > N _p

118ꢁH

min

N _p= n ⋅ N_s=1.93×19 = 37 > N _p

117ꢁH

115ꢁH

114ꢁH

Rev. 1.0.0 • 4/20/11

www.fairchildsemi.com

18

ANꢀ9738

APPLICATION NOTE

The nominal voltage of the resonant capacitor in normal

operation is given as:

(Design Example)

Final Resonant Network Design

max

RMS

V

2 ⋅ I_Cr

2⋅π ⋅ f_o⋅C_r

nom

in

Even though the integrated transformer approach in LLC

resonant converter design can implement the magnetic

components in a single core and save one magnetic

component, the value of L_ris not easy to control in real

transformer design. Resonant network design sometimes

requires iteration with a resultant L_rvalue after the

transformer is built. The resonant capacitor value is also

changed since it should be selected among offꢀtheꢀshelf

capacitors. The final resonant network design is summarized

in Table 2. and the new gain curves are shown in Figure 37.

V_C

≅

+

(60)

r

2

However, the resonant capacitor voltage increases higher

than this at overload condition or load transient. Actual

capacitor selection should be based on the OverꢀCurrent

Protection (OCP) trip point. With the OCP current, I_OCP, the

maximum resonant capacitor voltage is obtained as:

max

V

I_OCP

2⋅π ⋅ f_o⋅C_r

nom

in

V_C

≅

+

(61)

r

2

Table 2. Final Resonant Network Design Parameters

Parameters

Initial Design

Final Design

(Design Example)

L_p

L_r

665µH

133H

19nF

100kHz

5

691µH

122µH

22nF

96kHz

5

π

I_O

n(V_o+V_F)

4 2 f_oM_v(L_p− L_r)

1

RMS

2

I_C

≅

[

]²+[

]

r

E_ff

2 2n

C_r

1

π

⋅

1.4

1.93(103

3

+

0.9)

500

2

f_o

=

[

]

+

[

]

−

×10

6

0.92

2 2 ⋅1.93

4 2

⋅

96

×

10

⋅

1.12

⋅

m

=1.12A

Q

0.38

0.3

M at f_o

1.12

The peak current in the primary side in normal operation is:

peak

rms

Minimum

Frequency

I_C

= 2 ⋅ I_C

=1.58A

75kHz

74.4kHz

r

peak

OCP level is set to 2.5A with 50% margin on I_Cr

:

RMS

max

2

⋅ I_C

r

V_in

nom

V_C

≅

+

r

2

2 ⋅π ⋅ f_o⋅C_r

430

2

2 ⋅1.18

=

+

= 340V

2⋅

π

⋅96×10³⋅22×10⁻⁹

max

V_in

I_OCP

π ⋅ f_o⋅C_r

max

V_C

≅

+

r

2

2⋅

2.5

π

⋅96×10³⋅22×10⁻⁹

430

2

=

+

= 403.3V

2⋅

A 630V rated lowꢀESR film capacitor is selected for the

resonant capacitor.

[STEP-18] Rectifier Network Design

When the center tap winding is used in the transformer

secondary side, the diode voltage stress is twice of the

output voltage expressed as:

Figure 37. Gain Curve of the Final Resonant

Network Design

[STEP-17] Select the Resonant Capacitor

V_D= 2(V_o+ V_F)

(62)

When choosing the resonant capacitor, the current rating

should be considered because a considerable amount of

current flows through the capacitor. The RMS current

through the resonant capacitor is given as:

The RMS value of the current flowing through each rectifier

diode is given as:

π

4

RMS

I_D

=

I_o

(63)

1

π

2 2n

I_o

n(V_o+V_F)

4 2 f_oM_V(L_p− L_r)

RMS

2

I_C

≅

[

]²+[

]

(59)

r

E_ff

Rev. 1.0.0 • 4/20/11

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19

ANꢀ9738

APPLICATION NOTE

Meanwhile, the ripple current flowing through output

capacitor is given as:

π

2 2

I_o

π

²−8

8

RMS

2

I_Co

= (

)²− I_o

=

I_o

(64)

The voltage ripple of the output capacitor is:

π

2

ꢀV_o= I_o⋅ R_C

(65)

where R_Cis the effective series resistance (ESR) of the

output capacitor and the power dissipation is the output

capacitor is:

P

= (I_Co^RMS)²⋅ R_C

(66)

Loss.Co

(Design Example) The voltage stress and current stress of

the rectifier diode are:

Figure 38. Typical Circuit Configuration for RT Pin

Softꢀstart prevents excessive inrush current and overshoot of

output voltage during startup, increases the voltage gain of

the resonant converter progressively. Since the voltage gain

of the resonant converter is reversely proportional to the

switching frequency, softꢀstart is implemented by sweeping

down the switching frequency from an initial high

frequency (f ^ISS) until the output voltage is established, as

illustrated in Figure 39. The softꢀstart circuit is made by

connecting RC series network on the RT pin as shown in

Figure 38. FAN7621S also has an internal softꢀstart for 3ms

to reduce the current overshoot during the initial cycles,

which adds 40KHz to the initial frequency of the external

softꢀstart circuit, as shown in Figure 39. The actual initial

frequency of the softꢀstart is given as:

V_D= 2(V_o+V_F) = 2(103+0.9) = 207.8V

π

4

RMS

I_D

=

I_o=1.14A

The 600V/8A ultraꢀfast recovery diode is selected for the

rectifier, considering the voltage overshoot caused by the

stray inductance.

The RMS current of the output capacitor is:

π

²−8

8

π

I_o

RMS

2

I_C

=

(

)²− I_o

=

I_o= 0.584A

o

2 2

When two electrolytic capacitors with ESR of 100mꢂ are

used in parallel, the output voltage ripple is given as:

π

2

π

2

0.1

ꢀV_o= I_o⋅R_C= ⋅1.46⋅( ) = 0.114V

2

5.2kꢂ 5.2kꢂ

f ^ISS= (

+

)×100+ 40 (kHz)

The loss in electrolytic capacitors is:

(69)

P

= (I_C^RMS)²⋅R_C= 0.584²⋅0.05 = 0.017W

R_min

R_SS

Loss,C_o

o

It is typical to set the initial frequency of softꢀstart (f ^ISS) at

2~3 times of the resonant frequency (f_o).

The softꢀstart time is determined by the RC time constant:

[STEP-19] Control Circuit Configuration

t_SS

= 3 ~ 4( R_SS• C_SS)

(70)

Figure 38 shows the typical circuit configuration for the RT

pin of FAN7621S, where the optoꢀcoupler transistor is

connected to the RT pin to control the switching frequency.

The minimum switching frequency occurs when the optoꢀ

coupler transistor is fully tuned off, which is given as:

5.2kꢂ

R_min

f_min

=

×100(kHz)

(67)

Assuming the saturation voltage of optoꢀcoupler transistor is

0.2V, the maximum switching frequency is determined as:

5.2kꢂ 4.68kꢂ

f_max= (

+

)×100(kHz)

(68)

R_min

R_max

Figure 39. Frequency Sweep of the Soft-Start

Rev. 1.0.0 • 4/20/11

www.fairchildsemi.com

20

ANꢀ9738

APPLICATION NOTE

(Design Example) The minimum frequency is 75kHz in

(Design Example) Since the OCP level is determined as

STEPꢀ15. R_minis determined as:

2.5A in STEPꢀ17 and the OCP threshold voltage is ꢀ0.6V, a

sensing resistor of 0.24

set to 100ns (1/100 of switching period) with 1k

and 100pF capacitor.

ꢂ is used. The RC time constant is

100KHz

R_min

=

× 5.2Kꢂ = 6.93Kꢂ

ꢂ resistor

f_min

Considering the output voltage overshoot during transient

(10%) and the controllability of the feedback loop, the

maximum frequency is set as 140kHz. R_maxis determined as:

[STEP-21] Voltage and Current Feedback

Power supplies for LED lighting must be controlled by

Constant Current (CC) Mode as well as a Constant Voltage

(CV) Mode. Because the forwardꢀvoltage drop of LED

varies with the junction temperature and the current also

increases greatly consequently, devices can be damaged.

4.68Kꢂ

R_max

=

f_o×1.40

100KHz

5.2Kꢂ

R_min

(

−

)

4.68Kꢂ

96KHz ×1.40 5.2Kꢂ

=

= 7.88Kꢂ

(

−

)

Figure 42 shows an example of a CC and CV Mode

feedback circuit for singleꢀoutput LED power supply.

During normal operation, CC Mode is dominant and the CV

control circuit does not activate as long as the feedback

voltage is lower than reference voltage, which means that

CV control circuit only acts as OVP for abnormal modes.

100KHz

6.93Kꢂ

Setting the initial frequency of softꢀstart as 250kHz (2.5

times of the resonant frequency), the softꢀstart resistor R_SSis

given as:

5.2Kꢂ

R_SS

=

f_ISS− 40KHz

100KHz

5.2Kꢂ

R_min

(

−

)

(Design Example) The output voltage (V_O) is 103V in

design target. V_Ois determined as:

5.2Kꢂ

=

= 3.85Kꢂ

250KHz − 40KHz 5.2Kꢂ

R_FU

(

−

)

V_o= 2.5(1+

)

100KHz

6.93Kꢂ

R_FL

Set the upperꢀside feedback resistance (R_FU) as 330K

is determined as:

ꢂ. R_FL

[STEP-20] Current Sensing and Protection

FAN7621S senses lowꢀside MOSFET drain current as a

negative voltage, as shown in Figure 40. and Figure 41.

Halfꢀwave sensing allows low power dissipation in the

sensing resistor, while fullꢀwave sensing has less switching

noise in the sensing signal. Typically, an RC lowꢀpass filter

is used to filter out the switching noise in the sensing signal.

The RC time constant of the lowꢀpass filter should be

1/100~1/20 of the switching period.

2.5× R_FU2.5×330Kꢂ

R_FL

=

= 8.2Kꢂ

(V_o− 2.5)

(103 − 2.5)

The output current (I_LED) is 1.46A in design target.

Assuming the sensing resistor (R_SENSE) of 0.1 and

ꢂ

feedback resistor (R202) of 47K

resistor R203 is determined as:

ꢂ

are used, the input

V_SENSE× R202

(

R_SENSE× I_LED)× R202

R

203

=

0.36

(0.1×1.46)×47Kꢂ

=

=19Kꢂ

0.36

Figure 40. Half-Wave Sensing

Figure 42. Example of CC and CV Feedback Circuit

Figure 41. Full-Wave Sensing

Rev. 1.0.0 • 4/20/11

www.fairchildsemi.com

21

ANꢀ9738

APPLICATION NOTE

4. Schematic of the Evaluation Board

G P . 6 1

G S . 0 1

FAN7621S

c c V L . 2 1

1

3

2

1

3

5

4

0 1

8

9

7

6

1

2

CS19

220nF

RS33

47k

J6

4

VLED

ISENSE

VAUX

VFB

1

2

3

4

5

6

7

8

Vꢀ

LM358/ON

2

ꢀ

1

OUT

8

RS35

13k

3

+

V+

U6A

9

10

11

12

DS2

LL4148

RS42

RS44

R46

0.1

CS6

33uF/25V

RS40

100k

RS41

4.7k

RS49

1k

N.C

CON12

U7

TL431

RS55

120k

DS3

LL4148

RS57

330k

CS25

220nF

RS56

47k

4

Vꢀ

LM358/ON

6

ꢀ

7

OUT

5

+

8

V+

U6B

RS59

8.2k

VAUX

Figure 43. Evaluation Board Schematic

Rev. 1.0.0 • 4/20/11

www.fairchildsemi.com

22

ANꢀ9738

APPLICATION NOTE

Dimensions: 240 (W) × 80 (H) [mm]

Figure 44. Top View of Evaluation Board

Figure 45. Bottom View of Evaluation Board

5. Bill of Materials

Item No.

Qty

Reference

Part Reference

Description (Manufacturer)

1

2

1

5

3

1

2

1

2

1

6

2

BD1

600V/8A

3PIN

Bridge Diode (Fairchild Semiconductor)

Connector

CN1

3

CP1

630V22nF

33µF/25V

120µF/450V

680p/25V

0.1µF/25V

1µF/25V

Film Capacitor

4

CP2,CP6,CP13,CP21

SMD Tantal Capacitor

Electrolytic Capacitor

SMD Capacitor 2012

Electrolytic Capacitor

SMD Capacitor 2012

Film Capacitor

5

CP4,CP5,CP8

6

CP7

7

CP9

CP10,CP14

CP11

8

9

470pF/25V

33µF/25V

10µF/16V

12nF/25V

100pF/26V

0.68µF/630V

100p/25V

47µF/200V

470nF/400V

220nF/25V

10

11

12

13

14

15

16

17

CP15,CP16

CP17

CP18

CP19

CP20

CP22

SMD Capacitor 2012

Electrolytic Capacitor

Film Capacitor

CS1,CS2,CS5,CS6,CS7,CS8

CS3,CS4

CS19,CS25

SMD Capacitor 2012

Rev. 1.0.0 • 4/20/11

www.fairchildsemi.com

23

ANꢀ9738

APPLICATION NOTE

Item No.

Qty

Reference

Part Reference

Description (Manufacturer)

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

2

3

1

4

5

2

1

2

1

2

1

2

1

3

4

1

5

6

1

2

5

CS9,CS10

220p/400V

220nF/400V

100nF/50V

4.7µF/400V

600V/8A

Ceramic Capacitor

Film Capacitor

CS11

C1

SMD Capacitor 3216

Ceramic Capacitor

Hyperfast2 Diode

Fast Rectifier Diode

SMD General Purpose Diode

UltraꢀFast Diode

Fuse

C2

DP1

DS1,DP2,DP3,DP5

1000V/1A

100V/200mA

600V/20A

FS101

DS2,DS3,DP4,DP6,DP7

D1,D2

F1

J1,J6

12PIN

Connector

J2

LF1,LF2

2PIN

Connector

10mH/2.3A

650V/11A

600V/7A

CommonꢀMode Filter

MOSFET

M1

M2,M3

MOSFET

PC1

Photo Copuler

40V/1A

Photo Coupler

Q1,Q3,Q4

Q2,U3,U4,U5

RP1

SMD NPN Transitor

SMD PNP Transitor

SMD Resistor 2012

SMD Resistor 3216

Watt Resistor

40V/200mA

390kꢂ/25V

1M/ꢂ50V

4.3Mꢂ/50V

68Kꢂ/2W

0ꢂ/50V

RS1,RS2,RP2,RS3,RP9

RP3,RP4,RP13,RP14,RP20,RP21

RP5

RP6,RP7

RP8,RP11

RP30,RP32,RP36

RP10,RP26

RP12

SMD Resistor 3216

SMD Resistor 2012

SMD Resistor 3216

SMD Resistor 2012

SMD Resistor 3216

SMD Resistor 2012

SMD Resistor 3216

SMD Resistor 2012

SMD Resistor 3216

Watt Resistor

10kꢂ/25V

10kꢂ/50V

33kꢂ/25V

24kꢂ/50V

47kꢂ/25V

2.7ꢂ/25V

10ꢂ/50V

41

42

43

44

45

2

1

3

1

4

RP15,RS33,RS56

RP16

RP17,RP19

RP22,RP34

RP18

10ꢂ/25V

46

47

48

49

50

51

52

53

54

55

56

57

58

59

1

2

1

2

1

2

1

4.7ꢂ/25V

10kꢂ/25V

8.2kꢂ/25V

1.8Kꢂ/25V

5.1kꢂ/25V

3ꢂ/25V

RP23

RP24,RS59

RP25

RP27

RP28,RP35

RP29,RP31

RP33

75kꢂ/50V

0.1ꢂ/5W

RP37,RS49

RP38A

1kꢂ/50V

SMD Resistor 3216

Watt Resistor

0.1ꢂ/1W

RS35

13kꢂ/25V

100kꢂ/25V

4.7kꢂ/25V

0.1ꢂ/2W

SMD Resistor 2012

SMD Resistor 2013

Watt Resistor

RS40

RS41

RS42

Rev. 1.0.0 • 4/20/11

www.fairchildsemi.com

24

ANꢀ9738

APPLICATION NOTE

Item No.

Qty

Reference

Part Reference

Description (Manufacturer)

60

61

62

63

64

65

66

67

68

69

70

71

2

1

2

1

RS44,R46

RS55

RS57

TM1

NC

120kꢂ/25V

330kꢂ/25V

EER3019Nꢀ10

EER3543ꢀ16

FL7930B

SMD Resistor 2012

PFC Inductor

TM2

LLC Transformer

CRM PFC Controller

LLC Resonant Controller

OPꢀAMP

U1

U2

FAN7621S

LM358

U6

U7

KA431

Shunt Regulator

Zener Diode 18V

Zener Diode 6.8V

Varistor 470V

ZDP1,ZDP3

ZDP2

ZNR1

MMSZ5248

MMSZ5235

10D471

Related Datasheets

FL7930B — SingleꢀStage Flyback and Boundary Mode PFC Controller for Lighting

FAN7621S — Controller for Resonant Half Bridge

FDPF17N60NT — 600V NꢀChannel MOSFET, UniFET™2

FDPF7N60NZ — 600V NꢀChannel MOSFET, UniFET™2

Author

WonSeok, Kang

Power Conversion Korea

Senior System and Application Engineer

Wonseok.kang@fairchildsemi.com

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS

PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which,

(a) are intended for surgical implant into the body, or (b)

support or sustain life, or (c) whose failure to perform when

properly used in accordance with instructions for use provided

in the labeling, can be reasonably expected to result in

significant injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

Rev. 1.0.0 • 4/20/11

www.fairchildsemi.com

25


型号：	AN-9738
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Design Guideline on 150W Power Supply for LED Street Lighting Design Using FL7930B and FAN7621S 对150W电源设计指南LED路灯设计中的应用FL7930B和FAN7621S
文件：	总25页 (文件大小：1186K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AN-9738 [FAIRCHILD]

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