AN-9735_技术文档

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AN-9735

Design Guideline for LED Lamp Control Using Primary-

Side Regulated Flyback Converter, FAN103 & FSEZ1317

design without incurring tremendous costs. Fairchild

Semiconductor PWM PSR controller FAN103 and Fairchild

Introduction

Many LED lamp systems use the flyback converter

topology. In applications where precise output current

regulation is required, current sensing in the secondary side

is always necessary, which results in additional sensing loss.

For power supply designers struggling to meet increasing

regulatory pressures, the output current sensing is a daunting

design challenge.

Power Switch (FPS™) (MOSFET + Controller, EZ-PSR)

FSEZ1317 significantly simplify meeting tighter efficiency

requirements with fewer external components.

This application note presents design considerations for

LED lamp systems employing Fairchild Semiconductor

components. It includes designing the transformer and

output filter, selecting the components, and implementing

constant-current control. The step-by-step procedure

completes a power supply design. The design is verified

through an experimental prototype converter using

FSEZ1317. Figure 1 shows the typical application circuit

for an LED lamp using FSEZ1317.

Primary-Side Regulation (PSR) for power supplies can be

an optimal solution for compliance and cost in LED lamp

systems. Primary-side regulation controls the output voltage

and current precisely with information in the primary side of

the LED lamp controller only. This removes the output

current sensing loss and eliminates all secondary-feedback

circuitry. This facilitates a higher efficiency power supply

Figure 1. Typical Application Circuit

Rev. 1.0.0 • 4/12/11

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AN-9735

APPLICATION NOTE

current (I_F) decreases linearly from the peak value to zero.

At the end of t_DIS, all the energy stored in the inductor has

been delivered to the output.

Operation Principle of Primary-Side

Regulation

Stage III

Figure 2 shows typical waveforms of a flyback converter.

Generally, Discontinuous Conduction Mode (DCM)

operation is preferred for primary-side regulation since it

allows better output regulation. The key of primary-side

regulation is how to obtain output voltage and current

information without directly sensing them. Once these

values are obtained, the control can be accomplished by the

conventional feedback compensation method.

When the diode current reaches zero, the transformer

auxiliary winding voltage (V_A) begins to oscillate by the

resonance between the primary-side inductor (L_m) and the

output capacitor of MOSFET.

Design Procedure

In this section, a design procedure is presented using the

schematic in Figure 3 as a reference.

Stage III Stage I

Stage I

I_PK

Stage II

I_DS

N

P

I



PK

N

S

I_O= I_{F_AVG}

I_F

Figure 3. CV & CC Operation Area

N _A

V_F



N _S

[STEP-1] Estimate the Efficiencies

N _A

N _S

Figure 3 shows the CV & CC operation area. To optimize

the power stage design, the efficiencies and input powers

should be specified for operating point A (nominal output

voltage and current), B (70% of nominal output voltage),

and C (minimum output voltage).

V_O



V_A

1. Estimated overall efficiency (η) for operating points

A, B, and C: The overall power conversion efficiency

should be estimated to calculate the input power. If

no reference data is available, set η = 0.7 ~ 0.75 for

low-voltage output applications and η = 0.8 ~ 0.85

for high-voltage output applications.

t_DIS

t_S

t_ON

Figure 2. Key Waveforms of PSR Flyback Converter

2. Estimated primary-side efficiency (η_P) and

secondary-side efficiency (η_S) for operating points A,

B, and C. Figure 4 shows the definition of primary-

side and secondary-side efficiencies, where the

primary-side efficiency is for the power transfer from

AC line input to the transformer primary side, while

the secondary-side efficiency is for the power transfer

from the transformer primary side to the power

supply output.

The operation principles of DCM flyback converter are:

Stage I

During the MOSFET ON time (t_ON), input voltage (V_DL) is

applied across the primary-side inductor (L_m). Then

MOSFET current (I_DS) increases linearly from zero to the

peak value (I_PK). During this time, the energy is drawn from

the input and stored in the inductor.

Stage II

The typical values for the primary-side and secondary-side

efficiencies are given as:

When the MOSFET is turned off, the energy stored in the

inductor forces the rectifier diode (D_F) to be turned on.

During the diode conduction time (t_DIS), the output voltage

(V_O), together with diode forward-voltage drop (V_F), are

applied across the secondary-side inductor and the diode

1

2

(1)

_P ³,_S ³;V_O10V

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AN-9735

APPLICATION NOTE

2

1

The secondary-side efficiency at 70% of nominal output

voltage (operating point B) can be approximated as:

(2)

_P ³,_S ³;V_O10V

N

0.7V_O

V_OV_F

_{S @ B}_S



(6)

N

0.7V_OV_F

V_O

Then, the power supply input power and transformer input

power at 70% nominal output voltage (operating point B)

are given as:

N

0.7V_O^N I_O

P



(7)

(8)

IN @B

_@B

0.7V_O^N I_O

N

P



IN _T @B

_{S @B}

The overall efficiency at the minimum output voltage

(operating point C) can be approximated as:

Figure 4. Primary- and Secondary-Side Efficiency

With the estimated overall efficiency, the input power at

nominal output is given as:

min

N

V_O

V_O^minV_F

V_OV_F

_@C 



(9)

N

V_O^N I_O

V_O

(3)

P 

where, Vo^minis the minimum output voltage.

IN



N

The secondary-side efficiency at minimum output voltage

(operating point C) can be approximated as:

where V_Oand I_Oare the nominal output voltage and

current, respectively.

min

N

The input power of transformer at nominal output is given

as:

V_O

V_O^minV_F

V_OV_F

_@C_S



(10)

N

V_O

N

V_O^N I_O

(4)

Then, the power supply input power and transformer input

power at the minimum output voltage (operating point C)

are given as:

P



IN _T

_S

When the output voltage drops below 70% of its nominal

value, the frequency is reduced to 33kHz to prevent CCM

operation. Thus, the transformer should be designed for

DCM both at 70% of nominal output voltage and minimum

output voltage.

N

V_O^min I_O

P



(11)

(12)

IN @C

_@C

V_O^min I_O

N

As output voltage reduces in CC Mode, the efficiency also

drops. To optimize the transformer design, it is necessary to

estimate the efficiencies properly at 70% of nominal output

voltage and minimum output voltage conditions.

P



IN _T @B

_{S @C}

[STEP-2] Determine the DC Link Capacitor

(C_DL) and the DC Link Voltage Range

The overall efficiency at 70% of nominal output voltage

(operating point B) can be approximated as:

It is typical to select the DC link capacitor as 2-3µF per watt

of input power for universal input range (90 ~ 265V_RMS) and

1µF per watt of input power for European input range (195

~ 265V_RMS). With the DC link capacitor chosen, the

minimum DC link voltage is obtained as:

N

0.7V_O

V_OV_F

_{@ B} 



(5)

N

0.7V_OV_F

V_O

where V_Fis diode forward-voltage drop.

P (1 D_ch)

C_DL f_L

min

V_DL 2(V_LINE)²

IN

(13)

min

where V_LINEis the minimum line voltage, C_DLis the

DC link capacitor, f_Lis the line frequency, and D_chis the

DC link capacitor charging duty ratio defined as shown in

Figure 5, which is typically about 0.2.

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AN-9735

APPLICATION NOTE

voltage should be also considered. The maximum voltage

stress of MOSFET is given as:

max

V_DSV_DL^maxV_ROV_OS

(20)

T₁

T₂

D_ch



For reasonable snubber design, voltage overshoot (V_OS) is

typically 1~1.5 times the reflected output voltage. It is also

typical to have a margin of 15~20% of breakdown voltage

for maximum MOSFET voltage stress.

Figure 5. DC Link Voltage Waveforms

The maximum DC link voltage is given as:

max

(14)

V_DL 2 V_LINE

where V_LINE^maxis the maximum line voltage.

N_P

(V_OV_F) 

N_S

The minimum input DC link voltage at 70% nominal output

voltage are given as:

P

_@B(1 D_ch)

C_DL f_L

IN

min

V_DL@B 2(V_LINE)²

(15)

The minimum input DC link voltage at minimum output

voltage are given as:

Figure 6. Voltage Stress of MOSFET

The transformer turns ratio between the auxiliary winding

and secondary winding (N_A/N_S) should be determined by

considering the permissible IC supply voltage (V_DD) range

and minimum output voltage in constant current. When the

LED operates in constant current, V_DDis changed, together

with the output voltage, as seen Figure 7. The overshoot of

auxiliary winding voltage caused by the leakage inductance

also affects the V_DD. V_DDvoltage at light-load condition,

where the overshoot of auxiliary winding voltage is

negligible, is given as:

P

_@C(1 D_ch)

C_DL f_L

IN

min

V_DL@C 2(V_LINE)²

(16)

[STEP-3] Determine the Transformer Turns

Ratio

Figure 6 shows the MOSFET drain-to-source voltage

waveforms. When the MOSFET is turned off, the sum of

the input voltage (V_DL) and the output voltage reflected to

the primary is imposed across the MOSFET as:

N_A

VDD^min1







V_OV_FV_FA



nom

max

(21)

(17)

V_DS

 V_DLV_RO

N_S

The actual V_DDvoltage at heavy load is higher than

Equation (21) due to the overshoot by the leakage

inductance, which is proportional to the voltage overshoot

of MOSFET drain-to-source voltage shown in Figure 7.

Considering the effect of voltage overshoot, the V_DD

voltages for nominal output voltage and minimum output

voltage are given as:

where V_ROis reflected output voltage defined as:

N_S

V_RO







V_OV_F



(18)

N_P

where V_Fis the diode forward voltage drop and N_Pand N_S

are number of turns for the primary side and secondary

side, respectively.





N_A

N_S

N_P

VDD^max

VDD^{min 2}



 V_OV_F

V_OSV_FA

When the MOSFET is turned on, the output voltage,

together with input voltage reflected to the secondary, are

imposed across the diode as:





(22)

(23)













N_A

N_S

N_P

min







 V_OV_F

V_OSV_FA

N_S





max

V_FV_O

V_DL





(19)

N_P

where V_FAis the diode forward-voltage drop of auxiliary

winding diode.

As observed in Equations (5) and (6), increasing the

transformer turns ratio (N_P/N_S) results in increased voltage

of MOSFET, while it leads to reduced voltage stress of

rectifier diode. Therefore, the transformer turns ratio

(N_P/N_S) should be determined by the compromise between

MOSFET and diode voltage stresses. When determining the

transformer turns ratio, the voltage overshoot (V_OS) on drain

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AN-9735

APPLICATION NOTE

Transformer primary-side inductance can be calculated as:

(V_DL@B^mint_{ON @B})² f_S

(26)

L_m

2 P

IN _T @B

The maximum peak-drain current can be obtained at the

nominal output condition as:

2 P

PK

IN _T

(27)

I_DS



L_m f_S

The MOSFET conduction time at the nominal output

condition is obtained as:

L_m

t_ON I_DS^PK

(28)

min

V_DL

The minimum number of turns for the transformer primary

side to avoid the core saturation is given by:

Figure 7. V_DDand Winding Voltage

PK

L_m I_DS

B_sat A_e

min

[STEP-4] Design the Transformer

(29)

N_P



Figure 8 shows the definition of MOSFET conduction time

(t_ON), diode conduction time (t_DIS), and non-conduction time

(t_OFF). The sum of MOSFET conduction time and diode

conduction time at 70% of nominal output voltage is

obtained as:

where A_eis the cross-sectional area of the core in m²and

B_satis the saturation flux density in Tesla.

Figure 9 shows the typical characteristics of ferrite core

from TDK (PC40). Since the saturation flux density (B_sat)

decreases as the temperature rises, the high-temperature

characteristics should be considered when it comes to

charger in enclosed case. If there is no reference data, use

min









V_{DL@ B}

N_S

t_{ON @ B} t_{DIS @ B} t

1



(24)

^{ON @ B}





N_P0.7V_OV_F



B_sat=0.25~0.3T.

The first step in transformer design is to determine how

much non-conduction time (t_OFF) is allowed in DCM

operation.

Once the turns ratio is obtained, determine the proper

integer for N_Sso that the resulting N_Pis larger than N_P

obtained from Equation (29).

min

Once the t_OFFis determined, by considering the frequency

variation caused by frequency hopping and its own

tolerance, the MOSFET conduction time is obtained as:

1

t_{OFF @ B}

f_S

t_{ON @ B}



(25)

min

V_{DL@ B}

N_S

1



N_P0.7V_OV_F

Figure 8. Definition of t_ON, t_DIS, and t_OFF

Figure 9. Typical B-H Curves of Ferrite Core (TDK/PC40)

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AN-9735

APPLICATION NOTE

N

DCM operation at minimum output voltage should be also

checked. The MOSFET conduction time at minimum output

voltage is given as:

R₁V_O

N_A





1

(38)

R₂V_refN_S

Select 1% tolerance resistor for better output regulation.

2 P_{IN _T @C} L_m

1

t_{ON @C}





(30)

min

It is recommended to place a bypass capacitor of 22~68pF

closely between the VS pin and the GND pin to bypass the

switching noise and keep the accuracy of the sampled

voltage for CV regulation. The value of the capacitor affects

the load regulation and constant-current regulation. Figure

10 illustrates the measured waveform on the VS pin with a

different VS capacitor. If a higher value VS capacitor is

used, the charging time becomes longer and the sampled

voltage is higher than the actual value.

f_SR

V_DL@C

where f_SRis the reduced switching frequency to prevent

CCM operation.

Then, the non-conduction time at minimum output voltage

is given as:

min

V_DL@C

1

N_P

N_S

(31)

t_{OFF @C}



t_{ON @C}(1



)

min

f_SR

V_OV_F

The non-conduction time should be larger than 3µs (10% of

the switching period), considering the tolerance of the

switching frequency.

[STEP-5] Calculate the Voltage and Current of

the Switching Devices

Primary-Side MOSFET

The voltage stress of the MOSFET was discussed when

determining the turns ratio in STEP-3. Assuming that drain-

voltage overshoot is the same as the reflected output

voltage, maximum drain voltage is given as:

max

V_DSV_DL^maxV_ROV_OS

(32)

The RMS current though the MOSFET is given as:

t_ON f_S

rms

I_DS I_DS^PK

(33)

Figure 10.Effect on Sampling Voltage with

Different VS Capacitor

3

Secondary-Side diode

[STEP-7] Determine the Output Filter Stage

The maximum reverse voltage and the RMS current of the

rectifier diode are obtained, respectively, as:

The peak to peak ripple of capacitor current is given as:

N_S

N_P

N

max

PK

V_FV_O



V_DL

I_CO



 I_DS

(34)

(35)

(39)

N_P

N_S

The voltage ripple on the output is given by:

min

V_DL

N_P

N_S

I_F I_DS^rms



rms

²

N







I_COt_DIS

2C_O

I_CO I_O

I_CO

V_RO



(40)

V_O



 I_CO R_C





[STEP-6] Output Voltage and Current Setting

Sometimes it is impossible to meet the ripple specification

with a single output capacitor (C_O) due to the high ESR (R_C)

of the electrolytic capacitor. Additional LC filter stages

(post filter) can be used. When using the post filters, do not

to place the corner frequency too low. Too low a corner

frequency may make the system unstable or limit the control

bandwidth. It is typical to set the corner frequency of the

post filter at around 1/10 ~ 1/5 of the switching frequency.

The nominal output current is determined by the sensing

resistor value and transformer turns ratio as:

N_P

R_Sense



(37)

N_S I_O^N8.5

The voltage divider R₁and R₂should be determined such

that V_Sis 2.5V at the end of diode current conduction time,

as shown in Figure 8.

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AN-9735

APPLICATION NOTE

once the MOSFET drain voltage exceeds the voltage of

cathode of D_SN. In the analysis of snubber network, it is

assumed that the snubber capacitor is large enough that its

voltage does not change significantly during one switching

cycle. The snubber capacitor should be ceramic or a

material that offers low ESR. Electrolytic or tantalum

capacitors are unacceptable for these reasons.

[STEP-8] Cable Voltage-Drop Compensation

When the load is far away from output, the output voltage

needs to compensate for voltage drop. FAN103 and

FSEZ1317 have cable voltage-drop compensation that can

be programmed by a resistor on the COMR pin, as shown in

Table 1. If the COMR is not used, such as for LED bulb, it

needs be to connected to GND.

The snubber capacitor voltage at full-load condition (V_SN) is

given as:

Table 1. Cable Compensation

% of Voltage Drop Compensation COMR Resistor

V_SNV_ROV_OS

(41)

7%

6%

Open

The power dissipated in the snubber network is obtained as:

900㏀

2

V_SN

1

2

PK

P



 L_lk(I_DS)²

 f_S

(42)

SN

5%

4%

3%

2%

1%

0%

380㏀

230㏀

180㏀

145㏀

100㏀

45㏀

R_SN

V_SNV_OS

PK

where I_DSis peak-drain current at full load, L_lkis the

leakage inductance, V_SNis the snubber capacitor voltage

at full load, and R_SNis the snubber resistor.

The leakage inductance is measured at the switching

frequency on the primary winding with all other windings

shorted. Then, the snubber resistor with proper rated

wattage should be chosen based on the power loss. The

maximum ripple of the snubber capacitor voltage is

obtained as:

[STEP-9] Design RCD Snubber in Primary

Side

V_SN

V_SN



(43)

When the power MOSFET is turned off, there is a high-

voltage spike on the drain due to the transformer leakage

inductance. This excessive voltage on the MOSFET may

lead to an avalanche breakdown and, eventually, failure of

the device. Therefore, it is necessary to use an additional

network to clamp the voltage. The RCD snubber circuit and

MOSFET drain-voltage waveform are shown in Figure 6.

The RCD snubber network absorbs the current in the

leakage inductance by turning on the snubber diode (D_SN)

C_SN R_SN f_S

In general, 5~20% ripple of the selected capacitor voltage is

reasonable.

In the snubber design in this section, neither the lossy

discharge of the inductor nor stray capacitance is

considered. In the actual converter, the loss in the snubber

network is less than the designed value due to this effect.

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APPLICATION NOTE

Design Example Using FSFR1317

Table 2. Cable Compensation

Application

Device

Input

Output

LED Bulb

FSEZ1317MY

90V_AC~ 265V_AC(50 ~ 60Hz)

4.2W (12V/0.35A)

Description

Symbol

Value

Unit

System Specifications

min

Minimum Line Input Voltage

Maximum Line Input Voltage

Line Frequency

V_LINE

90

265

60

V_AC

Hz

V

max

V_LINE

f_L

Setting Output Voltage

V_O

12

Output Voltage at Point B

Minimum Output Voltage

V_O@B

8.40

3

V

Input

min

V_O

V

N

Normal Output Current

I_O

0.35

0.55

50

A

Output Diode Voltage Drop

Normal Switching Frequency

Switching Frequency between Point B and Point C

V_F

f_S

V

kHz

f_SR

33

Estimated Efficiency

Input

Efficiency

η

0.75

0.91

5.60

4.62

0.74

0.89

3.99

3.30

0.66

0.80

1.58

1.31

Secondary-Side Efficiency

Input Power

η_S

P_IN

Input Power of Transformer

Efficiency at Point B

P_{IN_T}

η_@B

Secondary-Side Efficiency at Point B

Input Power at Point B

η_S@B

P_IN@B

P_{IN_T@B}

η_@C

W

Output

Input Power of Transformer at Point B

Efficiency at Point C

Secondary-Side Efficiency at Point C

Input Power at Point C

η_S@C

P_IN@C

P_{IN_T@C}

Input Power of Transformer at Point C

Determine DC Link Capacitor & DC Link Voltage Range

Input

DC Link Capacitor

C_DL

9.40

µF

V

min

Minimum DC Link Voltage

V_DL

90.87

max

Maximum DC Link Voltage

Minimum DC Link Voltage at Point B

Minimum DC Link Voltage at Point C

V_DL

374.77

102.64

118.12

Output

min

V_DL@B

min

V_DL@C

Determine the Transformer Turn Ratio

Rectifier Output Voltage

Maximum V_DD

V_RO

VDD^max

VDD^min

VDD_ripple

V_FA

70.0

24.0

5.5

Minimum V_DD

Input

V_DDRipple in Burst Mode

2.5

V_DDDiode Drop Voltage

N_A/N_SRatio

0.70

0.80

70.00

5.58

0.69

0.39

0.69

0.98

N_A/N_s

V_OS

V

MOSFET Overshoot Voltage

N_P/N_SRatio

N_P/N_S

min1

Minimum N_A/N_SRatio 1

Output

N_A/N_S

min2

Minimum N_A/N_SRatio 2

N_A/N_S

Determine Minimum N_A/N_SRatio

Determine Maximum N_A/N_SRatio

N_A/N_s^min

N_A/N_s^max

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APPLICATION NOTE

Description

Symbol

Value

Unit

Transformer Design

Non Conduction Time at Point B

Transformer Core Cross-Sectional Area

Maximum Flux Density

t_OFF@B

A_e

5.00

20.10

0.30

20

µs

mm²

T

Input

B_sat

N_S

Determine Secondary-Side Turns

MOSFET Conduction Time at Point B

Transformer Primary-Side Inductance

Peak Drain Current

Turns

µs

t_ON@B

L_m

4.91

1.92

0.31

98.93

112

mH

PK

I_DS

A

min

Minimum Primary-Side Turns

Determine Primary-Side Turns

Determine Auxillary Winding Turns

Final N_P/N_SRatio

N_p

Turns

N_p

N_A

16

N_P/N_S

N_A/N_s

t_ON

5.60

0.80

6.57

8.49

4.95

3.31

19.65

7.35

Output

Final N_A/N_SRatio

MOSFET Conduction Time

Inductor Discharge Time

µs

t_DIS

Non-Conduction Time

t_OFF

MOSFET Conduction Time at Point C

Inductor Discharge Time at Point C

Non Conduction Time at Point C

t_ON@C

t_DIS@C

t_OFF@C

Selection Switching Device

MOSFET Maximum Drain-Source Voltage

max

V_DS

514.77

0.10

V

A

V

A

rms

MOSFET RMS Current

I_DS

Output

Maximum Diode Voltage

Maximum Diode RMS Current

V_F

I_F

78.92

0.65

Setting Output Voltage & Current

VS Low-Side Resistor

R2

R_sense1

R_sense2

R1__real

R1

33.00

3.9

KΩ

Ω

Current-Sensing Resistor 1

Input

Current-Sensing Resistor 2

3.6

Ω

Real VS High-Side Resistor

VS High-Side Resistor

100

KΩ

Ω

93.72

1.92

11.34

1.872

0.36

Current-Sensing Resistor

R_sense

VO

Output

Real Output Voltage Setting

Real Current-Sensing Resistor

Real Output Current Setting

V

RS

Ω

IO

A

Design RCD Snubber Stage

Leakage Inductance of Primary Side

L_lk

V_RO

V_OS

V_SN

ΔV_SN

t_S

50

70

µH

V

Rectifier Output Voltage

MOSFET Overshoot Voltage

Snubber Voltage

Input

70

V

141

V

Snubber Capacitor Ripple Voltage

Resonance Time

28.11

0.22

0.24

82.26

1.22

V

µs

W

KΩ

nF

Output

Power Dissipation in Snubber Resistor

Snubber Resistor

P_SN

R_SN

C_SN

Snubber Capacitor

Rev. 1.0.0 • 4/12/11

www.fairchildsemi.com

9

AN-9735

APPLICATION NOTE

Design Summary using FSFR1317

1

4

2

3

N

-

L

+

Figure 11.Schematic for LED Bulb

Rev. 1.0.0 • 4/12/11

www.fairchildsemi.com

10

AN-9735

APPLICATION NOTE

Transformer for LED Bulb

Core : EE-16 (Material: PC-40)

Bobbin : 8-Pin

Figure 12.Transformer Specifications and Construction

Table 3. Winding Specifications

No.

1

Winding

Pin (S → F)

2  1

Wire

Turns

Winding Method

Np

0.12φ×1

112 Ts

Solenoid winding

2

Insulation: Polyester Tape t = 0.025mm, 3 Layer

0.32φ(TEX)×1 20 Ts

Insulation: Polyester Tape t = 0.025mm, 3 Layer

0.15φ×1 16 Ts

3

Ns

8  5

3  4

4

5

Naux

6

Insulation: Polyester Tape t = 0.025mm, 3 Layer

Table 4. Electrical Characteristics

Specification

Remark

Inductance

1 – 2

1.90mH ±10%

1kHz, 1V

Rev. 1.0.0 • 4/12/11

www.fairchildsemi.com

11

AN-9735

APPLICATION NOTE

Related Datasheets

FSEZ1317 — Primary- Side Regulation PWM with Power MOSFET Integrated Datasheet

FAN103 — Primary-Side Regulation PWM Controller Datasheet

AN-8033 — Design and Application of Primary-Side Regulation (PSR) PWM Controller

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS

PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

Rev. 1.0.0 • 4/12/11

www.fairchildsemi.com

12


型号：	AN-9735
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Design Guideline for LED Lamp Control Using Primary-Side Regulated Flyback Converter, FAN103 & FSEZ1317 设计指南LED灯控制使用初级侧稳压反激式转换器， FAN103和FSEZ1317 转换器
文件：	总12页 (文件大小：481K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AN-9735 [FAIRCHILD]

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