AN-6003 [FAIRCHILD]
Shoot-through in Synchronous Buck Converters; 直通在同步降压转换器
| 型号： | AN-6003 |
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FAIRCHILD SEMICONDUCTOR |
| 描述： | Shoot-through in Synchronous Buck Converters |
| 文件： | 总6页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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AN-6003
“Shoot-through” in Synchronous Buck
Converters
Jon Klein
Power Management Applications
Abstract
The synchronous buck circuit is in widespread use to
provide “point of use” high current, low voltage
power for CPU’s, chipsets, peripherals etc. In the
synchronous buck converter, the power stage has a
“high-side” (Q1 below) MOSFET to charge the
inductor, and a “Low-side” MOSFET which replaces
a conventional buck regulator’s “catch diode” to
provide a low-loss recirculation path for the inductor
current.
2. Adaptive gate drive: This circuit looks at the
VGS of the MOSFET that’s being driven off to
determine when to turn on the complementary
MOSFET. Theoretically, adaptive gate drives
produce the shortest possible dead-time for a
given MOSFET without producing shoot-
through.
In practice, a combination of adaptive and fixed
V IN
produces the best results, and is typically what is in
today’s PWM controllers and gate drivers as shown
in Figure 2
High-Side
D1
Q1
VOUT
+5
RG
L1
BOOT
+
CBOOT
VIN
–
D
CGD
Low-Side
Q2
RGATE
HDRV
SW
PW M
G
CGS
+
1V
Q1
Figure 1. Synchronous Buck output stage
S
D
Delay
Shoot-through is defined as the condition when both
MOSFETs are either fully or partially turned on,
providing a path for current to “shoot through” from
VIN to GND. To minimize shoot-through,
synchronous buck regulator IC’s employ one of two
techniques to ensure “break before make” operation
of Q1 and Q2 to minimize shoot-through:
CGD
RGATE
LDRV
PGND
G
PW M
CGS
Q2
S
Delay
1V
1. Fixed “dead-time”: A MOSFET is turned off,
then a fixed delay is provided before the low-
side is turned on. This circuit is simple and
usually effective, but suffers from its lack of
flexibility if a wide range of MOSFET gate
capacitances are to be used with a given
Figure 2. Typical Adaptive Gate drive
Even though there apparently is a “break before
make” action by the controller, shoot-through can
still occur when the High-side MOSFET turns on,
due to Gate Step.
controller. Too long a dead-time means high
conduction losses. Too short a dead time can
cause shoot-through. A fixed dead-time
typically must err on the “too long” side to allow
high CGS MOSFETs to fully discharge before
turning on the complementary MOSFET.
Shoot-through is very difficult to measure directly.
Shoot-through currents persist for only a few nS,
hence the added inductance in a current probe
drastically affects the shoot-through waveform.
Shoot-through manifests itself typically as increased
ringing, reduced efficiency, higher MOSFET
temperatures (especially in Q1) and higher EMI.
This paper will provide analytical techniques to
predict shoot-through, and methods to reduce it.
04/25/2003
Shoot-through in Synchronous Buck Regulators
AN-6003
6
5
4
3
2
1
0
25
20
15
10
5
“Gate Step” – The shoot-
through culprit
If the adaptive circuits are working, then we
shouldn’t see any shoot-through, right?
SW NODE VOLTAGE
LS MOSFET GATE
Not exactly. Most shoot-through occurs when the
high-side MOSFET is turned on. The high dv/dT on
the SW node (Drain of the low-side MOSFET)
couples charge through CGD. This drives the gate
positive at the very moment when the driver is trying
to hold the gate low. CGD and CGS form a capacitive
voltage divider, which attenuates the gate step such
that the worst case peak amplitude of the gate step
(VSTEP) seen is:
0
-5
0
20
40
60
80
t (nS)
Figure 4. Gate Step for VIN .=20V
−TR
RT •(CGD +CGS
Further exacerbating the problem for adaptive
circuits is the fact that the adaptive comparator is not
actually sensing the voltage at the internal gate
junction of the MOSFET. As seen in Figure 5, the
internal MOSFET’s gate voltage has an unavoidable
internal RGATE resistance. In addition, some designers
like to have a “damping” resistor in series with the
gates of MOSFETs that are located physically far
away from their gate drives. This creates a bigger
problem for the adaptive gate drive circuit. These
series resistances form a voltage divider with the
internal pull-down resistance of the low-side gate
drive of the IC, causing it to think the gate voltage is
lower than it really is when it decides to release the
High-side driver.
V
)
IN
V
≈ R • C •
GD
• 1− e
STEP(PK)
T
T
R
(1a)
Where RT = RDRIVER + RGATE + RDAMPING (see Figure 5),
and TR is the rise-time of the SW node.
The limiting case is when TR = 0. Then
C
GD
V
≈ V •
(1b)
STEP(MAX)
IN
C
+ C
GD
GS
This expression only illustrates the AC portion of the
gate step. The gate step is injected onto whatever
voltage the MOSFET’s gate has discharged to. For
example, if the switch node rises when VGS = 1V,
and the gate step amplitude is 2V, instantaneously
there will be 3 VGS which is more than enough to
have a high instantaneous current through both
MOSFETs. It’s important, therefore that adaptive
gate drive circuits allow sufficient delay to prevent
the high side from turning on before the low-side VGS
is discharged down to a few hundred mV.
HDRV
H.S. MOSFET
D
Delay
CGD
RGATE
LDRV
1V
G
RDamping
CGS
RDRIVER
Q2
S
An illustration of gate step is seen below.
6
5
4
3
2
1
0
14
12
10
8
Figure 5. Resistance in the gate drive path
attenuates the voltage at the MOSFET gate node.
SW NODE VOLTAGE
When there is 1V at the pin of the IC, the internal
MOSFET VGS is:
LS MOSFET GATE
6
4
1V
(
)
V
=
• R
+ R
+ R
GATE Damping
GS(I)
DRIVER
2
R
DRIVER
0
-2
Consider an example where:
0
20
40
60
80
t (nS)
R
R
DRIVER = 2Ω ,
DAMPING = 5Ω
RGATE = 1.2Ω
Figure 3. Gate Step for VIN .=12V.
04/25/2003
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Shoot-through in Synchronous Buck Regulators
AN-6003
When the adaptive gate circuit switches, the internal
MOSFET gate voltage will be:
MOSFET Choices
MOSFET characteristics can have a dramatic effect
on how much shoot-through current can be induced
by the gate step. The worst case for shoot-through is
an infinitely fast (0 rise time) on the drain node. The
amount of gate step is largely determined by the
ration of CGS and CGD . Once the size of the gate step
is determined (eq. 1 above), the peak magnitude of
the shoot-through current can be calculated as :
1V
2Ω
(
)
• 2 +1.2 + 5 Ω = 4.1V
In this example, if there were no delay in the circuit,
the HDRV would turn on when the low-side
MOSFET has just begun to discharge, causing a very
high shoot-through current.
Much of the problem in the above circuit is the
damping resistor. If a damping resistance is
necessary, place a Schottky diode across the resistor
(as shown below) to reduce the effect the damping
resistor will have on the adaptive gate drive.
IPEAK(MAX) ≈ K • GM
•
VSTEP(MAX) − VTH(MIN)
(2)
where GM is the transconductance (in S, or A/V)
given in the datasheet. While only a small
percentage of MOSFETs exhibit VTH(MIN) at room
temperature, VTH goes down with increasing junction
temperature, therefore VTH(MIN) is a good proxy for the
VTH at the operating junction temperature of the
MOSFET. Subsequent calculations use VTH(MIN) for
this reason.
HDRV
H.S. MOSFET
D
Delay
CGD
RGATE
LDRV RDamping
1V
GM is not really a contstant, however, and its value is
greatly reduced low enhancement voltages (VGS-VTH).
In these calculations we use a factor "K" from the
graph below, which is typical of GM with low values
of enhancement. The X axis of Figure 7 is calculated
G
CGS
RDRIVER
Q2
S
VGS − VTH(MIN)
Figure 6. Schottky diode reduces damping
resistor error in adaptive gate drive
as
VTH(MIN)
When using the schottky, the internal gate node will
be at:
1.0
0.8
0.6
0.4
0.2
0.0
1V
(
)
V
= 0.5 +
• R
+ R
DRIVER GATE
GS(I)
R
DRIVER
or 2.1V for our example. A dramatic improvement.
Furthermore, the Schottky reduces the duration of the
shoot-through step, since only RGATE + RDRIVER will be
discharging CGS, rather than the sum of
RGATE + RDAMPING + RDRIVER
.
Table 1 below illustrates the performance
improvement in our example with and without the
Schottky diode:
0%
50%
100%
150%
200%
250%
300%
Normalized Enhancement Voltage
Figure 7 GM factor (K)
No
With
Schottky Schottky
Comparator Flips @ VGS(INT)
VGS(INT) after 20nS delay
VSTEP Peak
Peak current
Power Loss @ FSW=300KHz
=
4.1
2.23
2.50
36
2.1
1.14
1.25
0.29
20
V
Table 2 shows the relevant MOSFET characteristics
which determine the maximum shoot-through
current.
V
V
A
mW
Typical Min
1100
CGS CGD
GM
MOSFET
VTH
VTH
Conditions: Typical low-side MOSFET, 25nS
delay from comparator sense to beginning of SW
node rise, 19VIN, 10nS SW node rise time.
MOSFET1 3,514 307
MOSFET2 5,070 230
MOSFET3 4,942 315
MOSFET4 3,888 401
MOSFET5 6,324 281
1.6
1.2
1.6
1.6
1
0.8
1
1
0.6
86
97
80
135
90
Table 1 . Peak Currents with and without
1.15
Schottky with RDAMPING = 5Ω .
Table 2 . Low-Side MOSFET Characteristics
04/25/2003
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Shoot-through in Synchronous Buck Regulators
AN-6003
Each of the MOSFETs represented is from a different
process and has different ratios of internal
capacitance.
Reducing gate step by slowing
down Q1 rise time
Usually, designers attempt to achieve the fastest rise-
time possible on the High-Side MOSFET in order to
minimize switching losses. A simplified expression
for turn-on losses (P(TURN-ON)) for the high-side
MOSFET is:
VSTEP
IPEAK
VSTEP(MAX) VTH(MIN)
MOSFET
–VTH(MIN)
(max)
MOSFET1
MOSFET2
MOSFET3
MOSFET4
MOSFET5
1.53
0.82
1.14
1.78
0.81
1
0.8
1
1
0.6
0.53
0.02
0.14
0.78
0.21
0.31
0.02
0.07
16.37
0.13
TR • VIN •IOUT
PTURN−ON ≈ FSW
•
(3)
2
Table 3. Maximum VSTEP and ISHOOTTHROUGH
VIN = 19V and VGS(START) = 0V.
@
where TR is the rise-time of the MOSFET. A very
dV
fast rise-time (high
on SW) is desirable to
Table 3 assumes that the VGS has dropped to 0 before
the SW node rises when HDRV turns on. As
demonstrated above, the smallest amplitude of VSTEP
comes from MOSFET2 and MOSFET5, which are
low-threshold devices. Low threshold in large part is
due to a thin gate oxide, giving the MOSFET a high
dt
minimize high-side power dissipation, but if it results
in a large gate-step, causing shoot-through, the
dissipation effect can be greater than the dissipation
induced by slowing the rise time. In some situations
this is the only practical approach to eliminate shoot-
through.
C
C
GS
ratio, which attenuates VSTEP. more than other
GD
As can be seen in Figure 8, slowing down the rise
time has a dramatic effect on the amplitude of VSTEP
that is coupled into the Low-side MOSFET gate. TR
slowdown has the added benefit of reducing EMI, but
comes at a cost of efficiency loss . Figure 8 and
subsequent tables were simulated with MOSFETs
typical of those used in notebook PC’s (2 in parallel)
with 15A output current and 19VIN. Figure 8 assumes
that the SW node begins to rise when the internal
gate node has discharged down to 0.5V.
MOSFETs.
Also, Table 3 only shows the theoretical peak current
in Q2 due to the gate step. In a real converter,
parasitic inductance limits the rise in current to
4A/nS. Even for the MOSFET4, the gate pulse only
stays above threshold for about 5nS, so the shoot-
through current would be further limited.
An additional shortcoming of the simplified
calculations of Table 3 is the assumption that SW
node turn-on begins when VGS of the low-side is at 0.
As we saw from the earlier discussion, this may not
be the case.
04/25/2003
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Shoot-through in Synchronous Buck Regulators
AN-6003
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
MOSFET4
MOSFET1
MOSFET3
MOSFET5
MOSFET2
0
5
10
15
20
25
30
35
19V RiseTime(nS)
Figure 8 . Effect of SW node rise-time on VSTEP
VIN=19V, SW rise starts @ VGS(Q2) = 0.5V
Table 4 shows the power loss due to shoot-through
for each MOSFET.
SW will rise when there is still a substantial VGS on
Q2 as shown is Table 5. Slowing down Q1 can then
be an effective strategy to reduce shoot-through
losses.
The major component of switching loss during Q1
turn-on is:
TR(SW) FET1 FET2 FET3 FET4 FET5 Q1 tR Loss
VIN •IOUT
PTURN−ON ≈ tR • FSW
•
(3)
90
30
23
16
8
62
31
26
21
16
11
29
24
18
13
7
380
127
61
50
39
551
266
58
54
51
214
428
5
2
10
15
20
25
30
641
855
1,069
1,283
and is computed in the right-most column for each
rise-time in Table 4 for IOUT = 15A.
0
1
25
47
TR(SW) FET1 FET2 FET3 FET4 FET5 Q1 tR Loss
18
12
7
10
6
3
10
6
3
56
39
28
19
11
4
27
24
19
16
12
8
214
428
641
855
1,069
1,283
5
Table 5. Worst case (Min VTH) shoot-through
power loss (mW)
10
15
20
25
30
3
0
0
SW rise starts @ VGS(Q2) = 1V
0
0
0
0
0
0
This is typically achieved by adding resistance (RG
in Figure 2) in series with CBOOT . An approximation
for TR provides a good starting point for choosing a
value of RG:
Table 4. Worst case (Min VTH) shoot-through
power loss (mW)
SW rise starts @ VGS(Q2) = 0.5V
T
≈ C
• R
+ RG
(4)
R
GS
DRIVE(L−H)
In most cases, the shoot-through is negligble, so
slowing down high-side rise-time would not be a
prudent choice, since the more power would be lost
in slowing down the rise time than power saved by
eliminating shoot-through.
where RDRIVE(L-H) is the resistance of the IC’s high-side
MOSFET gate driver when driving from low to high.
If, the controller's gate drive starts to turn Q1 on
before allowing the internal node of Q2 to discharge,
04/25/2003
5
Shoot-through in Synchronous Buck Regulators
AN-6003
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04/25/2003
6
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