AN-6073 [FAIRCHILD]
Highly Integrated Green-Mode PWM Controller; 高度集成绿色模式PWM控制器
| 型号： | AN-6073 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Highly Integrated Green-Mode PWM Controller |
| 文件： | 总13页 (文件大小：493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
AN-6073
FAN6751 — Highly Integrated Green-Mode PWM Controller
Internal Open-loop Protection
Introduction
GATE Output Maximum Voltage Clamp: 18V
VDD Under-Voltage Lockout (UVLO)
VDD Over-Voltage Protection (OVP)
Internal Recovery Circuit (OVP, OLP)
Internal Sense Short-Circuit Protection
External Constant Power Limit (Full AC Input Range)
Internal OTP Sensor with Hysteresis
Built-in 5ms Soft-Start Function
This application note describes a detailed design strategy for
a high-efficiency, compact flyback converter. Design
considerations and mathematical equations are presented as
well as guidelines for a printed circuit board layout. The
highly integrated FAN6751 series of PWM controllers
provides several features to enhance the performance for
LCDM/TV, NB, and adapters.
The green-mode function includes off-time modulation and
burst mode to reduce the PWM frequency at light-load and
in no-load conditions. To avoid acoustic noise problems, the
minimum PWM frequency is set above 18KHz. This green-
mode function enables the power supply to meet
international power conservation requirements. With the
internal high-voltage startup circuitry, the power loss due to
bleeding resistors is also eliminated. Built-in synchronized
slope compensation achieves stable peak-current-mode
control. The proprietary external line compensation ensures
constant output power limit over a wide AC input voltage
Built-in VIN Pin Pull HIGH (> 4.7V) Recovery
Function for Second-Side Output OVP
Brownout Protection with Hysteresis
Applications
General-purpose, switch-mode power supplies and flyback
power converters, including:
range, from 90VAC to 264VAC
.
Power Adapters
Open-frame SMPS
LCD Monitor/TV
FAN6751 provides many protection functions, as shown in
Table 1. In addition to cycle-by-cycle current limiting, the
internal open-loop protection circuit ensures safety should
an open-loop or output short-circuit failure occur.
SOP-8
Features
High-Voltage Startup
GND
FB
1
2
3
4
8
7
6
5
GATE
VDD
Low Operating Current: 4mA
Linearly Decreasing PWM Frequency to 18KHz
Fixed PWM Frequency: 65KHz
Peak-Current-Mode Control
NC
HV
SENSE
VIN
Cycle-by-Cycle Current Limiting
Leading-Edge Blanking (LEB)
Synchronized Slope Compensation
Figure 1. Pin Configuration (Top View)
Table 1. Protection Functions of FAN6751 Series
Pull-High
Protection (VIN)
OTP
(Internal)
SCP
(SENSE)
PWM
Frequency
Part Number
OVP (VDD)
OLP (FB)
FAN6751MRMY
FAN6751HLMY
Recovery
Latch
Recovery
Latch
Recovery
Latch
Recovery
Recovery
Recovery
Recovery
65KHz
100KHz
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
www.fairchildsemi.com
AN-6073
APPLICATION NOTE
Typical Application
RSn2
CSn2
BD1
RSn1 CSn1
Lp
CBulk
R1
RHV
DSn
D1
D2
CO
Cp
VO
T1
CVDD
4
7
HV
VDD
EMI
Filter
Rd
5
2
VIN
Rg
PC817
KA431
8
Q1
RS
GATE
Fuse
C2
R2
R1
R3
FB
RLF
CLF
C1
RFB
SENSE
6
AC
INPUT
CFB
GND
1
NC
3
R2
Figure 2. Typical Application
Block Diagram
Figure 3. Functional Block Diagram
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
www.fairchildsemi.com
2
AN-6073
APPLICATION NOTE
Internal Block Operation
Startup and Soft-Start Circuitry
When power is turned on, the internal high-voltage startup
current (typically 2mA) charges the hold-up capacitor C1
through startup resistor RHV. RHV can be directly connected
by VBULK to the HV pin. The built-in 5ms soft-start circuit
starts when the VDD pin reaches the start threshold voltage
V
DD-ON. Soft-start helps reduce the inrush current, the startup
current spike, and output voltage overshoot during the
startup period, as shown in Figure 4. When VDD reaches
V
DD-ON, the internal high-voltage startup current is switched
off and the supply current is drawn from the auxiliary
winding of the main transformer, as shown in Figure 5.
Figure 6. UVLO Specification
Under-Voltage Lockout (UVLO)
VDD
The FAN6751 has a voltage detector on the VDD pin to
ensure that the chip has enough power to drive the
MOSFET. Figure 7 shows a hysteresis of the turn-on and
turn-off threshold levels and an open-loop-release voltage.
Soft
Driver
8
6
GATE
Sense
S
R
Q
Soft Start
Figure 4.
Soft-start Circuit
Figure 7. UVLO Specification
Figure 5. Startup Circuit for Power Transfer
The turn-on and turn-off thresholds are internally fixed at
16.5V and 10.5V. During startup, the VDD’s capacitor must
be charged to 16.5V to enable the IC. The capacitor
continues to supply the VDD until the energy can be
delivered from the auxiliary winding of the main
transformer. The VDD must not drop below 10.5V during the
startup sequence.
If a shorter startup time is required, a two-step startup
circuit, as shown Figure 6, is recommended. In this circuit, a
smaller capacitor C1 can be used to reduce startup time. The
energy supporting the FAN6751 after startup is mainly from
a larger capacitor C2. If a shorter releasing latch mode time
is required, a DHV and RHV can be directly connected by VAC
to the HV pin.
To further limit the input power under a short-circuit or
open-loop condition, a special two-step UVLO mechanism
prolongs the discharge time of the VDD capacitor. Figure 8
shows the traditional UVLO method along with the special
two-step UVLO method. In the two-step UVLO mechanism,
an internal sinking current, IDD-OLP, pulls the VDD voltage
toward the VDD-OLP. This sinking current is disabled after the
VDD drops below VDD-OLP; after which, the VDD voltage is
again charged towards VDD-ON. With the addition of the two-
step UVLO mechanism, the average input power during a
short-circuit or open-loop condition is greatly reduced. As a
result, over-heating does not occur.
When the supply current is drawn from the transformer, it
draws a leakage current of about 1µA from HV pin. The
maximum power dissipation of the RHV is:
PRHV = IHV − LC(Typ.)2 ×RHV
(1)
= IμA2 ×100KΩ ≅ 0.1μW
where
I
HV-LC is the supply current drawn from HV pin, and
HV is 100KΩ.
R
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
www.fairchildsemi.com
3
AN-6073
APPLICATION NOTE
down at no load. The value of the biasing resistor Rb is
determined as:
Vo −VD −VZ
• K ≥ 1.5mA
(3)
Rb
where:
VD is the drop voltage of photodiode, approximately 1.2V;
VZ is the minimum operating voltage, 2.5V of the shunt
regulator; and
K is the current transfer rate (CTR) of the opto-coupler.
For an output voltage VO=5V with CTR=100%, the
maximum value of Rb is 860Ω.
Green Mode Operation
Green mode includes off-time modulation and burst mode to
reduce the PWM frequency at light-load and in no-load
conditions. The feedback voltage of the FB pin is taken as a
Figure 8.
UVLO Effect
reference. When the feedback voltage is lower than VFB-N
,
the PWM frequency decreases. Because most losses in a
switching-mode power supply are proportional to the PWM
frequency, the off-time modulation reduces the power
consumption of the power supply at light-load and no-load
conditions. Figure 10 is the PWM frequency is 65KHz at
nominal load and decreases to 18KHz at light load.
FB Input
The FAN6751 is designed for peak-current-mode control. A
current-to-voltage conversion is done externally with a
current-sense resistor RS. Under normal operation, the FB
level controls the peak inductor current:
Frequency
VFB − 0.6
VSENSE = Ipk × RS
=
(2)
4
where VFB is the voltage on FB pin and 4 is an internal
divider ratio.
PWM Frequency
Fosc:65KHz
When VFB is less than 0.6V, the FAN6751 terminates the
output pulses.
Fosc:18KHz
VFB-N
VFB-ZDC
VFB-G
Figure 10. PWM Frequency vs. FB Voltage
The power supply enters “burst mode” in no-load
conditions. As shown in Figure 11 and Figure 12, when VFB
drops below VFB-ZDC, the PWM output is shuts off and the
output voltage drops at a rate dependent on load current.
This causes the feedback voltage to rise. Once VFB exceeds
V
FB-ZDC, the internal circuit starts to provide switching pulse.
The feedback voltage then falls and the process repeats.
Burst mode operation alternately enables and disables
switching of the MOSFET, reducing the switching losses in
standby mode.
Figure 9. Feedback Circuit
Figure 9 is a typical feedback circuit consisting mainly of a
shunt regulator and an opto-coupler. R1 and R2 form a
voltage divider for the output voltage regulation. R3 and C1
are adjusted for control-loop compensation. A small-value
RC filter (e.g. RFB= 100Ω, CFB= 1nF) placed on the FB pin
to the GND can further increase the stability. The maximum
sourcing current of the FB pin is 1.5mA. The phototransistor
must be capable of sinking this current to pull FB level
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
www.fairchildsemi.com
4
AN-6073
APPLICATION NOTE
larger ripple current ratings are required. DCM operation
also results in a higher output voltage spike. A large LC
filter is added. Therefore, a flyback converter in CCM
achieves better performance with lower component cost.
Despite the above advantages of CCM operation, there is
one concern—stability. In CCM operation, the output power
is proportional to the average inductor current, while the
peak current remains controlled. This causes sub-harmonic
oscillation when the PWM duty cycle exceeds 50%. Adding
slope compensation (reducing the current-loop gain) is an
effective way to prevent oscillation. The FAN6751
introduces a synchronized positive-going ramp (VSLOPE) in
every switching cycle to stabilize the current loop.
Therefore, the FAN6751 can be used to design a cost-
effective, highly efficient, compact flyback power supply
operating in CCM without additional external components.
The positive ramp added is:
VSLOPE = VSL • D
(4)
where VSL = 0.33V and D = duty cycle.
Figure 11. FAN6751HL Burst-mode Operation
VO
VFB
1.1
Ids
Vds
Figure 13. Synchronized Slope Compensation
Over-Power Compensation
time
The maximum output power of a flyback converter can
generally be designed by the current-sense resistor RS. When
the load increases, the peak inductor current increases
accordingly. As the current-sense signal of the SENSE pin
exceeds the internal limit VSENSE, 0.83V typically, as
VIN=1V, FAN6751 stops the PWM pulse immediately. The
output power of a flyback power supply in DCM is
calculated as follows:
Switching Switching Switching
Disabled Disabled Disabled
Switching
Disabled
Figure 12. FAN6751MR Burst-Mode Operation
Built-in Slope Compensation
A flyback converter can be operated in either discontinuous
current mode (DCM) or continuous current mode (CCM).
There are many advantages when operating the converter in
CCM. With the same output power, a converter in CCM
exhibits a smaller peak inductor current than in DCM.
Therefore, a small-sized transformer and a low-rated
MOSFET can be applied. On the secondary side of the
transformer, the RMS output current of DCM can be twice
that of CCM. Larger wire gauge and output capacitors with
1
POUT
=
• LP •IPK2 • fS •η
(5)
2
where:
Lp is the transformer primary-side inductance;
PK is the peak inductor current;
I
fS is the PWM frequency; and
η is the conversion efficiency.
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
www.fairchildsemi.com
5
AN-6073
APPLICATION NOTE
If the conversion efficiency remains unchanged for a wide
input voltage range, the maximum output power would be
the same for a fixed IPK, which is limited by the internal
current limiting threshold voltage VTH and RS. However, due
to the time delay from the comparator to output stage inside
the FAN6751, the maximum output power with high-line
input is always higher than with low line. A 30% error is
common for the universal input voltage range if the
converter is operated in DCM. In CCM operation, the
deviation becomes even larger. For the purpose of constant
output power limit, the peak current limit VTH must be
adjustable according to the VIN pin, which is proportional
to input voltage. VIN=1V and VSENSE=0.83V at low line;
VIN=3V and VSENSE=0.7 at high line.
or Latched (for HL). OVP condition is usually caused by
feedback open loops.
Overload Protection (OLP)
If the secondary output short circuits or the feedback loop is
open, the FB pin voltage rises rapidly toward the open-loop
voltage, VFB-OPEN. If the FB voltage remains above VFB-OLP
and lasts for tD-OLP, the FAN6751 stops emitting output
pulses and enters Recovery Mode (for FAN6751MR) or
latched-up mode (for FAN6751HL), as shown in Figure 17.
Vds
OVP
occurs
Power
On
Removed
AC line
Power
On
VDD
26V
16.5V
Figure 14. Universal Line Voltage Compensation for
Constant Output Power Limit
10.5V
7.5V
5V
Protection Functions
FAN6751 has protection functions in two categories: some
enter Latch Mode and the others enter Recovery Mode. The
Latch Mode can only be restart if VDD falls below 5V, as
shown Figure 15. The Recovery Mode lets VDD decrease to
UVLO mechanism until the fault condition removed, as
shown Figure 16. Both modes prevent the SMPS from
destructive states. Table 2 shows the relationship between
protection functions and part numbers.
Remove
Latch
mode
Latch mode
Without any
switching
Normal
operation
Normal
operation
Figure 15.VDD OVP Protection Waveforms
for FAN6751HL, Latch Off
Table 2. Protection Functions
Protection Functions FAN6751MR FAN6751HL
VDD Over-Voltage
Protection (OVP)
Recovery
Recovery
Recovery
Latch
Latch
Latch
Overload Protection (OLP)
Pull-High Protection
Function by VIN > 4.7V
Internal Over Temperature
Protection(OTP)
Recovery
Recovery
SENSE Pin Short-Circuit
Protection
Recovery
Recovery
Recovery
Recovery
Brownout Protection
VDD Over-Voltage Protection (OVP)
VDD OVP has protection prevents damage due to over-
voltage conditions. When the VDD voltage exceed 26V due
to abnormal conditions, PWM output is turned off until the
VDD voltage drops below UVLO then starts again (for MR)
Figure 16. VDD OVP Protection Waveforms for
FAN6751MR, Recovery
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
www.fairchildsemi.com
6
AN-6073
APPLICATION NOTE
SENSE Pin Short-Circuit Protection
The FAN6751 provides a safety protection for power supply
production. When the sense resistor is shorted by soldering
during production, the pulse-by-pulse current limiting loses
efficiency for the purpose of providing over-power
protection of the unit. The unit may be damaged when the
loading is larger than the original maximum load. To protect
against a short circuit across the current-sense resistor, the
controller immediately shuts down if a continuously low
voltage (~0.15V/150µs) on the SENSE pin is detected.
Brownout Protection
Since the VIN pin is connected through a resistive divider to
the rectified AC input line voltage, it can also be used for
brownout protection. If the VIN voltage is less than 0.7V, the
PWM output is shut off. As the VIN voltage reaches 0.92V,
the PWM output is turned on again. The hysteresis window
for ON/OFF is around 0.22V. The recommended values for
Figure 17. Overload Protection Waveforms
RBo1, RBo2, and CBo1 are 10M (5M+5M), 100K, and 2.2µF.
Using these values in the test board, the power supply is
turned off at 66V (maximum load) and recovered at 70V.
Pull-HIGH Protection Function in VIN Pin
The pull-high protection function is also included in the VIN
pin. When VIN is higher than 4.7V, FAN6751 latches up and
stops regulating. Figure 18 shows the external latch circuit
for secondary-side output OVP. If the output voltage (VO) is
higher than VZ (Zener diode voltage), VDD passes through
the RRESTRICT to VIN pin (there are three Zener diodes to
clamp this over-voltage at 6V) to achieve the latch mode.
Figure 19. Circuit for Brownout
Leading-Edge Blanking (LEB)
A voltage signal proportional to the MOSFET current
develops on the current-sense resistor RS. Each time the
MOSFET is turned on, a spike induced by the diode reverse
recovery and by the output capacitances of the MOSFET
and diode, appears on the sensed signal. Inside the
FAN6751, a leading-edge blanking time of about 350ns
helps avoid premature termination of MOSFET by the spike.
Therefore, only a small-value RC filter (e.g. 100Ω + 470pF)
is required between the SENSE pin and RS. Still, a non-
inductive resistor for the RS is recommended.
Figure 18. External Circuit for Second OVP
Internal Over-Temperature Protection (OTP)
The FAN6751 has a built-in temperature sensing circuit to
shut down PWM output once the junction temperature
exceeds 135°C. While PWM output is shut down, the VDD
voltage gradually drops to the UVLO voltage (around 7.5V).
Then VDD is charged up to the startup threshold voltage of
16.5V through the startup resistor until PWM output is
restarted. This “hiccup” mode protection continues as long
as the temperature remains above 130°C. The temperature
hysteresis window for the OTP circuit is 25°C.
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
www.fairchildsemi.com
7
AN-6073
APPLICATION NOTE
Output Driver / Soft Driving
The FAN6751’s output stage is a fast totem-pole gate driver
capable of directly driving an external MOSFET. An
internal Zener diode clamps the driver voltage under 18V to
protect the MOSFET against over-voltage. By integrating
special circuits to control the slew rate of switch-on rising
time, the external resistor Rg may not be necessary to reduce
switching noise, improving EMI performance.
Figure 20. Turn-On Spike
Figure 21. Gate Driver
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
www.fairchildsemi.com
8
AN-6073
APPLICATION NOTE
Printed Circuit Board Layout
Current/voltage/switching frequency makes printed circuit
board layout and design a very important issue. Good PCB
layout minimizes excessive EMI and prevents the power
supply from being disrupted during surge/ESD tests. The
following are some general guidelines:
Two suggestions with different pros and cons for ground
connections are recommended.
GND3→2→4→1: Possible method for circumventing the
sense signals common impedance interference.
GND3→2→1→4: Potentially better for ESD testing
where a ground is not available for the power supply. The
charges for ESD discharge path go from the secondary
through the transformer stray capacitance to the GND2
first. Then, the charges go from GND2 to GND1 and
back to the mains. Control circuits should not be placed
on the discharge path. Point discharge for common choke
can decrease high-frequency impedance and help increase
ESD immunity.
Should a Y-cap between primary and secondary be
required, the Y-cap should be connected to the positive
terminal of the Cbulk (VDC). If this Y-cap is connected to
the primary GND, it should be connected to the negative
terminal of the Cbulk (GND1) directly. Point discharge of
the Y-cap also helps with ESD. However, according to
safety requirements, the creepage between the two
pointed ends should be at least 5mm.
To get better EMI performance and reduce line frequency
ripples, the output of the bridge rectifier should be
connected to capacitor Cbulk first, then to the switching
circuits.
The high-frequency current loop is found in Cbulk
–
Transformer – MOSFET – RS – Cbulk. The area
enclosed by this current loop should be as small as
possible. Keep the traces (especially 4→1) short, direct,
and wide. High-voltage drain traces related to the
MOSFET and RCD snubber should be kept far way from
control circuits to prevent unnecessary interference. If a
heatsink is used for the MOSFET, it is recommended to
ground the heatsink.
As indicated by 3, the control circuit’s ground should be
connected first, then to other circuitry.
As indicated by 2, the area enclosed by the transformer
auxiliary winding, D1, and C1, should be kept small.
Place C1 close to the FAN6751 for good decoupling.
BD1
D1
CBulk
RHV
R1
Common
mode
CVDD
choke
HV
VDD
Rg
VIN
FB
GATE
C2
R2
SENSE
RLF
CLF
RFB
CFB
CFB
RS
GND
Figure 22. Layout Considerations
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
www.fairchildsemi.com
9
AN-6073
APPLICATION NOTE
Typical Application Circuit
Application
Output Power
Input Voltage Range
Output Voltage/Maximum Current
LCD Monitor
Power Supply
Universal Input
(90-264VAC)
12V/2A
5V/4A
44W
Features
High-Voltage Startup
Built-in 5ms Soft-Start Function
Built-in VIN Pin Pull-High (> 4.7V) Recovery Function for Second-Side Output OVP
Brownout Protection with Hysteresis
Low Standby Mode Power Consumption (Input Wattage <0.3W at No-Load Condition)
Key Design Notes
Resistors R12 and R13 work as a startup resistor to provide necessary current for IC startup. After startup, there is no
power loss on these resistors. The recommended values for R12 and R13 are 130KΩ(1/4W) and 51KΩ(1/4W).
Because the VIN pin is connected through a resistive divider R3 and R16 to the rectified AC input line voltage, it can also
be used for brownout protection. If the VIN voltage is less than 0.7V, the PWM output is shut off. As the VIN voltage
reaches 0.92V, the PWM output is turned on again. The hysteresis window for ON/OFF is 0.22V. The recommended
values for R3+R15, R16, and C16 are 10MΩ (5MΩ+5MΩ), 100KΩ, and 2.2µF. Using these values in the test board, the
power supply is turned off at 66V (maximum load) and recovered at 70V.
The secondary-side over-voltage protection (OVP) is achieved by pulling the VIN pin high. ZD1, ZD2, R29, R30, R31, R32,
C15, and U3 form a secondary-side over-voltage protection (OVP) circuit. When each output reaches OVP, photocoupler
U3 pulls the VIN pin high. The OVP voltages of the 12V-output and 5V-output are 15V and 6.8V, respectively.
Figure 23. Schematic
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
www.fairchildsemi.com
10
AN-6073
APPLICATION NOTE
Table 3. Experimental Results
Input Voltage
Input Wattage (No load)
Output Current Protection (5V)
90V/60Hz
0.198W
0.277W
5.8A
5.1A
264V/50Hz
Table 4. 44W LCD Monitor Evaluation Board Part List
PART#
F1
VALUE
NOTE
PART#
VALUE
NOTE
Fuse
4A/250V
NTC
Capacitor
2.2nF/250V
2.2nF/250V
0.33µF/250V
0.22µF/250V
120µF/400V
10nF /1KV
2.2nF /250V
2.2nF
Glass
C1
C2
Y2, Ceramic
Y2, Ceramic
Box Capacitor
Box Capacitor
Electrolytic
Ceramic
Ceramic
1206
NTC1
5Ω
C3
Resistor
1MΩ
C4
R1, R2
R3
1206+/-5%
1206 +/-5%
2W +/-5%
C5
10MΩ
47KΩ
47Ω
C6
R4
C7
R5, R6, R7, R8
R9
1206+/-5%
0805 +/-5%
0805 +/-5%
C8
2KΩ
C9
1nF
1206
R10
0Ω
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
1nF
1206
R11
NC
1000µF/16V
1000µF/16V
0.1µF/50V
0.1µF/50V
0.1µF/50V
4.7µF/50V
2200µF/10V
1000µF/10V
470pF
Electrolytic
Electrolytic
1206
R12
130KΩ
51KΩ
10Ω
2W +/-5%
2W +/-5%
0805+/-5%
1206+/-5%
1206+/-5%
1/4W
R13
R14
1206
R15
0Ω
1206
R16
100KΩ
22KΩ
10KΩ
15Ω
Electrolytic
Electrolytic
Electrolytic
0805
R17
R18
0805
R19
5µH,1/2W
1/4W
R20
100Ω
100Ω
0.5Ω
10µF/50V
0.1µF
Electrolytic
0805
R21
0805+/-5%
1W
R22
Diode
R23
750Ω
4.7KΩ
120KΩ
15KΩ
10KΩ
1KΩ
0805+/-5%
0805+/-5%
0805+/-5%
0805+/-5%
1206+/-5%
0805+/-5%
0805+/-5%
0805+/-5%
D1
D2
STPS20H100CT
1N4148
100V/20A
R24
R25
D3
FR107
R26
D4
FR103
R29
D5
MBR2060CT
6.8V
60V/20A
R30
ZD1
ZD2
BD1
R31
1KΩ
15V
R32
1KΩ
KBP206G
MOSFET
FQP8N60C
Filter
IC
U1
U2
U3
U4
FAN6751MR
PC817
PC817
TL431
TNR
Fairchild
Fairchild
Fairchild
Fairchild
Q1
Fairchild
L1
L2
L3
9mH
2.7µH
2.7µH
M1
470V
7ψ
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
www.fairchildsemi.com
11
AN-6073
APPLICATION NOTE
Transformer Specification
Figure 24. Transformer Schematic
Figure 25. Winding Sequence
Winding Specification
No
Pin(s-f)
Wire
Turns
Winding Method
Np1
6-5
0.4Ф
36Ts
Solenoid Winding
Insulation: Polyester Tape t = 0.03mm, 1 Layers
Shield1 -2
Insulation: Polyester Tape t = 0.03mm, 3 Layers
NS-5V NS-12V 7,8-9,10 7,8-11,12
Insulation: Polyester Tape t = 0.03mm, 3 Layers
Shield1 -2
Insulation: Polyester Tape t = 0.03mm, 1 Layers
Np2 5-4
Insulation: Polyester Tape t = 0.03mm, 5 Layers
NVcc 1-2
Copper Tape
0.6Ф*2
1.2Ts
Not Shorted
Solenoid Winding
Not Shorted
5 Ts
6 Ts
Copper Tape
0.4Ф
1.2Ts
32Ts
14Ts
Solenoid Winding
Solenoid Winding
0.2Ф
Insulation: Polyester Tape t = 0.03mm, 3 Layers
Electrical Specification
Pin
Value
800μH
40μH
Remarks
1KHz, 0.25V
2nd Shorted
Inductance
6-4
Leakage
6-4
Core: EER2828
Bobbin: EER2828
Ae: 82.1 [mm2]
Related Datasheets
FAN6751 — Highly Integrated Green-Mode PWM Controller
© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
www.fairchildsemi.com
12
AN-6073
APPLICATION NOTE
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HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
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© 2008 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 9/26/08
www.fairchildsemi.com
13
相关型号：
AN-6206
Primary-Side Synchronous Rectifier (SR) Trigger Solution for Dual-Forward Converter
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