AN-6075_技术文档

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AN-6075

Compact Green-Mode Adapter Using FSQ500L for Low Cost

1. Introduction

This application note describes a detailed design strategy for

a compact flyback converter. Design considerations and

mathematical equations are presented, as well as guidelines

for a printed circuit board layout. The FSQ500L is designed

for a replacement of linear power supplies to achieve low

cost. This device combines current-mode Pulse Width

Modulator (PWM) with a single-chip 700V senseFET. The

integrated PWM controller features include: fixed operating

frequency (130KHz), under-voltage lockout (UVLO)

protection, soft-start time tuned by external capacitor,

overload protection (OLP), leading-edge blanking (LEB),

optimized gate turn-on/turn-off driver, thermal shutdown

(TSD) protection with hysteresis, and temperature-

When compared to a linear power supply, the FSQ500L

reduces total size and weight, while increasing efficiency,

productivity, and system reliability. This device provides a

platform for cost-effective flyback converters.

compensated

precision-current

sources

for

loop

Figure 1.

SOT-223 Pin Configuration

compensation. The no-load power consumption can be less

than 250mW without auxiliary bias winding and down to

60mW with auxiliary bias winding for universal AC input

voltage range to meet the power conservation requirements.

Figure 2.

Typical Application

Rev. 1.0.0 • 9/11/08

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AN-6075

APPLICATION NOTE

2. Device Block Description

progressively increased with the intention of smoothly

establishing the required output voltage. It also helps to

prevent transformer saturation and reduce the stress on the

secondary diode during startup.

2.1 Startup Circuit and Soft Start

At startup, an internal high-voltage current source supplies

the internal bias and charges the external capacitor (C )

a

connected to the V_CCpin, as illustrated in Figure 4. An

internal high-voltage regulator (HV/REG) located between

2.2 Feedback Control

the D and VCC pins regulates the V

supplies operating current. FSQ500L needs no auxiliary

bias winding.

to be 6.5V and

CC

FSQ500L employs current-mode control, as shown in

Figure 5. An opto-coupler (such as the FOD817A) and

shunt regulator (such as the KA431) are typically used to

implement the feedback network. Comparing the feedback

voltage with the voltage across the R_senseresistor makes it

possible to control the switching duty cycle. When the

reference pin voltage of the shunt regulator exceeds the

internal reference voltage of 2.5V, the opto-coupler LED

current increases, pulling down the feedback voltage and

reducing the duty cycle. This typically occurs when the line

input voltage increases or the output load current decreases.

Transformer

D

2

I

CH

V

6.5V

V

CC

HV/REG

UVLO

3

I

STAR T

C

a

2.3 Pulse-by-Pulse Current Limit

REF

Because current-mode control is employed, the peak current

through the senseFET is limited by the non-inverting input

of PWM comparator (V_fb*), as shown in Figure 5.

Assuming that 225µA current source flows only through the

internal resistor (8R + R = 12 kΩ), the cathode voltage of

diode D2 is about 2.7V. Since D1 is blocked when the

feedback voltage (V_fb) exceeds 2.7V, the maximum voltage

of the cathode of D2 is clamped at this voltage, clamping

V_fb*. Therefore, the peak value of the current through the

senseFET is limited.

Figure 3.

Startup Block

The soft-start time of FSQ500L is tuned by an external V_CC

capacitor (C_a), which increases PWM comparator non-

inverting input voltage, together with the senseFET current,

slowly after it starts up. Before V_CCreaches V_START, C_ais

charged by the current I_CH-I_START, where I_CHand I_STARTare

described in Figure 3. After V_CCreaches V_START, all internal

blocks are activated, so that the current consumed inside the

IC becomes I_OP. Therefore, C_ais charged by the current I_CH

-

I_OP, which makes the increasing slope of V_CCbecome

sluggish. Make the soft-start time long or short by selecting

C_aas described in Figure 4. During t_S/S, I_DELAYis disabled to

avoid unwanted OLP. Typically, t_S/Sis around 8ms with

47µF of C_a.

V_CC

I

DELAY

I_FB

V

v_o

SenseFET

fb

OSC

2

FOD817A

KA431

D1

D2

C_B

8R

R

R₁

+

V_fb*

Gate

driver

V_CC

t_S/S

C_F

-

R₂

6.5V

6V

V_{CC R E G}

V_{S TAR T}

OLP

R_sense

V_SD

5V

V_{S TOP}

Figure 5.

Pulse-Width Modulation (PWM) Circuit

2.4 Leading-Edge Blanking (LEB)

t₁

)

t₂

t

At the instant the internal senseFET is turned on, a high-

current spike occurs through the senseFET, caused by

primary-side capacitance and secondary-side rectifier

reverse recovery. Excessive voltage across the R_senseresistor

would lead to incorrect feedback operation in the current

mode PWM control. To counter this effect, the FSQ500L

employs a leading-edge blanking (LEB) circuit. This circuit

inhibits the PWM comparator for a short time (t_LEB=250ns)

after the senseFET turns on.

t₁=C ×6V/(I_CH-I_{S TAR T}

a

t_S/S=C ×0.5V/(I_{C H}-I_OP)

a

Figure 4.

Soft-Start Function

The peak value of the drain current of the power switching

device is progressively increased to establish the correct

working conditions for transformers, inductors, and

capacitors. The voltage on the output capacitors is

Rev. 1.0.0 • 9/11/08

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APPLICATION NOTE

V_CC. In this condition, V_fbcontinues increasing until it

reaches 4.5V, when the switching operation is terminated,

as shown in Figure 7.

2.5 Protection Functions

The FSQ500L has two self-protective functions: overload

protection (OLP) and thermal shutdown (TSD). While OLP

is implemented as auto-restart mode, there is no switching

when TSD triggers. Once the overload condition is

detected, switching is terminated, the senseFET remains off,

and HV/REG turns off. This causes V_CCto fall. When V_CC

falls down to the under-voltage lockout (UVLO) stop

voltage of 5.0V, the protection is reset and the startup

circuit charges V_CCcapacitor. When V_CCreaches the start

voltage of 6.0V, the FSQ500L resumes normal operation. If

the fault condition is still not removed, the senseFET and

HV/REG remain off and V_CCdrops to V_STOPagain. In this

manner, the auto-restart can alternately enable and disable

the switching of the power senseFET until the fault

condition, is eliminated, as shown in Figure 6.

V_fb

Overload protection

4.5V

2.7V

T₁₂= C_B*(4.5-2.7)/I_{DE LA Y}

T₁

T₂

t

Figure 7.

Overload Protection

Because these protection circuits are fully integrated into

the IC without external components, the reliability can be

improved without increasing cost.

The OLP delay time is:

C_B

•

(

4.5 - 2.7

)

OLP

occurs

t₁₂

=

OLP

removed

(1)

Power

on

V

ds

I_Delay

Under 50ms delay time (the C_Bvalue should be smaller than

138nF) is applied for most applications. This protection is

implemented in auto restart mode.

V

cc

2.5.2 Thermal Shutdown (TSD)

6.5V

6.0V

The senseFET and the control IC are built in one package.

This makes it easy for the control IC to detect the abnormal

over-temperature of the senseFET. When the temperature

exceeds approximately 140°C, thermal shutdown triggers.

5.0V

t

TSD

occurs

TSD

removed

Power

on

Normal

operation

Fault

situation

Normal

operation

V

ds

Figure 6.

Auto-Restart Protection Waveforms

2.5.1 Overload Protection (OLP)

V

Overload is defined as the load current exceeding normal

level due to an unexpected abnormal event. In this situation,

the protection circuit should trigger to protect the SMPS.

However, even when the SMPS is in normal operation, the

over load protection circuit can be triggered during the load

transition. To avoid this undesired operation, the overload

protection circuit is designed to trigger after a specified time

to determine whether it is a transient situation or an

overload situation. Because of the pulse-by-pulse current

limit capability, the maximum peak current through the

senseFET is limited and, therefore, the maximum input

power is restricted with a given input voltage. If the output

consumes more than this maximum power, the output

voltage (V_O) decreases below the set voltage. This reduces

the current through the opto-coupler LED, which also

reduces the opto-coupler transistor current, increasing the

feedback voltage (V_fb). If V_fbexceeds 2.7V, D1 is blocked

and the 5µA current source starts to charge C_Bslowly up to

cc

6.5V

6.0V

5.7V

t

Normal

operation

Normal

operation

Fault

situation

Figure 8.

Over-Temperature Protection

When TSD triggers, delay current is disabled, switching

operation stops, and V_CCthrough the internal high-voltage

current source is set to 5.7V from 6.5V, as shown in Figure

8. Since the TSD signal prohibits the senseFET from

switching, there is no switching until the junction

temperature decreases sufficiently. If the junction

temperature is lower than 60°C typically, the TSD signal is

removed and V_CCis set to 6.5V again. While V_CCincreases

Rev. 1.0.0 • 9/11/08

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APPLICATION NOTE

from 5.7V to 6.5V, the soft-start function turns the

senseFET on and off with no voltage and/or current stress.

3.2 Determine DC Link Capacitor (C_DC) and

DC Link Voltage Range

It is typical to select the DC link capacitor as 2-3µF per watt

of input power for universal input range (85-264V_AC) and

1µF per watt of input power for European input range (195-

264V_AC). Figure 10 shows the corrected input voltage

waveform. The red line shows ripple voltage on the DC link

capacitor and the minimum and maximum voltage on the

DC link capacitor are expressed in Equations 2 and 3.

2.6 Burst Operation

To minimize power dissipation in standby mode, the

FSQ500L enters burst-mode operation. As the load

decreases, the feedback voltage decreases. As shown in

Figure 10, the device automatically enters burst mode when

the feedback voltage drops below V_BURL(750mV). At this

point, switching stops and the output voltages start to drop

at a rate dependent on standby current load. This causes the

feedback voltage to rise. Once it passes V_BURH(800mV),

switching resumes. The feedback voltage then falls and the

process repeats. Burst-mode operation alternately enables

and disables switching of the power senseFET, thereby

reducing switching loss in standby mode.

V

Vo^set

o

Figure 10. Bridge Rectifier and Bulk Capacitor

Voltage Waveform

V_fb

2V_O×I_O× (1- D_ch

η × C_DC× 2f_L

)

2

V_DC,min

=

2V_ac,min

-

0.80V

0.75V

(2)

(3)

2× 5.1V × 0.4A × (1- 0.3)

0.5 × 5.7μF ×120Hz

2× 85Vac²

-

I

ds

= 87V

2V_ac,max

V_DC,max

=

2 × 264V = 373V

where D_chis DC link capacitor charging duty ratio defined

as shown in Figure 10, which is typically about 0.3.

V

Output power is 2.04W, so the V_DCcapacitor is 6.08µF.

Select the nearest standard value 5.7µF (4.7µF+1µF) for

C

_DCand substitute it above. Therefore; from Equation 2 and

time

3, the V_DC,minis 87V and V_DC,maxis 373V.

Switching

disabled

Switching

disabled

t₄

t₂

t₃

t₁

3.3 Determine the Turn Ratio

Figure 9.

Burst-Mode Operation

The transformer turn ratio (n=N_pri/N_sec) is an important

parameter of the flyback converter; it affects the maximum

duty ratio when the input voltage is at a minimum value. It

also influences the voltage stresses on the MOSFET and the

secondary rectifier. The permissible voltage stresses and the

maximum voltage stresses on the MOSFET, as well as the

secondary rectifier, can be expressed as:

3. Design Example

The following is design example for 2W compact adapter.

3.1 Determine System Specifications

Output Power, P_O=2.04W (5.1V/0.4A); V_ACinput range=85

to 264V_AC(universal input), line frequency, f_L=60Hz;

Efficiency, η>50%.

V_DS,max= V_DC,max+ n(V_O+V_F)

(4)

(5)

= 373V + 11.5 × (5.1V + 0.7V )

= 440V

V_DC,max

373V

11.5

V_DR,max

=

+V_O

=

+ 5.1V = 37.5V

n

where V_Fis the forward-voltage of output diode.

Rev. 1.0.0 • 9/11/08

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APPLICATION NOTE

It is typical to set V_DS,maxas 420V~560V (60%~80% of

MOSFET rated voltage). Select the transformer turn ratio,

n, to be 11.5. According to Equation 4, V_DS,max=440V,

which satisfies 60%~80% of MOSFET rated voltage. The

maximum voltage stress on the secondary rectifier can be

calculated from Equation 5. Select SB260 rectifier diode

from Equation 5 results. (Specification of SB260 as: the

maximum reverse voltage, V_RRMis 60V and average

forward current, I_Fis 2A).

Base on Faraday’s law and the peak inductor current, the

minimum turns for the primary inductance is calculated as:

L_P×I_PK

B_max× A_e

N_P,min

=

×10⁶

(9)

800μH× 0.28A

0.24T ×19.2mm²

×10⁶= 48 Turns

where B_maxis the saturation magnetic flux density, typical

set 0.2~0.3Tesla; A_eis the cross-sectional of the core.

3.4 Determine Transformer Primary-Side

Inductance (L_P), Maximum Duty (D_max), and

3.6 Determine Secondary-Side Turns (N_P,min

)

The number of turns for the secondary winding is defined as:

Primary RMS Current (I_RMS

)

The primary-side inductance (L_P) of the transformer is

designed specifically for DCM operation and obtained as:

N_P

104

N_S

=

≅ 9 Turns

(10)

n

11.5

2×P_O

2× 5.1V × 0.4A

Select primary-side turns, N_Pto be 104 turns, so the

secondary-side turns is 9 turns, based on Equation 10.

L_P

=

≅ 800μH

(6)

2

I_PK×η × f_S

(

0.28A

)

× 0.5 ×130KHz

where I_PKis primary-side peak current, given in the

datasheet as I_LIM.

3.7 Determine Primary-Side RCD Snubber

When the MOSFET turns off, a high-voltage spike occurs

on the drain pin because of a resonance between the leakage

inductor (L_lk) of the main transformer and the output

capacitor (C_oss) of the MOSFET. The excessive voltage on

the drain pin may lead to an avalanche breakdown and

eventually damage the MOSFET. Therefore, it is necessary

to add an additional circuit to clamp the voltage.

The maximum duty ratio (D_max) can be derived as:

L_P× f_S×I_PK800μ0 ×130kHz ×0.28A

D_max

=

= 33%

(7)

V_DC,min

87V

The maximum duty ratio should be kept below 50% for

DCM operation.

The RCD snubber circuit and MOSFET drain voltage

waveforms are shown in Figure 11 and Figure 12,

respectively. The RCD snubber circuit absorbs the current

in the leakage inductor by turning on the snubber diode

(D_sn) when V_DSexceeds V_in+nV_O. It is assumed that the

snubber capacitance is large enough that its voltage does not

change during one switching period. The R_sn2can reduce the

spike damping wave and affect EMI.

The primary-side RMS current can be derived as:

D_max

3

0.33

3

(8)

I_RMS= I_PK

×

= 0.28 ×

= 0.09A

3.5 Determine Transformer Core Size (Ae) and

Minimum Primary-Side Turns (N_P,min

)

Table 1 shows the commonly used cores with output power

under 10W. The cores recommended are typical for the

universal input range and 130kHz switch frequency. Choose

the EE16 core to meet this output power from Table 1.

Table 1. Core Quick Select Table

(for universal input, f_S=130KHz and 5V output)

Cross-

Sectional

Area (Ae)

Output

Power

Range

Window

Area (Aw)

Core

EE13-Z

EI16-Z

EE16-Z

EI19-Z

17.1mm²

19.8mm²

19.2mm²

24.0mm²

33.4mm²

42.3mm^２

39.8mm²

54.4mm²

1-5W

1-10W

Figure 11. Primary-Side RCD Snubbber Circuit

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APPLICATION NOTE

3.8 External V_CCAuxiliary Winding Circuit for

Improving Power Saving

Figure 13 shows an external V_CCauxiliary winding circuit

for improving power saving. The external V_CCauxiliary

winding circuit reduces internal circuit power loss to

improve power saving.

Figure 12. MOSFET Drain Voltage Waveform

The snubber capacitor voltage (V_sn) should be determined at

the minimum input voltage and full-load condition. Once

Vsn is determined, the power dissipated in the snubber

circuit at the minimum input voltage and full-load condition

is obtained by:

Figure 13. External V_CCAuxiliary Winding Circuit for

Improving Power Saving

2

V_sn

1

2

Loss_sn

=

L_lk× I_pk²× f_S

×

(11)

R_sn

V_sn− nV_O

The number of turns for the V_CCauxiliary winding is

defined as:

where f_Sis the switching frequency of FSQ500L.

Vsn should be 2~2.5 times of nV_O. Very small Vsn results in

a severe loss in the snubber circuit, as shown Equation 11.

V_A+V_D2F

V_O+V_F

7.7 + 0.7

5.1+ 0.7

N_aux

=

× N_S

=

× 9 ≅ 13 Turns

(15)

The resistance is obtained by:

where V_Ais the voltage of V_CCauxiliary winding and V_D2F

is forward-voltage of D₂diode.

2

V_sn

R_sn

=

V_sn

1

2

L_lk×I_pk²× f_S

×

Because the FSQ500L has an internal high-voltage regulator

(HV/REG) located between the D and VCC pins that

regulates the V_CCto be 6.5V and supplies operating current.

If using the auxiliary winding, the V_CCshould be set higher

than 6.5V. Assume V_Ais 7.7V and V_CCis 6.8V, according

to Equation 15, N_aux= 13 turns is solved. The R_CFis limited

operation current; it can be obtained as:

V_sn− nV_O

130²

(12)

=

130

0.5 × 90μH× 0.28A²×130kHz ×

130 -11.55 × 5.1

= 20kΩ

The power loss from R_sncan be calculated as:

V_A- V_CC

I_OP

7.7 - 6.8

R_F

≤

=

= 1.18KΩ , using 1KΩ

(16)

760μA

2

V_sn

130

P_sn

=

≅ 0.845W

(13)

R_sn

20kΩ

where I_OPis operation current, in the datasheet as I_OP.

In this circuit, a smaller capacitor C1 (~1µF) can be used to

reduce startup time. The energy supporting the FSQ500L

after startup is mainly from a larger capacitor C2 (~22µF).

In this design example, if using the V_CCauxiliary winding,

the no-load power saving is down to 60mW.

To reduce the power loss from R_sn, the R_snshould be

selected higher than 20kΩ. From Equation 12 if the R_sn

increases, the V_snalso increases, the R_snrecommended

value is between 200kΩ and 47kΩ.

The maximum ripple of the snubber capacitor voltage is

obtained as:

Note:

1. If using the external V_CCauxiliary circuit, the V_SDvoltage of

FB pin follows as V_CCvoltage.

V_sn

C_sn

=

ΔV_sn× R_sn× f_s

(14)

130

=

≅ 0.7nF , selected 1nF

5%×130 × 200kΩ ×130kHz

where fs is the switching frequency and R_snuses 200kΩ. In

general, 5~10% ripple is reasonable.

Rev. 1.0.0 • 9/11/08

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APPLICATION NOTE

4. Printed Circuit Board Layout

Two suggestions with different pro and cons for ground

connections are recommended.

High-frequency switching current / voltage makes printed

circuit board layout a very important design issue. Good

PCB layout minimizes excessive EMI helps the power

supply survive during surge/ESD tests.

GND2→1: This could avoid common impedance

interference for the sense signal.

4.1 Guidelines

Regarding the ESD discharge path, the charges go from

secondary, through the transformer stray capacitance, to

GND1 first, and back to mains. It should be noted that

control circuits should not be placed on the discharge

path. Point discharge for common choke can decrease

high-frequency impedance and increase ESD immunity.

To improve EMI performance and reduce line frequency

ripples, the output of the bridge rectifier should be

connected to capacitor C_DCfirst, then to the switching

circuits. Refer to Figure 14.

3 should be a point-discharger route to bypass the static

electricity energy. As shown in Figure 12, it is

suggested to map out this discharge route.

The high-frequency current loop is in C_DC– Transformer

– Drain PIN – GND PIN – C_DC. The area enclosed by

this current loop should be as small as possible. Keep the

traces (especially 2→1) short, direct, and wide. High-

voltage traces related the drain of MOSFET and RCD

snubber should be kept far way from control circuits to

prevent unnecessary interference. If a heatsink is used for

MOSFET, connect this heatsink to ground.

Should a Y-cap be required between primary and

secondary, connect this Y-cap to the positive terminal

of C_DC. If this Y-cap is connected to primary GND, it

should be connected to the negative terminal of C_DC

(GND1) directly. Point discharge of this Y-cap helps

for ESD; however, the creepage between these two

pointed ends should be at least 5mm according to safety

requirements.

As indicated by 2, the ground of control circuits should

be connected first, then to other circuitry.

Place C_aclose to the controller for good decoupling.

Figure 14. Layout Considerations

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APPLICATION NOTE

5. Typical Application Circuit

Application

Output Power

Input Voltage Range

Output Voltage/Maximum Current

Universal Input

Adapter

2.04W

5.1V/0.4A

(85-264V_AC

)

5.1 Features

Single Chip 700V SenseFET Power Switch

Soft-Start Time Tuned by External Capacitor

Built-in Overload Protection (OLP) and Internal Thermal Shutdown Function (TSD) with Hysteresis

Low Standby Mode Power Consumption (Input Wattage <0.3W at No-Load Condition)

5.2 Key Design Notes

Resistors R₁and inductance L₁improve EMI.

External V_CCauxiliary circuit is from with D₆, C₉, C₁₀, and R₉. The external V_CCauxiliary winding circuit reduces

internal circuit power loss and improves power saving.

C₁₂

R₅C₂

F₁

D₁

D₂

D₄

D₃

L₁

AC

T₁

Input

L₃

C₁

R₄

D₇

R₁

C₄

C₅

C₈

C₃

V_O

R₉

D₅

Drain

D₆

C₁₀

R₃

V_CC

C₁₁

2

1

PC817

U₃

R₁₀

U₁

FSQ500L

R₃

C₆R₇

R₆

PWM

U₂

KA431

R_sense

External V_CCAuxiliary Circuit

4

3

R₈

PC817

V_FBV_CC

GND

C₉

C₇

Figure 15. Schematic

Rev. 1.0.0 • 9/11/08

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AN-6075

APPLICATION NOTE

Table 2. 2W Compact Green-Mode Adapter Evaluation Board Part List

PART#

VALUE

NOTE

PART#

VALUE

NOTE

Fuse

18Ω

Capacitor

1nF/1kV

NC

F1

1W

C1

C2

Ceramic

Resistor

4.7kΩ

1kΩ

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

SMD 0805+/-5%

SMD 1206+/-5%

C3

220µF/10V

1µF/400V

4.7µF/400V

330nF

Electrolytic

SMD 1206

Electrolytic

SMD 1206

Y2, Ceramic

C4

30Ω

C5

200kΩ

NC

C6

C7

22nF

2.2kΩ

300Ω

2KΩ

SMD 0805 +/-5%

1/4W

C8

330µF/10V

47µF/16V

22µF/50V

1µF

C9

C10

C11

C12

30Ω

1kΩ

2.2nF/250V

D1, D2, D3, D4,

D5,

IC

IN4007

1000V/1A

U1

U2

U3

FSQ500L

PC817

Fairchild

D6

D7

1N4148

SB260

Filter

60V/2A

TL431

L1

L3

470µH

3µH

Resistance

5.3 Transformer Specification

Figure 16. Transformer Schematic

Figure 17. Winding Sequence

5.3.1 Winding Specification

No

Pin(s-f)

Wire

Turns

Winding Method

Shield1

1-

0.15Ф

46Ts

Solenoid Winding

Insulation: Polyester Tape t = 0.03mm, 4 Layers

N_P2-1

Insulation: Polyester Tape t = 0.03mm, 2 Layers

Shield2 1-

Insulation: Polyester Tape t = 0.03mm, 5 Layers

N_S10-9

0.2Ф

0.15Ф

104Ts

46Ts

9Ts

TEX-E 0.4Ф

Insulation: Polyester Tape t = 0.03mm, 2 Layers

Rev. 1.0.0 • 9/11/08

www.fairchildsemi.com

9

AN-6075

APPLICATION NOTE

5.3.2 Electrical Specification

6-4

Value

800μH±5%

90μH

Remarks

1KHz, 0.25V

2nd Shorted

Inductance

Leakage

Core and Bobbin: EE16

Ae: 19.2 [mm²]

5.4 Experimental Results

Table 3. No-Load Input Wattage, Efficiency, Out Current Protection, Experimental Result

Input Wattage

(No Load without V_CC(No Load with V_CC

Auxiliary Winding ) Auxiliary Winding ) Auxiliary Winding)

Input Wattage

Efficiency

(without V_CC

Efficiency

(with V_CCAuxiliary Current

Output

Input

Voltage

Winding)

69.55%

71.08%

63.00%

59.59%

Protection

85V/60Hz

120V/60Hz

230V/50Hz

264V/50Hz

0.094W

0.116W

0.209W

0.242W

0.04W

0.043W

0.053W

0.06W

65.93%

66.34%

56.62%

53.14%

0.611A

0.65A

0.836A

0.881A

Table 4. Experimental Waveform

Figure 19. Over-Current Protection Waveform at Input

Voltage 85V_AC; Delay time is ~ 12.7ms

Figure 18. Burst-Mode Operation at Input Voltage 85V_AC

(CH1:V_O, CH2: V_DS, CH3: V_FB

)

(CH1:V_O, CH2: V_DS, CH3: V_FB

)

Figure 20. Voltage Stress of MOSFET at Input Voltage

264V_AC; Maximum Voltage is ~490V (CH2: V_DS

Figure 21. Short-Circuit Protection at Input Voltage

120V_AC(CH1:V_O, CH2: V_CC, CH3: V_FB, CH4:V_DS

)

www.fairchildsemi.com

Rev. 1.0.0 • 9/11/08

10

AN-6075

APPLICATION NOTE

6. Reference

FSQ500L — Compact Green-Mode Fairchild Power Switch (FPS™)

AN-4137 — Design Guidelines for Off-line Flyback Converters Using the FPS™

AN-4147 — Design Guideline for RCD Snubber of Flyback Converters

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS

PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or

sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be

reasonably expected to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause

the failure of the life support device or system, or to affect its safety or effectiveness

Rev. 1.0.0 • 9/11/08

www.fairchildsemi.com

11


型号：	AN-6075
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Compact Green-Mode Adapter 小巧的绿色模式适配器
文件：	总11页 (文件大小：684K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AN-6075 [FAIRCHILD]

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