AN-6206 [FAIRCHILD]
Primary-Side Synchronous Rectifier (SR) Trigger Solution for Dual-Forward Converter; 初级侧同步整流器（ SR ）触发解决方案的双正激变换器
| 型号： | AN-6206 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Primary-Side Synchronous Rectifier (SR) Trigger Solution for Dual-Forward Converter |
| 文件： | 总9页 (文件大小：546K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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AN-6206
Primary-Side Synchronous Rectifier (SR) Trigger Solution
for Dual-Forward Converter
Introduction
In any switching converter, rectifier diodes are used to
obtain DC output voltage. The conduction loss of diode
rectifier contributes significantly to the overall power losses
in a power supply; especially in low output voltage
applications, such as personal computer (PC) power
supplies. The conduction loss of a rectifier is proportional to
the product of its forward-voltage drop and the forward
conduction current. Using synchronous rectification (SR)
where the rectifier diode is replaced by MOSFET with
proper on resistance (RdsON), the forward-voltage drop of a
synchronous rectifier can be lower than that of a diode
rectifier and, consequently, the rectifier conduction loss can
be reduced.
signals for the secondary-side SR driver FAN6206.
FAN6210 also provides drive signal for the primary-side
power switches by using an output signal from the PWM
controller. FAN6210 can be combined with any PWM
controller that can drive a dual-forward converter. To obtain
optimal timing for the SR drive signals, transformer winding
voltage is also monitored. To improve light-load efficiency,
green-mode operation is employed, which disables the SR
turn-on trigger signal, minimizing gate drive power
consumption at light-load condition.
This application note describes the design procedure of SR
circuit using FAN6210 and FAN6206. The guidelines for
printed circuit board (PCB) layout and a design example
with experiment results are also presented.
The highly integrated FAN6210 is a primary-side SR
controller for dual-forward converter that provides control
Vin
PFC stage
Vac
Cbulk
Lo
Vo
Drv
n:1
R8
Q2
D1
R2
R9
Q1
FAN6210
1
2
3
4
XP
XN
SIN
GND
SOUT
VDD
8
7
6
5
R6
R7
Drv
PWM control signal
(From PWM controller)
FAN6206
RDLY DET
C1
D2
R1
1
2
3
4
LPC1
GATE1
8
7
6
5
From power supply
of PWM controller
LPC2 GND
D5
D3
D4
R3
SN
SP
GATE2
VDD
C2
R5
D6
PT
R4
Figure 1. Typical Application
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/27/10
www.fairchildsemi.com
AN-6206
APPLICATION NOTE
1. FAN6210 External Component Setting
Figure 4 and Figure 5 show the detailed timing diagrams of
XP and XN for the rising edge and falling edge of the SIN
signal. The delay from the rising edge of SOUT to XP
signal rising edge (tDLY_XP) is programmable using R1, as
shown in Figure 1. The linear relationship between R1 and
Figure 2 and Figure 3 show the simplified schematic of two
switch forward converters and their waveforms. The
rectifying SR (SR1) should be turned on right after the
primary-side MOSFETs are turned on. Then, SR1 should be
turned off right before the primary-side MOSFETs are
turned off. The freewheeling SR (SR2) should be turned on
right after the primary-side MOSFETs are turned off. Then,
SR2 should be turned off right before the primary-side
MOSFETs are turned on. The primary-side SR trigger
controller FAN6210 generates XN and XP signals, where
XN rising edge triggers the turn-off of SR and XP rising
edge triggers the turn-on of SR. FAN6210 generates XP and
XN signals two times for each in one switching cycle and
FAN6206 in the secondary side determines which SR
MOSFET should be controlled for each XP and XN signals
within one switching cycle.
tDLY_XP is shown in Figure 6.
The transformer winding voltage is much higher than the
voltage rating of FAN6210 during PWM turn-on time.
Therefore, R2 and D1 are used to block the high voltage, as
shown in Figure 1. Since there is a 400ns DET falling-edge
detection window after SOUT falls to prevent mis-
triggering of XP in DCM operation, too large value of R2
does not trigger XP properly due to too large RC time
delay. It is typical to use 10kΩ~33kΩ for R2.
The other requirement for triggering XP signal is that the
HIGH level of the DET signal must be higher than 3V. To
shorten the falling time from HIGH level to LOW level,
the breakdown voltage of Zener diode D2 is recommended
as 5~6V.
Figure 2. Simplified Circuit Diagram of
Dual-Forward Converter
Figure 4. Timing Diagram During PWM Rising Edge
Figure 3. Key Waveforms of Dual-Forward Converter
Figure 5. Timing Diagram During PWM Falling Edge
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/27/10
www.fairchildsemi.com
2
AN-6206
APPLICATION NOTE
To protect the XP and XN pins from transient voltage
spikes; components R3, R4, D3, D4, D5, and D6 are necessary
(shown in Figure 1). R3 and R4 are recommended as 10Ω.
D3~D6 are chosen as Fairchild diode 1N4148.
At the secondary side, R5 is connected between the SP and
SN pins for reducing the overshoot caused by PT. The
proper value of R5 is 1kΩ~10kΩ for most of applications.
FAN6206 External Components Setting
FAN6206 needs only four resistors to achieve winding
detection and linear-predict control (LPC). Voltage divider
with R6 and R7 detects the voltage across the drain-to-source
terminal of Q1, while the other divider with R8 and R9
detects the voltage across the drain-to-source terminal of
Q2. Figure 9 shows the typical waveform under CCM
operation, which includes rectifying SR MOSFET drain
voltage (Vds-R), freewheeling SR MOSFET drain voltage
(Vds-F), inductor current (ILo), SR control signals (SP & SN),
and SR gate signals. The detected signal on LPC1 and
LPC2 pin determines the operation of synchronous
rectification.
Figure 6. Programmable Delay with Resistor R1
2. Pulse Transformer (PT)
The differential SR control XP-XN is delivered from
FAN6210 to FAN6206 through a pulse transformer (PT), as
shown in Figure 7. For the proper signal transfer, the core
should have high initial permeability (μi). To separate
primary-side and secondary-side windings, isolation is also
necessary. It is typical to have the same number of turns for
the primary and secondary to maximize the coupling. As the
inductance of the winding decreases, the magnetizing
increases, causing the voltage drop in the primary winding,
as shown in Figure 8. The HIGH level of XP or XN signal
should be higher than 4V to ensure proper SR gate driving.
Meanwhile, too many turns may increase the inter-winding
capacitance and, therefore, the inductance value should be
determined properly. Typically, the inductance value is
recommended as 100μH~300μH.
The voltage divider scale-down factors are defined as:
R7
RatioLPC1
RatioLPC2
=
=
(1)
(2)
R6 + R7
R9
R8 + R9
2.1 Rectifying SR Gate Drive
Linear-predict control (LPC) is not essential for rectifying
SR because rectifying SR is always turned off by the SN
signal. Voltage divider with R6 and R7 is used to detect the
HIGH/LOW status of Vds-R, as shown in Figure 9. The
HIGH level threshold voltage for LPC1 is 2V, so the
plateau voltage of LPC1 should be higher than 2V. To
guarantee stable operation, the minimum plateau voltage of
LPC1 is suggested to be 3V. However, LPC pin is a low-
voltage pin, so the proper operation range is from 3V to 5V.
Therefore:
Figure 7. Pulse Transformer Structure
V
in
3 < RatioLPC1
⋅
< 5
(3)
n
where RatioLPC1 is specified in Equation 1, Vin is the input
voltage for PWM stage, and n is the turn ratio between
primary and secondary winding.
Figure 8. Slope Difference Between Different Turn
Number On XP Signal
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/27/10
www.fairchildsemi.com
3
AN-6206
APPLICATION NOTE
RatioLPC2 gets too much higher, freewheeling SR is still
turned on after ILo decreases to zero. Therefore, negative ILo
is generated. Abnormal voltage on VdsR is derived from
negative ILo and exceeds the Vds rating of MOSFET in DCM
operation. It’s important to determine RatioLPC2 properly.
For normal LPC operation, the value of R7 and R9 are
recommended as 4.7kΩ~15kΩ. R6 and R8 can be calculated
V
in
n
V
in
n
according to proper RatioLPC1 and RatioLPC2
.
V
in
n
Figure 9. Typical Waveform in CCM Operation
2.2 Freewheeling SR Gate Drive
Once the forward converter enters discontinuous conduction
mode (DCM) at light-load condition, the current through the
freewheeling SR decreases to zero before the turn-off
command by XN signal is given. Thus, the current can flow
in the reverse direction if the freewheeling SR is not turned
off before the current changes direction. LPC function is
necessary to turn off the free-wheeling SR before the output
inductor current reaches zero in DCM operation.
Figure 10.Typical Waveform in DCM Operation
R9
RatioLPC2
=
R8 + R9
is changed while
is fixed
Voltage divider with R8 and R9 determines the turn-off
timing of freewheeling SR. For proper LPC operation, the
LPC pin voltage should be normalized to the nominal
output voltage. The scale-down factor of the voltage divider
should be 1/VO.
decreases
SR is turned off later
Gate drive of
Freewheeling SR
increases
SR is turned off earlier
For 12V output application, the proper value of RatioLPC2 is:
Figure 11.Typical Waveform of QR Operation
2.3 VDD Section
1
1
< RatioLPC2
<
(4)
11.5
12
The power supply source of FAN6206 is provided from
output voltage terminal (Vo). To keep FAN6206 away from
output current interference, the VDD pin is suggested not to
be connected to Vo directly. In PC power applications, the
supervisor IC is applied to manage the protection of
secondary side. Output terminal Vo is connected to the
supervisor to achieve protection under abnormal conditions.
Therefore, Vo detecting terminal of the supervisor IC can be
used as the power source of the VDD pin. Adding a
capacitor C2 between the VDD pin and the GND pin can
keep the VDD pin away from noise. Adding a capacitor C1
is also recommended for the VDD pin of FAN6210. The
recommended value for C1 and C2 is 100nF~1μF.
Figure 10 shows the typical waveform in DCM operation.
In proper designs, freewheeling SR is turned off before ILo
decreases to zero. RatioLPC2 determines the internal charge
current of LPC function. Figure 11 shows the relationship
between RatioLPC2 and freewheeling SR gate drive signal.
The voltage level detected by the LPC2 pin (Vo/n)
determines the internal charge current ICHG. If RatioLPC2
becomes smaller, ICHG decreases. The voltage level of the
VDD pin determines the internal discharge current IDISCHG
.
However, IDISCHG does not vary with RatioLPC2. Therefore,
the discharging period is shortened. The turn-off instant of
freewheeling SR gets earlier when RatioLPC2 gets lower. If
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/27/10
www.fairchildsemi.com
4
AN-6206
APPLICATION NOTE
Printed Circuit Board Layout
In Figure 12, the power traces are marked as bold lines.
Good PCB layout improves power system efficiency,
minimizes excessive EMI, and prevents the power supply
from being disrupted during surge/ESD tests.
As indicated by 8, FAN6206 control circuits’ ground
should be connected together, then to the GND pin of
FAN6206.
As indicated by 9, the GND pin of FAN6206 should
be connected to the source of Q1 and Q2 separately.
Keeping trace 9 short and direct can maintain the
ground level between MOSFET and GND pin closed.
Thus, the SR control signal can be kept away from
error triggering.
Guidelines
For PC power applications, the PFC/PWM combination
controller is usually separated from main board and is
applied at
a daughter board. FAN6210 is also
As indicated by 10, the source terminals of Q1 and Q2
are connected to the negative terminal of Co. Keep
trace 10 short, direct, and wide.
recommended to be placed on the same daughter board.
As indicated by 1 and 2, FAN6210 control circuits’
ground should be connected together and to the GND
pin of FAN6210 first, then the GND pin to ground of
PFC/PWM combination controller.
As indicated by 11, Vo is connected to the supervisor
IC. As indicated by 12, the power supply source of
FAN6206’s VDD pin is connected to the detection
terminal of supervisor IC. Trace 11 should be long
and far away from Vo terminal. It’s helpful to prevent
LPC mechanism from output current interference.
As indicated by 7, the negative terminal of Co is
connected to case directly.
As indicated by 3 and 4, PFC/PWM combination
controller’s ground and PWM MOSFETs’ ground are
connected to the negative terminal of Cbulk. Keep trace 4
short, direct, and wide.
A Y-cap between the primary and secondary is
necessary for PC power applications. As indicated by 5
and 6, the Y-cap is suggested on the low-side, where it
is between the negative terminal of Cbulk and case.
Connecting trace 6 directly to case is helpful to surge
immunity. According to the safety requirements, the
creepage between the two pointed ends should be at
least 5mm. The Y-cap should be far away from PT.
Figure 12. Layout Considerations
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/27/10
www.fairchildsemi.com
5
AN-6206
APPLICATION NOTE
Design Example
The following example is a 12V/300W PC power supply, in
which the dual-forward topology is used. As Figure 13
shows, the FAN4801 integrated CCM PFC/PWM
combination controller is used as the controller for both PFC
stage and PWM stage.
Table 1. System Specification
Input
Input Voltage Range
90~264VAC
47~63Hz
Line Frequency Range
Output Voltage of PFC Stage (Vbulk
)
310V / 380V
The basic system parameters are listed in Table 1.The two-
level Vbulk is derived from FAN4801. The typical voltage
level for Vbulk is 380V; but under low-line and light-load
condition, Vbulk is 310V for decreasing power loss at the
PFC stage. The typical switching frequency (fs) is 65kHz for
both PFC and PWM stage.
Output
Output Voltage (Vo)
12V
Output Power (Po)
300W
65kHz
Typical Switching Frequency (fs)
In addition to low-line and light-load condition, Vbulk is
boosted to 380V. The turn ratio n for of TX1 is 11, hence the
Vds voltage during PWM turn-on period is 380/11=34.55V.
According to Equation 4, RatioLPC2 = 1/11.5. The divided
voltage on LPC2 is 3.00V. According to Equation 3, the
plateau divided voltage on LPC1 during PWM turn-off
period should be between 3V~5V. Select RatioLPC2 = 1/7.8,
then the divided voltage is 4.43V. Select R9 = 10kΩ and R8
= 105kΩ, then R7 = 10kΩ and R6 = 68kΩ. Under low-line
and light-load condition, Vbulk is decreased to 310V. The
divided voltage on LPC2 is 2.45V, while the divided voltage
on LPC1 is 3.61V.
In a typical PC power application, multi-output is necessary.
If the 12V output terminal is used to generate other output
terminals, SG6520 can be the proper supervisor IC. The
power supply of the supervisor is from 5V standby output
terminal. Flyback topology is the general structure for
standby power. The following measurements include
standby loading. FAN6751 is chosen to be the PWM
controller of standby stage.
From the specification, all critical components are treated
and final measurement results are given. Base on the design
guideline, the critical parameters are calculated and
summarized in Table 2.
+
PFC stage
(controlled by FAN4801)
-
=12V
IPWM
(To FAN4801)
1
2
3
4
8
7
6
5
G
LPC2 GND
SN GATE2
SP
VDD
1
2
3
4
XN SOUT
SIN
RDLY DET
8
7
6
5
OPWM
(From FAN4801)
VDD
Supervisor
From VDD
of FAN4801
Power supply is from
5V standby output
Figure 13.Complete Circuit Diagram
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/27/10
www.fairchildsemi.com
6
AN-6206
APPLICATION NOTE
Table 2. Bill of Materials
Part
Value
Resistor
Note
Part
Value
Inductor
Note
R1
R2
1/8W
1/4W
1/8W
1/8W
1/8W
1/8W
1/8W
1/8W
1/8W
1/8W
1/8W
1/8W
1/8W
1/8W
1/8W
2W
L1
L2
73µH
8.2kΩ
10kΩ
10Ω
1.8µH
R3
Diode
R4
D1
FR107
Zenor Diode/5.6V
1N4148
10Ω
R5
D2
2kΩ
R6
D3
68kΩ
10kΩ
105kΩ
10kΩ
10kΩ
10kΩ
4.7Ω
4.7Ω
10kΩ
10kΩ
0.15Ω
3kΩ
R7
D4
1N4148
R8
D5
1N4148
R9
D6
1N4148
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
Capacitor
C1
D7
1N4148
D8
1N4148
D9
UF1007
D10
UF1007
MOSFET
Q1
FDP5800
FDP5800
Q2
1/8W
1/8W
1/8W
1/8W
Q3
FCP20N60
FCP20N60
Q4
38.3kΩ
10kΩ
1kΩ
Transformer
TX1
TX2
TX3
IC
66:6
1:1
Primary 20mH
Primary 160μH
Primary 300μH
100nF
100nF
50V
50V
1:1.2
C2
C3
470pF
25V
U1
FAN6210
FAN6206
PC817
C4
100nF
50V
U2
C5
270μF
450V
50V
U3
C6
1μF
U4
TL431
C7
3300μF
3300μF
4.7nF/250V
16V
C8
16V
C9
Y-Capacitor
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/27/10
www.fairchildsemi.com
7
AN-6206
APPLICATION NOTE
Figure 14 and Figure 16 show the example design
waveform. Figure 14 shows the typical SR driving signals
and SR control signal SP-SN under CCM operation. Figure
16 shows that the freewheeling SR is turned off by the LPC
mechanism under DCM operation.
Figure 16. Freewheeling SR is Turned Off by LPC
Mechanism Under DCM Operation
Figure 14. SR Gate is Driven by Primary-Side Control
Signal Under CCM Operation
Figure 17.SIN Signal (Falling Edge) and SR
Control Signal
Table 4. Efficiency Measurements at VAC=115V on
300W PC Power with SRs (FDP5800)
Figure 15. SIN Signal (Rising Edge) and SR
Control Signal
Input
Watts
(W)
Output
Watts
(W)
Vs.
Efficiency Schottky
Diode
Table 3. Efficiency Measurements at VAC=115V on
300W PC Power with Schottky Diodes (FYP2006DN)
Load
100%
50%
20%
347.02
169.75
69.24
305.43
152.69
61.04
88.01%
89.94%
88.15%
+2.70%
+2.40%
+2.20%
Input
Watts(W)
Output
Watts(W)
Load
Efficiency
100%
50%
20%
357.98
174.21
70.84
305.42
152.56
70.84
85.31%
87.57%
85.95%
Figure 15 and Figure 17 shows the SIN signal of FAN6210
and SR control signals of FAN6206 together. The efficiency
test results are shown in Table 3 and Table 4. The
significant difference between the SR MOSFET and the
Schottky diode is shown in Table 4.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/27/10
www.fairchildsemi.com
8
AN-6206
APPLICATION NOTE
Related Resources
FAN6210 — Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
FAN4801 — PFC/PWM Controller Combination
FAN6751MR — Highly Integrated Green-Mode PWM Controller
SG6520 — PC Power Supply Supervisors
FDP5800 — N-Channel Logic Level PowerTrench® MOSFET 60V,80A, 6mΩ
FCP20N60 / FCPF20N60 — 600V N-Channel MOSFET
1N/FDLL 914/A/B / 916/A/B / 4148 / 4448 — Small Signal Diode
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Rev. 1.0.0 • 4/27/10
www.fairchildsemi.com
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