AN-6067_技术文档

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AN-6067

Design and Application of Primary-Side Regulation (PSR)

PWM Controller

FAN100 / FAN102 / FSEZ1016A / FSEZ1216

Abstract

Features

This application note describes a typical charger using the

PSR controller. Both the features of this controller, as well

as the operation of the power supply adaptor, are presented

in detail. Based on the proposed design guideline, a design

example with detailed parameters is given to demonstrate

the superior performance of the controller.

Constant-Voltage (CV) and Constant-Current (CC)

Control without Secondary-Feedback Circuitry

Accurate Constant Current Achieved by Fairchild’s

Proprietary TRUECURRENT^™Technique

Green-Mode Function: PWM Frequency Decreasing

Linearly

Fixed PWM Frequency at 42kHz with Frequency

Hopping to Solve EMI Problems

Applications

Low Startup Current: 10μA (Typical)

Low Operating Current: 3.5mA (Typical)

Peak-Current-Mode Control

Battery chargers for cellular phones, cordless phones,

PDAs, digital cameras, power tools

Optimal choice for the replacement of linear

transformers and RCC SMPS

Cycle-by-Cycle Current Limiting

V

_DDOver-Voltage Protection (OVP)

_DDUnder-Voltage lockout (UVLO)

Gate Output Maximum Voltage Clamped at 18V

Fixed Over-Temperature Protection (OTP)

Cable Compensation for Tight CV Regulation

(FAN102 / FSEZ1216)

PSR PWM Controller

FAN100

PSR PWM Controller

FAN102

FAN100 + Cable Compensation

FAN100 + MOSFET (1A/600V)

FAN102 + MOSFET (1A/600V)

FSEZ1016A

FSEZ1216

Pin Configurations

Figure 1. FAN100

Figure 2. FAN102

Figure 3. FSEZ1016A

Figure 4. FSEZ1216

Rev. 1.0.1 • 1/26/10

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AN-6067

APPLICATION NOTE

Typical Applications

Vbus

VS

VDD

7

3

4

6

5

8

1

2

VS

VDD

7

3

4

6

5

8

1

2

COMI

COMV

GATE

CS

COMI

COMV

GATE

CS

GND

COMR

SGND

PGND

FAN100

Figure 5. FAN100

Figure 6. FAN102 (FAN100 + Cable Compensation)

Vbus

VS

VDD

5

8

1

2

6

3

4

7

VDD

VS

5

8

1

7

6

3

4

2

DRAIN

COMI

COMV

COMI

COMV

CS

COMR

GND

N.C.

FSEZ1016A

FSEZ1216

Figure 8. FSEZ1216 (FAN102 + MOSEFET)

Figure 7. FSEZ1016A (FAN100 + MOSFET)

Rev. 1.0.1 • 1/26/10

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AN-6067

APPLICATION NOTE

Block Diagrams

Figure 9. FSEZ1016A (FAN100 + MOSFET)

Rev. 1.0.1 • 1/26/10

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AN-6067

APPLICATION NOTE

Block Diagrams (Continued)

Figure 10. FSEZ1216 (FAN102 + MOSFET)

Rev. 1.0.1 • 1/26/10

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AN-6067

APPLICATION NOTE

Introduction

This highly integrated PSR PWM controller contains several

features to enhance the performance of low-power flyback

converters. The patented topology of the PSR controller

allows for simplified of circuit designs, particularly battery

charger applications. CV and CC control can be accurately

achieved without secondary feedback circuitry. With the

addition of frequency-hopping in PWM operation, EMI

problems can be solved using minimized filter components.

As a result, a low-cost, smaller, and lighter charger is

produced when compared to a conventional design or a

linear transformer.

protection function shuts down the controller with auto

recovery when over heating occurs.

By using the PSR controller, a charger can be implemented

with few external components and at a minimized cost.

Internal Block Operation

Constant Voltage Output Regulation

PSR controller’s innovative method can achieve accurate

output CV/CC characteristic without voltage and current

sensing circuitry on the secondary side. The application

circuit and a conceptualized internal block diagram relating

to the constant voltage regulation are shown in Figure 11,

and the key waveform is shown in Figure 12. The secondary

output status is taken from the primary auxiliary winding

when the MOSFET is off. A unique sampling method is

used to acquire a duplication of the output voltage (V_sah) and

the output diode discharge time (t_dis). The sampled voltage

(V_sah) is then compared with the precise internal reference

voltage (V_ref) to determine the on-time of the MOSFET by

modulating error amplifier’s output. This inexpensive

method achieves accurate output voltage regulation.

To minimize standby power consumption, the proprietary

green-mode function provides off-time modulation to

linearly decrease the PWM frequency under light-load

conditions. This green-mode function is designed to help the

power supply meet power conservation requirements. The

startup current is only 10µA, which allows for the use of

large startup resistance for further power savings.

The PSR controller also provides numerous protection

functions. The VDD pin is equipped with over-voltage

protection and under-voltage lockout. Pulse-by-pulse current

limiting and CC control ensure over-current protection

during heavy loads. The GATE output is clamped at 15V to

protect the external/internal MOSFET from over-voltage

damage. Additionally, the internal over-temperature-

Vin

i_S

I_O

+

V_O

−

Naux

Npri

Nsec

C_O

R_O

n :1

Vref

Vsah

R₁

R₂

VS

PWM

i_P

S / H

CS

COMV

R_S

Figure 11. Internal Block of Constant Voltage Output Operation

Rev. 1.0.1 • 1/26/10

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AN-6067

APPLICATION NOTE

Constant Current Output Regulation

Green-Mode Operation

As shown in Figure 12, the output current I_Ocan be

expressed by Equation 1 when the flyback converter is

operated in DCM. As a result, the output current I_Ocan be

calculated by the signal i_pk, t_dis. The PSR controller then

determines the on-time of the MOSFET to modulate input

power and provide constant output current.

The proprietary green-mode function of the PSR controller

provides off-time modulation to linearly decrease the PWM

frequency at light-load conditions, as low as 500Hz. With

the green-mode function, the power supply can easily meet

the most stringent of power conservation requirements.

Figure 13 shows the characteristics of the PWM frequency

vs. the output voltage of the error amplifier (V_COMV). The

PSR controller uses the positive, proportional, output load

parameter (V_COMV) as an indication of the output load for

modulating the PWM frequency. In heavy load conditions,

the PWM frequency is fixed at 42KHz. Once V_COMVis lower

than V_N, the PWM frequency starts to linearly decrease from

42KHz to 500Hz. Figure 14 is a measured waveform at

burst-mode operation.

Gate

Ts

V_in

L_p

i_pk

i_P

t_dis

t_on

Frequency

n²⋅V_o

L_p

-

I_O

42KHz

40KHz

i_S

sampling voltage

1KHz

500Hz

V_S

V_G

V_N

V_COMV

Figure 12. Principal Operation Waveform of the

Flyback Converter (DCM)

Figure 13. PWM Frequency vs. V_COMV

The current-sense resistor can adjust the value of the

constant current. Through better design of the transformer

operations under discontinuous current mode, the PSR

controller’s proprietary control structure is able to achieve

accurate and constant current characteristics. Detailed

design guideline for the transformer is introduced in the

following section.

Vo(AC)

100mV/Div

Gate

10V/Div

1

Io =

⋅

[

t_dis⋅i_{s, pk}

]

V_COMV

500mV/Div

2Ts

1

=

⋅

[

n_p⋅i_pk⋅t_dis

(1)

2Ts

1

Figure 14. Measured Waveform at Burst-Mode Operation

⎡

⎤

V_CS

R_CS

⋅ n_p⋅

⋅t_dis

⎢

⎥

⎦

2Ts

⎣

where:

i_s,pkis the peak inductor current of the secondary side,

i_pkis the peak inductor of primary side.

t_disis discharge-time of transformer inductor current.

n_pis the turn ratio between primary and secondary winding.

R

V

_CSis the current-sense resistor.

_CSis the voltage on current-sense resistor.

Rev. 1.0.1 • 1/26/10

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AN-6067

APPLICATION NOTE

42kHz frequency, the MOSFET’s on-time is determined by

Frequency Hopping Operation

V

_COMIto modulate the output current.

A frequency hopping function is built in to further improve

EMI system performance. The frequency hopping period is

no longer than 3ms and the PWM switching frequency range

is 42kHz +/- 2.6kHz.

CC Regulation

CV Regulation

decreasing output impedance

V_COMI

V_COMV

4.5V

Deep Green Mode

Charging Sequence

44.6KHz

Figure 17. CV/CC Regulation Charging Sequence

+/- 2.6KHz

39.4KHz

Temperature Compensation

Frequency Hopping Period → 3mS

The PSR controller has built-in temperature compensation

circuitry to provide constant reliable voltage regulation even

at a different ambient temperature. This internal positive

temperature coefficient (PTC) compensation current is used

to compensate for the temperature due to the forward-

voltage drop of the diode output. Without temperature

compensation, the output voltage is distinctly higher in high

temperatures than in lower temperature condition, as shown

in Figure 18.

Figure 15. Gate Signal with Frequency Hopping

CV / CC Regulation

Battery chargers are typically designed for two modes of

operation, constant-voltage charging and constant-current

charging. The basic charging characteristic is shown in

Figure 16. When the battery voltage is low, the charger

operates on a constant current charging. This is the main

method for charging batteries and most of the charging

energy is transferred into the batteries. When the battery

voltage reaches its end-of-charge voltage, the current begins

to taper-off. The charger then enters the constant voltage

method of charging. Finally, the charging current continues

to taper-off until reaching zero.

high temp.

V_o

after compensation at high temp.

room temp.

Vo(V)

CV Regulation

I_o

Charging

Sequence

Figure 18. Output V-I Curve with Temperature

Compensation

As shown in Figure 19, the accuracy value of R1 and R2

determines the voltage regulation amount. The suggested

deviation for R1 and R2 is a +/-1% tolerance.

Temperature

Compensation

Io(mA)

PTC

Figure 16. Basic Charging V-I Characteristic

As mentioned in the CV regulation region section, the V_COMV

modulates MOSFET’s on-time and PWM frequency to

provide enough power to the output load. As shown in

Figure 17, as the output load increases, V_COMVgradually

rises until the system shifts into the CC regulation region. At

the same time, V_COMVincreases to 4.5V and the MOSEFT’s

on time is controlled by V_COMI. However, when power

system operates in the CC regulation region at a fixed

Vs

S / H

Auxiliary

Winding

Vref

PSR

Controller

Figure 19. Temperature Compensation

Rev. 1.0.1 • 1/26/10

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AN-6067

APPLICATION NOTE

The maximum power dissipation of R_INis:

Startup Circuitry

When the power is activated, the input voltage charges the

hold-up capacitor (C1) via the startup resistors, as shown in

Figure 20. As the voltage (V_DD) reaches the startup voltage

threshold (V_DD-ON), the PSR controller activates and drives

the entire power supply.

2

(

V_dc,max−V_DD

)

V_dc,max

R_IN

(3)

P

=

≅

R_IN,MAX

R_IN

where V_dc,maxis the maximum rectified input voltage.

Vdc

R_IN

Take a wide-ranging input (90V_AC~264V_AC) as an example,

V_dc=100V~380V:

380²

1.5×10⁶

(4)

P

=

≅ 96mW

R_IN,MAX

T_{D_ON}

V_DD

D1

PSR

Built-in Slope Compensation

C1

Controller

The sensed voltage across the current sense resistor is used

for peak-current-mode control and cycle-by-cycle current

limiting. Within every switching cycle, the PSR controller

produces a positively sloped, synchronized ramp signal. The

built-in slope compensation function improves power supply

stability and prevents peak-current-mode control from

causing sub-harmonic oscillations.

GND

Figure 20. Single-Step Circuit Connected to the

PSR Controller

The power-on delay is determined as follows:

Leading Edge Blanking (LEB)

⎛

⎞

⎟

⎠

V_DD−ON

⎜

T_{D _ON}= −R_IN⋅C₁⋅ ln 1−

(2)

Each time the MOSFET is powered on, a spike, induced by

the diode reverse recovery and by the output capacitances of

the MOSFET and diode, appears on the sensed signal. To

avoid premature termination of the MOSEFT, a leading-

edge blanking time is introduced in the PSR controller.

During the blanking period, the current-limit comparator is

disabled and unable to switch off the gate driver.

⎜

V_ac⋅ 2 − I_DD−ST⋅ R_IN

⎝

where I_DD-STis the startup current of the PSR controller.

Due to the low startup current, a large R_INvalue, such as

1.5MΩ can be used. With a hold-up capacitor of 4.7µF, the

power-on delay T_{D_ON}is less than 3s for a 90V_ACinput.

If a shorter startup time is required, a two-step startup

circuit, as shown in Figure 21, is recommended. In this

circuit, a smaller C1 capacitor can be used to decrease

startup time without a need for a smaller startup resistor

(R_IN) and increase the power dissipation on the R_INresistor.

The energy supporting the PSR controller after startup is

mainly from a larger capacitor C2.

Under-Voltage Lockout (UVLO)

The power-on and off thresholds of the PSR controller are

fixed at 16V/5V. During startup, the hold-up capacitor must

be charged to 16V through the startup resistor to enable PSR

controller. The hold-up capacitor continues to supply V_DD

until power can be delivered from the auxiliary winding of

the main transformer (V_DDmust not drop below 5V during

this startup process). This UVLO hysteresis window ensures

that the hold-up capacitor can adequately supply V_DDduring

startup.

Vdc

R_IN

V_DDOver-Voltage Protection (OVP)

T_{D_ON}

V_DDover-voltage protection prevents damage due to over-

voltage conditions. When V_DDexceeds 28V due to abnormal

conditions, PWM output is turned off. Over-voltage

conditions are usually caused by open feedback loops.

V_DD

PSR

C2

C1

Controller

GND

Over-Temperature Protection (OTP)

The PSR controller has a built-in temperature sensing circuit

to shut down the PWM output if the junction temperature

exceeds 145°C. When the PWM output shuts down, the V_DD

voltage gradually drops to the UVLO voltage. Some of the

internal circuits shut down and V_DDgradually starts

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Figure 21. Two Steps of Providing Power to the

PSR Controller

Rev. 1.0.1 • 1/26/10

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AN-6067

APPLICATION NOTE

increasing again. When V_DDreaches 16V, all the internal

circuits, including the temperature sensing circuit, start

operating normally. If the junction temperature is still higher

than 145°C, the PWM controller shuts down immediately.

This continues until the temperature drops below 120°C.

For example, a power board for a charger application is

5V/1A. Short the COMR pin to GND first and measure the

output voltage from light load to maximum load. If the

output voltage with cable is 4.7V at 1A, the percentage to

5V is 6%. Calculate the R_COMRas:

6

GATE Output

(6)

R_COMR

=

≅ 59.5KΩ

100.8×10⁻⁶

The PSR controller BiCMOS output stage is a fast totem

pole gate driver. Cross conduction design elimination was

used to minimize heat dissipation, increase efficiency, and

enhance reliability. The output driver is clamped by an

internal 15V Zener diode for the protection of power

MOSFET against over-voltage gate signals.

Choose the approximate value of R_COMRand let the output

voltage compensate gradually. Figure 23 is R_COMRcompared

to percentage curve for reference.

12

10

8

Brownout Protection

The PSR controller has a built-in brownout protection

circuit to shut down the PWM output. As the input voltage

decreases, the flowing current from VS pin is less than I_VS-

_UVP, the PWM output shuts down immediately and enters an

auto restart mode. The V_DDvoltage gradually drops to the

UVLO voltage.

6

4

2

0

10

20

30

39

51

60

68

81

91

100

R

_COMR(K ohm)

Figure 23. R_COMRvs. Percentage

R_VS

Lab Note

Vs

Auxiliary

Before reworking or soldering / desoldering on the power

supply, discharge the primary capacitors by way of the

external bleeding resistor. If not, the PWM IC may be

destroyed by external high-voltage discharge during the

soldering / desoldering.

Winding

I_VS-UVP

PSR

Controller

MOS turns on

Figure 22. Brownout Protection

Cable Compensation

The FAN102/FSEZ1216 PWM controller has a cable

compensation function used to compensate the output

voltage drop due to output cable loss. Use an external

resistor connected from COMR pin to GND adjusts the

amount of cable compensation.

In CV regulation control, the on-time of MOSFET only

regulates on-board voltage, not including output cable.

Different cable wire gauge or length results in different

output voltage. As previous mentioned in the CC regulation

control section that can calculate the output current. This

calculated signal can provide the controller the output load

condition and determine the amount of cable compensation,

then rescue output voltage drop. To calculate compensation

percentage, use the equation below:

Percentage

100.8×10⁻⁶

(5)

R_COMR

=

Rev. 1.0.1 • 1/26/10

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AN-6067

APPLICATION NOTE

Determine Maximum and Minimum Input Voltage

Application Information

Figure 26 shows the corrected input voltage waveform. The

red line shows ripple voltage on the bulk capacitor and the

minimum and maximum voltage on the bulk capacitor is

expressed in equations 7 and 8, respectively. The C_BULKis

the input capacitor and a typical value is 2-3µF per watt of

output power for wide range input voltage (90-264V).

Transformer Design

The transformer inductor current must operate in DCM

under any conditions. A typical output V-I curve is shown in

Figure 24. For discontinuous current mode operation, the

transformer inductor should be small enough to meet this

condition. Point “B” is the lowest output voltage within the

CC regulation and the widest discharge time of the

transformer inductor due to the reflected voltage on the

primary inductor. It is the easiest into CCM condition for

transformer inductor.

V

in.min

Assume

2.5mS

Point “A” is the maximum output power of the power

system. Ensure that the magnetic flux density falls within

0.25~0.3 Tesla, considered a safe range. The number of

turns for primary transformer inductor can be determined on

point “A.” Figure 25 shows the characteristic curve of turn

ratio and transformer inductance.

Figure 26. Bridge Rectifier and Bulk Capacitor Voltage

Waveform

2⋅V_o⋅ I_o⋅(1- 0.3)

η ⋅C_bulk⋅120

2

V_in.min= 2⋅V_ac,min

-

(7)

(8)

V

maximum output power

o

(determine turn number)

V

= 2 ⋅V_ac.max

in.max

A

Determine the Turn Ratio

determine

The transformer turn ratio (n_p=N_pri/N_sec) is an important

primary inductor

B

parameter of the flyback converter; it affects the maximum

duty ratio when the input voltage is at a minimum value. It

also influences the voltage stresses on the MOSFET and the

secondary rectifier. The permissible voltage stresses and the

maximum voltage stresses on the MOSFET, as well as the

secondary rectifier, can be expressed as:

I_o

Figure 24. Critical Operating Points to Determine

the Transformer

V_DS.max=V_in.max+ n_p⋅(V_o+V_f)

(9)

B=0.5V

B=1V

B=1.5V

B=2V

V

in.max

V_F.max

=

+V_o

3.5

3

(10)

n_p

2.5

2

The leakage spike due to leakage inductance on the

MOSFET and rectifier must also be taken into account.

1.5

1

Determine Transformer Inductance

Determine the V_DDvoltage level and if the output voltage is

defined. The turn ratio between auxiliary winding and

secondary winding can be calculated as:

0.5

0

Io =1A, Vf = 0.45V

5

6

7

8

9

10

11

12

13

14

15

V_DD+V_fa

n(turn ratio)

n_a=

(11)

V_O+V_f

Figure 25. Characteristic Curve of Turn Ratio

and Inductance

where V_DDis voltage on V_DDcap, usually ranging from

about 15V~20V.

In the CC regulation region, on point “B,” the power system

shuts down if the output voltage is too low and the V_DD

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Rev. 1.0.1 • 1/26/10

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AN-6067

APPLICATION NOTE

voltage reaches the turn-off threshold voltage of the PSR

controller. Therefore, if n_awas calculated, the Vo,_“B”can be

obtained as:

Determine Primary Inductance Turn Number

Based on Faraday’s law and the peak inductor current, the

minimum turns for the primary inductance is calculated as:

V + 6.75-V ⋅n

⎛

⎜

⎝

⎞

⎟

⎠

L_p⋅i_{pk," A"}

fa

f

a

⋅10⁶

V_O,"B"

=

(12)

N_pri

=

(17)

n_a

B_max⋅ A

e

where:

V_fais forward-voltage of rectifier diode of auxiliary winding.

V_fis forward-voltage of output diode.

B

_maxis the saturation magnetic flux density,

A_eis the effective area of the core-section.

6.75V is typically the turn-off threshold voltage of the PSR

controller.

The number of turns for the secondary winding is defined as:

N_pri

The maximum duty ratio can be calculated by using a point

“B” output condition:

N_sec

=

(18)

n_p

n_p⋅(V_o,"B"+V_f)

Once the secondary winding has been calculated, the

number of turns for the auxiliary winding is defined as:

d_on.max,"B"

=

(13)

V

_in.min,"B"+ n_p⋅(V_o,"B"+V_f)

N_aux= n_a⋅ N_sec

(19)

The transformer inductance (L_p) is designed specifically for

DCM operation and a CC tolerance of +/-10% should be

considered. The transformer inductance can be obtained as:

Determine the Divider Resistor (R₁) and Current-

Sense Resistor (R_S)

2

η

_,"B"⋅V_{in.min," B"}²⋅d_{max," B"}

L_p=

(14)

Once the output voltage V_Oand auxiliary winding have been

defined, the feedback signal divider resistor, R₁, can be

calculated as:

2⋅V_{o," B"}⋅ I_o⋅ f_s

where:

η_,”B”is the estimated system efficiency of point “B.”

⎡

⎢

⎤

⎥

n_a

R = R ⋅

⋅ V +V −1

(20)

(

)

1

2

O

f

If no values are available, use 0.45~0.5 as an initial value.

V

⎢

⎣

⎥

⎦

ref

f_sis the PWM frequency.

where V_ref=2.5V, R₂is typically set to 15~20KΩ.

After the primary inductance is calculated, the maximum

duty ratio of point “A” can be expressed as:

As discussed in the Constant Current Output Regulation

section, the region of constant current output operation can be

adjusted by the current-sense resistor. After the turn ratio (n_p)

has been determined, the relationship between the output

current I_Oand current sense resistor R_sis expressed as:

2⋅V_{O," A"}⋅ I_O⋅ L_P

d_{on.max," A"}

=

(15)

η

_{," A"}⋅V_{in. min," A"}²⋅T_s

where T_sis the switching period.

0.111875⋅n_p

The primary peak inductor current (I_PK) of point “A” at full

load and low line input voltage condition is:

R_S=

(21)

I_O

V

^in.min,"A"⋅d_on.max,"A"⋅T_S

As Figure 27 shows, a design spreadsheet can be used to

calculate the transformer design and select the power system

components for a first prototype. A 5V/1A design example

is shown in Figure 27.

i_pk,"A"

=

(16)

L_p

Rev. 1.0.1 • 1/26/10

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APPLICATION NOTE

Figure 27. Calculated System Parameter by Design Spreadsheet

The parameters in Figure 27 can be found in the corresponding components in Figure 28.

V_dc

R

in

- V_Fa

+

+ V_F

-

+

V_O

−

Nsec

Naux

Npri

R₁

+

V_ds

-

VS

VDD

n_a: n_p:1

R₂

Vs Cap.

VDD Cap.

R_S

Figure 28. Application Circuit

6

1

Vin

Primary

Winding

Secondary

Winding

N2

N1

N3

Transformer Structure

2

3

MOS 's

As mentioned in the Constant Voltage Output Regulation

section, the PSR controller incorporates a proprietary

control design to achieve CV/CC regulations. A correct

sampling voltage of the auxiliary winding is critical to the

CV/CC performance. Therefore, the coupling of the

auxiliary winding and the secondary winding should be

precise. The suggested transformer structure is shown in

Figure 29 and Figure 30. The coupling coefficient between

the secondary winding and the auxiliary winding can be

effectively improved by sloughing off the EMI shielding

between auxiliary winding and secondary winding. Further

effectiveness is achieved by increasing the coupling area

through a well-paved the auxiliary winding on the top layer.

Drain

8

Auxiliary

Winding

4

EMI Shielding

Figure 29. Transformer Winding

Auxiliary

4

3

6

Winding(N3)

Secondary

8

Winding(N2)

(Insulated)

EMI Shielding

1

2

Primary

Winding(N1)

EMI Shielding

Figure 30. Recommended Transformer Structure

Rev. 1.0.1 • 1/26/10

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AN-6067

APPLICATION NOTE

Effect of the Vs Pin Capacitor

A V_Scapacitor with 22~68pF placed closely between Vs pin

and the GND pin is recommended. The capacitor is used to

bypass switching induced noise and keep the accuracy of the

sampled voltage. The value of the capacitor affects the load

regulation and constant current performance. Figure 31

illustrates the measured waveform on the Vs pin with a

different V_Scapacitor. If a higher value V_Scapacitor is used,

the charging time becomes longer and the sampled voltage is

higher than the actual value. Figure 32 shows the effect on

the sampled voltage with a different V_Scapacitor.

No-Load

Figure 33 shows a measured Vs pin waveform at a no-load

condition. As illustrated, the feedback voltage is too narrow.

Additionally, a large V_Scapacitor causes the inaccurate

sampling of the voltage; resulting in the rising of the output

voltage. Figure 24 shows the influence of the V_Scapacitor

on the V-I curve.

VS

Gate COMV Vf

Figure 33. Measured Vs Pin Waveform at No Load

V_o

Lower Vs Cap.

Higher Vs Cap.

I_o

Figure 34. Comparison of V-I Curve

with Different V_sCapacitor

Effect of V_DDand Snubber Capacitors

V_DDvoltage and snubber capacitors are related to the

feedback signal inaccuracy and cause output voltage to rise

at no-load condition.

Figure 31. Measured Waveform with

Different V_SCapacitor

If the V_DDcapacitor is not big enough, the decreasing PWM

frequency at no-load condition causes V_DDvoltage to drop

quickly. In such a condition, the feedback signal is

dominated by the V_DDvoltage, but not the secondary output

voltage. To avoid this, it is recommended the V_DDcapacitor

value be larger than 4.7µF(6.8~10µF).

higher Vs Cap

lower Vs Cap

Vs pin waveform

sampling voltage

On the other hand, the value of the snubber capacitor also

affects the output voltage performance. When the MOSEFT

is turned off, the polarity of the transformer primary side

inductor is reversed and the energy stored in the transformer

inductor is delivered to the secondary to supply load current.

In the meantime, if the output voltage is higher than the

voltage on the secondary winding (V_sec), the output diode is

still reversed. The resulting voltage V_priis then applied to

the primary inductor, L_p, which charges the snubber

sampling voltage

No - Load

capacitor. The charge time influences the feedback voltage

signal on the auxiliary winding. It is recommended that the

snubber capacitor remain under 472pF(332~102pF).

Figure 32. Effect on Sampling Voltage with

Different V_SCapacitor

Rev. 1.0.1 • 1/26/10

www.fairchildsemi.com

13

AN-6067

APPLICATION NOTE

Vin

R_a

- V_fa+

+ V_f-

+

Vaux

-

+

Vsec

V_O

−

Vpri

R₁

-

VDD

VS

SGP100

n_a: n_p:1

V_O>V_sec

R₂

Vs Cap.

V_DDCap.

Figure 35. V_DDand Snubber Capacitors Effect on Output Voltage

Reducing No-Load Output Voltage with a

“Dummy” Load

At no-load and very light load conditions, due to the very

low PWM frequency caused by feedback signal deviations

and output voltage rises, especially at low-line input voltage

condition. Increasing the addition of a dummy load can fix

this problem. Figure 36 shows the effect of a higher and

lower dummy load on the V-I curve. The level of the

dummy load is suggested at about 25~100mW.

lower snubber cap,

V_o

higher V_DDcap , dummy load

higher snubber cap,

lower V_DDcap , dummy load

I_o

Figure 36. Dummy Load Effect on Output Characteristic

Rev. 1.0.1 • 1/26/10

www.fairchildsemi.com

14

AN-6067

APPLICATION NOTE

PCB Layout Considerations

High-frequency switching current / voltage make PCB

layout a very important design issue. Good PCB layout

minimizes excessive EMI and helps the power supply

survive during surge/ESD tests.

Suggestion for the Ground Connections

GND 3→2→4→1: May make it possible to avoid common

impedance interference for the sense signal.

Regarding the ESD discharge path, the charges go from

secondary through the transformer stray capacitance to

GND2 first. Then the charges go from GND2 to GND1 and

back to the mains. It should be noted that control circuits

should not be placed on the discharge path.

General Guidelines

The numbers in the following guidelines refer to Figure 37.

To improve EMI performance and reduce line frequency

ripples, the output of the bridge rectifier should be

connected to capacitors C1 and C2 first, then to the

switching circuits.

5 Should a point-discharge route to bypass the static

electricity energy. As shown in Figure 38, it is suggested to

map out this discharge route.

The high-frequency current loop is in C2 – Transformer –

MOSFET – R7 – C2. The area enclosed by this current

loop should be as small as possible.

Start in secondary GND to the positive terminal of C2, then

to front terminal of bridge rectifier. If this discharge route is

connected to the primary GND, it should be connected to the

negative terminal of C2 (GND1) directly.

Keep the traces (especially 4→1) short, direct, and wide.

High voltage traces related to the drain of MOSFET and

RCD snubber should be kept far way from control circuits to

prevent unnecessary interference. If a heatsink is used for

the MOSFET, connect this heatsink to a ground.

However, the creepage distance between these two pointed

ends should be long enough to satisfy the requirements of

applicable standards.

As indicated by 3, the ground of the control circuits should

be connected first, then to other circuitry.

As indicated by 2, the area enclosed by the transformer

aux winding, D1 and C3, should also be kept small.

Place C3 close to the PSR controller for good decoupling.

R13

5

T1

BD1

R8

C6

C1

C2

L1

D4

R1

D1

1

R2

R3

C3

U1

2

D3

VS

VDD

7

3

4

6

5

8

1

2

C5

R4

COMI

GATE

CS

R5

R6

C8 R10

COMV

R7

C7 R9

SGND

PGND

4

PSR Controller

3

Figure 37. Layout Consideration

Rev. 1.0.1 • 1/26/10

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15

AN-6067

APPLICATION NOTE

PCB Layout Considerations (Continued)

Figure 38. PCB Layout Example (5V/1A, 5W Power Board)

Rev. 1.0.1 • 1/26/10

www.fairchildsemi.com

16

AN-6067

APPLICATION NOTE

Reference Circuits

C8

R11

L2

R13

L1

D4

T1

BD1

R8

C5

D3

C1

C2

C9

C10

R12

R1

D1

R2

R3

C3

U1

R4

VS

VDD

7

3

4

6

5

8

1

2

C4

COMI

GATE

CS

R5

R6

C7 R10

COMV

R7

C6 R9

SGND

PGND

Figure 39. Application Circuit FAN100 (5V/1A)

BOM List

Symbol Component

R1

R2

R3

R4

R5

D4

C1

C2

C3

C4

Diode 5A/60V SB560

Resistor 1.5MΩ 1/2W

Electrolytic Capacitor 1µF/400V

Electrolytic Capacitor 10µF/400V

Electrolytic Capacitor 10µF/50V

MLCC X7R 22pF

Resistor 4.7Ω

Resistor 115KΩ 1%

Resistor 18KΩ 1%

Resistor 47Ω

R6

R7

R8

R9

C5

C6

C7

C8

Snubber Capacitor 472pF/1KV

MLCC X7R 683pF

Resistor 100Ω

Resistor 1.4Ω 1/2W 1%

Resistor 100KΩ 1/2W

Resistor 200KΩ

MLCC X7R 103pF

MLCC 102pF/100V

R10

C9

Electrolytic Capacitor 560uF/10V L-ESR

Resistor 30KΩ

Resistor 47Ω

Resistor 510Ω

R11

R12

C10

L1

Electrolytic Capacitor 330µF/10V L-ESR

Inductor 1mH

R13

BD1

D1

L2

Q1

Inductor 5µH

WireWound Resistor 18Ω

Rectifier Diode 1N4007 *4

Diode 1A/200V FR103

Fairchild 2A/600V 2N60 TO-251

FAN100

U1

D3

Diode 1A/1000V 1N4007

TR1

EE-16 Lm=1.5mH Pri:Sec:Aux=135:10:33

Rev. 1.0.1 • 1/26/10

www.fairchildsemi.com

17

AN-6067

APPLICATION NOTE

Reference Circuits (Continued)

R8

C8

L2

R10

L1

D4

T1

BD1

R5

C5

D3

C1

C2

C9

C10

R9

R1

D1

C3

R2

R3

U1

VS

VDD

6

3

4

2

5

8

1

7

C4

COMI

COMV

DRAIN

CS

C7 R7

R4

C6 R6

GND

N.C.

Figure 40. Application Circuit FSEZ1016A (FAN100 + MOSFET) (5V/1A)

BOM List

Component

Symbol

R1

R2

R3

R4

R5

C1

C2

C3

C4

C5

Electrolytic Capacitor 1µF/400V

Electrolytic Capacitor 10µF/400V

Electrolytic Capacitor 10µF/50V

MLCC X7R 47pF

Resistor 1.5MΩ

Resistor 127KΩ 1%

Resistor 20KΩ 1%

Resistor 1.36Ω 1/2W 1%

Resistor 100KΩ 1/2W

Snubber Capacitor 472pF/1KV

R6

R7

R8

R9

C6

C7

C8

C9

MLCC X7R 683pF

Resistor 200KΩ

Resistor 39KΩ

Resistor 47Ω

MLCC X7R 103pF

MLCC 102pF/100V

Electrolytic Capacitor 560µF/10V

Resistor 510Ω

R10

BD1

D1

C10

L1

Electrolytic Capacitor 330µF/10V

Inductor 1mH

WireWound Resistor 18Ω

Rectifier Diode 1N4007 *4

Diode 1A/200V FR103

Diode 1A/1000V 1N4007

Diode 5A/60V SB560

L2

Inductor 5µH

D3

U1

FSEZ1016A

D4

TR1

EE-16 Lm=1.5mH Pri:Sec:Aux=135:10:33

Rev. 1.0.1 • 1/26/10

www.fairchildsemi.com

18

AN-6067

APPLICATION NOTE

Reference Circuits (Continued)

C9

R11

L2

R13

L1

D4

T1

BD1

R8

C6

D3

C1

C2

C10

C11

R12

R1

D1

C3

R3

R4

U1

VDD

VS

7

3

4

6

5

8

1

2

C5

COMI

COMV

GATE

CS

R5

Q1

R6

C8 R10

R7

C7 R9

R2

C4

COMR

GND

Figure 41. Application Circuit FAN102 (5V/1A)

BOM List

Component

Symbol

R1

Symbol

D3

D4

C1

C2

C3

C4

C5

C6

C7

C8

C9

Diode 1A/1000V 1N4007

Diode 5A/60V SB560

Q1 1A/600V 1N60 TO-251

Resistor 1.5MΩ 1/2 W

Resistor 82KΩ 1%

Resistor 110KΩ 1%

Resistor 18KΩ 1%

Resistor 47Ω

R2

TR1

EE-16 Lm=1.5mH Pri:Sec:Aux=135:10:33

FAN102

R3

Electrolytic Capacitor 1µF/400V

Electrolytic Capacitor 10µF/400V

Electrolytic Capacitor 10µF/50V

MLCC 104pF

U1

R4

R5

R6

Resistor 100Ω

R7

MLCC X7R 22pF

Resistor 1.4Ω 1/4W 1%

Resistor 100KΩ 1/2W

Resistor 200KΩ

R8

Snubber Capacitor 472pF/1KV

MLCC X7R 683pF

R9

R10

R11

MLCC X7R 103pF

Resistor 47KΩ

MLCC 102pF/100V

Resistor 20Ω

Electrolytic Capacitor 560µF/10V

L-ESR

R12

R13

C10

C11

Resistor 510Ω

Electrolytic Capacitor 330µF/10V

L-ESR

WireWound Resistor 18Ω

Rectifier Diode 1N4007 *4

Diode 1A/200V FR103

BD1

D1

L1

L2

Inductor 1mH 1/2W

Inductor 5µH

Rev. 1.0.1 • 1/26/10

www.fairchildsemi.com

19

AN-6067

APPLICATION NOTE

Reference Circuits (Continued)

R8

C8

L2

R10

L1

D4

T1

BD1

R5

C5

D3

C1

C2

C9

C10

R9

R1

D1

C3

R2

R3

U1

VS

VDD

6

3

4

7

5

8

1

C4

COMI

COMV

DRAIN

C7 R7

CS

R4

C6 R6

R11

GND

COMR

2

C11

Figure 42. Application Circuit FSEZ1216 (5V/1A)

BOM List

Component

Symbol

R1

Symbol

D4

Symbol

U1

Diode 5A/60V SB560

FSEZ1216

Resistor 1.5M Ω

EE-16 Lm=1.5mH

Pri:Sec:Aux=135:10:33

R2

C1

Electrolytic Capacitor 1µF/400V

TR1

Resistor 110KΩ 1%

Resistor 18KΩ 1%

R3

R4

R5

C2

C3

C4

Electrolytic Capacitor 10µF/400V

Electrolytic Capacitor 10µF/50V

MLCC X7R 47pF

Resistor 1.4Ω 1/2W 1%

Resistor 100KΩ 1/2W

R6

R7

R8

R9

C5

C6

C7

C8

Snubber Capacitor 472pF/1KV

MLCC X7R 683pF

Resistor 200KΩ

Resistor 47KΩ

Resistor 47Ω

MLCC X7R 103pF

MLCC 102pF/100V

Resistor 510Ω

R10

R11

BD1

D1

C9

C10

C11

L1

Electrolytic Capacitor 560µF/10V

Electrolytic Capacitor 330µF/10V

MLCC X7R 104pF

WireWound Resistor 18Ω

Resistor 82KΩ 1%

Rectifier Diode 1N4007 *4

Diode 1A/200V FR103

Diode 1A/1000V 1N4007

Inductor 1mH

D3

L2

Inductor 5µH

Rev. 1.0.1 • 1/26/10

www.fairchildsemi.com

20

AN-6067

APPLICATION NOTE

Related Datasheets

FAN100 — Primary-Side Regulation PWM Controller

FAN102 — Primary-Side Regulation PWM Controller

FSEZ1016A — Primary-Side Regulation PWM with Integrated Power MOSFET

FSEZ1216 — Primary-Side Regulation PWM with Integrated Power MOSFET

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS

PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

Rev. 1.0.1 • 1/26/10

www.fairchildsemi.com

21


型号：	AN-6067
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Design and Application of Primary-Side Regulation (PSR) PWM Controller 设计与应用初级侧调节（ PSR ） PWM控制器控制器
文件：	总21页 (文件大小：932K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AN-6067 [FAIRCHILD]

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