AN-6027 [FAIRCHILD]
Design of Power Factor Correction Circuit; 功率因数校正电路的设计
| 型号： | AN-6027 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Design of Power Factor Correction Circuit |
| 文件： | 总16页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Application Note AN-6027
Design of Power Factor Correction Circuit Using FAN7530
1. Introduction
The FAN7530 is an active power factor correction (PFC)
controller for the boost PFC application that operates in the
critical conduction mode (CRM). The critical conduction
mode boost power factor converter operates at the boundary
of continuous conduction mode and discontinuous conduc-
tion mode. The CRM PFC controllers are of two kinds: the
current-mode CRM PFC controller and the voltage-mode
CRM PFC controller. For the current mode, a boost switch is
turned on when the inductor current reaches zero and turned
off when the inductor current meets the desired current refer-
ence. In this case, the rectified AC line voltage should be
sensed to generate the current reference, as in the
FAN7527B; however, the sensing network can cause addi-
tional power loss. In the voltage mode, the switch turn-on is
the same as that of the current mode, but the switch turn-off
is determined by an internal ramp signal. The ramp signal is
compared with an error amplifier output and the switch turn-
on time is controlled to be constant, as shown in Figure 1. If
the turn-on time is constant, the peak inductor current is pro-
portional to the rectified AC line voltage, as shown in Figure
2. In this way, the input current waveform follows the wave-
form of the input voltage, thereby obtaining a good power
factor. The FAN7530 is a voltage-mode CRM PFC control-
ler. Because the voltage-mode CRM PFC controller does not
need the rectified AC line voltage information, it can save
the power loss of the sensing network.
L
V
OUT
AC
IN
Turn-On
Q
OCP
Turn-Off
RSENSE
Feedback
OVP
Disable
Error Amp
Ramp
Figure 1. Voltage Mode CRM Boost PFC Circuit
Diode
Peak Inductor
Current
Conduction
Inductor
Current
Average
Input
Current
MOSFET
Conduction
Gating
Signal
Constant On-time & Variable Off-time
Figure 2. CRM Boost PFC Inductor Current Waveform
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.3 • 1/11/07
AN6027
APPLICATION NOTE
Figure 3 shows the block diagram of the FAN7530. The only
difference between the FAN7529 and the FAN7530 is the pin
configuration of pin 2 and pin 3. For the FAN7529, the INV
pin and the COMP pin are adjacent, but because the voltage
of pin 1 is 2.5V and the operating range of pin 2 is from 1V
to 5V, the PFC output voltage can increase at light load if
pins 1 and 2 are shorted. For the FAN7530, however, the INV
pin and the MOT pin are adjacent. Because the voltage of the
MOT pin is 2.9V, the over-voltage protection works if pin 1
and pin 2 are shorted.
Block Diagram
2.5V
Vref
VCC
8
Ref
VCC
UVLO
Internal
Bias
Drive
Output
7
OUT
8.5V
12V
Disable
150μs
13V
Timer
5
ZCD
S
Q
6.5V
1.4V 1.5V
R
Zero Current
Detector
OVP
2.5V
2.675V
4
CS
Disable
40k
0.45V 0.35V
8pF
0.8V
Current Protection
Comparator
Ramp
Signal
Vref
1V Offset
Error
Amplifier
Sawtooth
Generator
MOT
2
Gm
1
INV
1V~5V
Range
6
3
GND
COMP
Figure 3. Block Diagram of the FAN7530 Showing Error Amplifier Block, Zero Current Detector Block, Sawtooth
Generator Block, Over-Current Protection Block, and Switch Drive Block
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.3 • 1/11/07
2
AN6027
APPLICATION NOTE
the junction capacitor of the MOSFET resonates with the
boost inductor and the auxiliary winding voltage decreases
resonantly. If it reaches 1.4V, the zero current detector turns
on the MOSFET. The ZCD pin is protected internally by two
clamps: the 6.5V HIGH clamp and the 0.65V LOW clamp,
as shown in Figure 5.
2. Device Block Description
2.1 Error Amplifier Block
The error amplifier block consists of a transconductance
amplifier, output OVP comparator, and disable comparator.
For the output voltage control, a transconductance amplifier
is used instead of the conventional voltage amplifier. The
transconductance amplifier (voltage controlled current
source) aids the implementation of OVP and disable func-
tion. The output current of the amplifier changes according
to the voltage difference of the inverting input and the non-
inverting input of the amplifier. The output voltage of the
amplifier is compared with the internal ramp signal to gener-
ate the switch turn-off signal. The OVP comparator shuts
down the output drive block when the voltage of the INV pin
is higher than 2.675V and there is 0.175V hysteresis. The
disable comparator disables the operation of the FAN7530
when the voltage of the inverting input is lower than 0.45V
and there is 100mV hysteresis. An external, small-signal
MOSFET can be used to disable the IC, as shown in Figure
4. The IC operating current decreases to under 65µA to
reduce power consumption if the IC is disabled.
Turn-on
Signal
Timer
S
Q
R
V
IN
ZCD
5
1.5V
1.4V
6.5V
Zero Current
Detector
Figure 5. Zero Current Detector Block
2.675V 2.5V
OVP
Figure 6 shows typical ZCD-related waveforms. Because the
ZCD pin has some capacitance, there can be some delay
caused by R and the turn-on time can be delayed.
zcd
Disable
IPEAK
0.45V 0.35V
tzero
Inductor
Current
0A
VOUT
Vref (2.5V)
ton tdis
INEG
Error
Amp
toff
INV
Gm
n·(VOUT-VIN)
1
Disable
Signal
2
VAUX
COMP
0V
-n·VIN
Delay Time
Vclamp
Figure 4. Error Amplifier Block
ZCD
Voltage
Vth
0V
RZCD Delay
2.2 Zero Current Detection Block
OUT
VDS
The zero current detector (ZCD) generates the turn-on signal
of the MOSFET when the boost inductor current reaches
zero using an auxiliary winding coupled with the inductor.
Because the polarity of the auxiliary winding is opposite the
inductor winding, the auxiliary winding voltage is negative
and proportional to the rectified AC line voltage when the
MOSFET is turned on. If the MOSFET is turned off, the
voltage becomes positive and proportional to the difference
VOUT
Minimum
Voltage Turn-on
0V
Figure 6. Zero Current Detector Waveform
between V
and V . If the inductor current reaches zero,
OUT
IN
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.3 • 1/11/07
3
AN6027
APPLICATION NOTE
Ideally, the switch must be turned on when the inductor cur-
rent reaches zero; but because of the structure of the ZCD
Off Signal
1V Offset
block and R delay, it is turned on after some delay time.
MOT
zcd
Sawtooth
Generator
During this delay time, the stored charge of the C
(MOS-
3
OSS
FET output capacitor) is discharged through the path indi-
cated in Figure 7. This charge is transferred into a small filter
2.9V
capacitor, C , which is connected to the bridge diode.
Therefore, there is no current flow from the input side,
in1
Error Amp
Output
meaning the input current I is zero during this period. For
in
better total harmonic distortion (THD), it is important to
Figure 8. Sawtooth Generator Block
make t
/ T as small as possible. As shown in Figure 6,
zero
S
L ⋅ C
t
is proportional to
but t and t are propor-
on dis
zero
oss
2.4 Over-Current Protection Block
tional to L. Therefore t
proportional to
/ T is approximately inversely
zero
S
The MOSFET current is sensed using an external sense
resistor for over-current protection. If the CS pin voltage is
higher than 0.8V, the over-current protection comparator
generates a protection signal to turn off the MOSFET. An
internal R/C filter has been included to filter switching noise.
L
. Therefore THD increases as the induc-
tance decreases. Reducing the inductance can decrease the
inductor size and cost but the switching loss increases
because of the increased switching frequency. In real case,
boost diode’s junction capacitance and boost inductor’s para-
sitic capacitance should be added to C
when calculating
OSS
t
. That means it is important to minimize the parasitic
zero
OCP
Signal
4
capacitance of the boost inductor and diode junction capaci-
tance for better THD.
CS
40k
8pF
0.8V
O ver-Current
Protection
Com parator
iin
L
D
VOUT
AC
IN
iL
CIN1
Q
CO
Figure 9. Over-Current Protection Block
COSS
2.5 Switch Drive Block
The FAN7530 contains a single totem-pole output stage
designed specifically for a direct drive of a power MOSFET.
The drive output is capable of up to 500mA peak sourcing
current and 800mA peak sinking current with a typical rise
and fall time of 50ns with a 1.0nF load. Additional circuitry
has been added to keep the drive output in a sinking mode
whenever the UVLO is active. The output voltage is
clamped at 13V to protect the MOSFET gate even when the
Figure 7. Current Flow During tzero
In the ZCD block, there is an internal timer to provide a
means to start or restart the switching if the drive output has
been low for more than 150µs from the falling edge of the
drive output. Without this timer, the PFC converter does not
work because the inductor current is always zero when the
IC initially starts operation and the ZCD winding voltage
does not become positive without any switching.
V
voltage is higher than 13V.
CC
2.3 Sawtooth Generator Block
The output of the error amplifier and the output of the saw-
tooth generator are compared to determine the MOSFET
turn-off instant. The slope of the sawtooth is determined by
an external resistor connected at the maximum on time
(MOT) pin. The voltage of the MOT pin is 2.9V and the
slope is proportional to the current flowing output of the
MOT pin. The maximum on time is determined when the
output of the error amplifier is 5V. When a 40.5kΩ resistor is
connected, the maximum on time is 24µs. As the resistance
increases, the maximum on time increases, because the slope
decreases. The MOSFET on time is zero when the output of
the error amplifier is lower than 1V.
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.3 • 1/11/07
4
AN6027
APPLICATION NOTE
3.Circuit Components Design
2
η ⋅Vin(peak )
3.1 Power Stage Design
L =
(6)
⎛
⎞
Vin(peak )
1) Boost Inductor Design
4 ⋅ fsw (min) ⋅Vo ⋅ Io(max) 1+
⎜
⎟
⎟
⎠
⎜
⎝
Vo −Vin(peak )
The boost inductor value is determined by the output power
and the minimum switching frequency. The minimum
switching frequency must be above the audio frequency
(20kHz) to prevent audible noise. The maximum switching
2) Auxiliary Winding Design
The auxiliary winding voltage is lowest at the highest line.
So the turn number of the auxiliary winding can be obtained
by Equation 7. The voltage should be higher than the ZCD
threshold voltage of 1.5V.
period, T
is a function of V
and V , the output
S(max),
in(peak) o
voltage. It can have a maximum value at the highest input
voltage or at the lowest input voltage according to V . Com-
o
pare T
at V
and V
, then select the
S(max)
in(peak_min)
in(peak_max)
higher value for the maximum switching period. The boost
inductor value can be obtained by Equation 6.
1.5V ⋅NP
Naux
>
(7)
(Vo − 2V
)
in(peak _max)
I
L(peak)(t)
2⋅Iin(peak) sin(ωt)
ton = L ⋅
= L ⋅
(1)
3) Input Capacitor Design
The voltage ripple of the input capacitor is maximum when
the line is lowest and the load is heaviest. If f >> f ,
the input current can be assumed to be constant during a
switching period.
V
in(peak) sin(ωt)
Vin(peak) sin(ωt)
2⋅Iin(peak)
sw(min)
ac
= L ⋅
V
in(peak)
Inductor
Current
2⋅ Iin
I
L(peak)(t)
toff = L ⋅
= L ⋅
(2)
Vo −Vin(peak) sin(ωt)
2⋅Iin(peak) sin(ωt)
Input
Current
Iin
Vo −Vin(peak) sin(ωt)
ton / 2
2⋅Vo ⋅Io
Iin(peak)
=
(3)
(4)
η ⋅V
in(peak)
toff
ton
Figure 10. Input Current and Inductor Current Waveform
During a Switch Cycle
TS = ton + toff
= 2⋅L ⋅Iin(peak)
⎛
⎞
1
sin(ωt)
Vo −Vin(peak) sin(ωt)
+
⎜
⎜
⎝
⎟
⎟
⎠
V
in(peak)
ton
Iin(peak _max)
⎛
⎞
2
2
Cin
≥
≥
I
− 2
t dt
⎜
⎜
⎟
in(peak _max)
∫
0
⎛
⎞
V
in(peak) ⋅ sin(ωt)
⎟
4⋅L ⋅Vo ⋅Io
ΔV
ton
in(max)
⎝
⎠
=
1+
⎜
⎟
⎟
⎠
2
⎜
Vo −Vin(peak) sin(ωt)
η ⋅V
in(peak)
ton ⋅Iin(peak _max)
2⋅ ΔVin(max)
L ⋅Io2(max) ⋅Vo2
ΔVin(max) ⋅V3
⎝
(8)
≥
⎛
⎞
4 ⋅ L ⋅Vo ⋅ Io(max)
Vin(peak )
TS(max)
=
1+
(5)
⎜
⎜
⎝
⎟
⎟
⎠
in(peak _min)
2
Vo −Vin(peak )
η ⋅Vin(peak )
The input capacitor must be larger than the value calculated
by Equation 8 and the maximum input capacitance is limited
by the input displacement factor (IDF), defined as IDF≡cosθ.
As shown in Figure 11, the input capacitor generates 90°
© 2006 Fairchild Semiconductor Corporation
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Rev. 1.0.3 • 1/11/07
5
AN6027
APPLICATION NOTE
4) Output Capacitor Design
leading current, which causes phase difference between the
line current and the line voltage. The phase difference
increases as the capacitance of the input capacitor increases.
Therefore, the input capacitor must be smaller than Cin(max)
calculated by Equation 12. Cin(max) is the sum of all the
capacitors connected at the input side.
The output capacitor is selected by the relationship between
the input and output power. As shown in Figure 13, the min-
imum output capacitance is determined by Equation 14.
IIN
ID
IO
PFC
Va = VA = Vin(peak) cos(ωt)
(9)
+
+
VO
CO
V
IN
ia = Ia cos(ωt)
iA = ia + ic = Ia cos(ωt) − ω ⋅Cin ⋅Vin(peak) sin(ωt) (10)
Figure 12. PFC Configuration
ω ⋅C ⋅V
⎛
⎞
in
in(peak)
θ = tan−1
(11)
⎜
⎜
⎟
⎟
Ia
P = Iin(rms) ⋅V
⋅ 1− cos(2ωt) = I V
(
)
1− cos(2ωt)
)
⎝
⎠
in
in(rms)
D
o
Ia
Iin(rms) ⋅Vin(rms)
Cin(max)
=
tan cos−1(IDF)
(
)
ID
=
(
)
ω ⋅V
in(peak)
Vo
2⋅Vo ⋅Io
=
tan cos−1(IDF) (12)
= I ⋅ 1− cos(2ωt)
(13)
(
o
(
)
ω ⋅V 2
in(peak _max)
ID(avg) = IO (1- cos(2ωt))
L
iA
ia
in
IO
iC
+
VA
−
+
PFC
Circuit
C
Va
IO
in
ΔVO
=
ωCO
−
VO
Input Filter
Figure 13. Diode Current and Output Voltage Waveform
Im
iA
Io(max)
Co(min)
≥
(14)
2π ⋅fac ⋅ ΔVo(max)
iC
ia
VA
5) MOSFET and Diode Selection
θ
Re
The maximum MOSFET RMS current is obtained by Equa-
tion 15 and the conduction loss of the MOSFET is calculated
by Equation 16. When MOSFET turns on, the MOSFET cur-
rent rises from zero, so the turn-on loss is negligible. The
MOSFET turn-off loss and the MOSFET discharge loss are
obtained by Equations 17 and 18, respectively. The switch-
ing frequency of the critical conduction mode boost PFC
converter varies according to the line and load conditions.
Figure 11. Input Voltage and Current Displacement Due to
Input Filter Capacitance
© 2006 Fairchild Semiconductor Corporation
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Rev. 1.0.3 • 1/11/07
6
AN6027
APPLICATION NOTE
The switching frequency is the average value during a line
period. The total MOSFET loss can be calculated by Equa-
tion 19 and a MOSFET can be selected considering the
MOSFET thermal characteristic.
PFC OUT
Ro1
4 2 ⋅Vin(LL)
9π ⋅Vo
1
6
IQrms = IL(peak _max)
−
INV
1
Cp
2 2 ⋅Vo ⋅Io(max)
4 2 ⋅Vin(LL)
1
6
Ro2
=
−
(15)
(16)
η ⋅V
9π ⋅Vo
in(LL)
P
= IQ2rms ⋅RDSon
on
1
6
Figure 14. Output Voltage Sensing Circuit
P
=
=
Vo ⋅IL(peak _max) ⋅tf ⋅fsw
turn−off
V 2 ⋅I
2
o
o(max)
in(LL)
⋅tf ⋅fsw
(17)
The feedback loop bandwidth must be lower than 20Hz for
the PFC application. If the bandwidth is higher than 20Hz,
the control loop may try to reduce the 120Hz ripple of the
output voltage and the line current may be distorted, decreas-
ing the power factor. A capacitor is connected between
COMP and GND to eliminate the 120Hz ripple voltage by
40dB. If a capacitor is connected between the output of the
error amplifier and the GND, the error amplifier works as an
integrator and the error amplifier compensation capacitor
can be calculated by Equation 23. To improve the power fac-
tor, Ccomp must be higher than the calculated value. If the
value is too high, the output voltage control loop may
become slow.
3
η ⋅V
4
P
=
Coss.Vo ⋅Vo2 ⋅fsw
(18)
(19)
discharge
3
PMOSFET = P + P
+ P
disch arge
on
turn−off
The diode average current can be calculated by Equation 20.
The total diode loss can be calculated by Equation 21. Select
a diode considering diode thermal characteristic.
IDavg = Io(max)
(20)
(21)
PDiode = V ⋅IDavg
f
Ro2
Ccomp = gm⋅
(23)
0.01⋅2π ⋅120Hz ⋅(Ro1 + Ro2 )
3.2 Control Circuit Design
1) Output Voltage Sensing Resistor and Feedback Loop
Design
To improve the output voltage regulation, a resistor and a
capacitor can be added to a simple integrator, as shown in
Figure 15. The resistor, Rcomp, increases mid-band gain and
the capacitor, Cfilter, which is 1/10~1/5 of the Ccomp, is used
to filter high-frequency noise. The gain of the error amplifier
with the circuit in Figure 15 is shown in Figure 16.
The output voltage sensing resistors, Ro1 and Ro2, are deter-
mined by the output voltage at the high line by Equation 22.
The output voltage sensing resistors cause power loss, there-
fore Ro1 should be higher than 1MΩ. Too high resistance can
cause some delay of the OVP circuit due to internal capaci-
tance (Cp), which may slightly increase the OVP level.
Vo _ high − 2.5
Ro1
Ro2
=
(22)
2.5
© 2006 Fairchild Semiconductor Corporation
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Rev. 1.0.3 • 1/11/07
7
AN6027
APPLICATION NOTE
crossing point of the AC line, as shown in Figure 18. To min-
imize the zero crossing distortion, COSS must be minimized
and a larger inductor should be used. There is a limitation in
minimizing COSS and using a large inductor because a small
MOSFET increases MOSFET conduction loss and a larger
inductor is more expensive.
VOUT
Error
Amp
Ro1
INV
1
Gm
Ro2
Vref
Coss
INEG
=
⋅(Vo −V )
(25)
in
L
3
COMP
Cfilter
IPEAK
tzero
Rcomp
Ccomp
Inductor
Current
0A
ton tdis
INEG
Figure 15. Error Amplifier Circuit
toff
n·(VOUT-VIN)
VAUX
0V
Integrator
Ccomp
-n·VIN
Proportional gain
Rcomp
Delay Time
RZCD Delay
Freq
Vclamp
ZCD
Voltage
Cfilter
Vth
0V
High frequency
Noise filter
OUT
Figure 16. Gain of the Error Amplifier
Figure 17. ZCD Waveforms
2) Zero Current Detection Resistor Design
If the RZCD is selected appropriately, the MOSFET can be
turned on when the Vds voltage is minimum to reduce
switching loss. It is recommended to design the RZCD to turn
on the MOSFET when the Vds voltage is minimum.
The ZCD current should be less than 10mA; therefore the
zero current detection resistor, RZCD is determined by Equa-
tion 24.
To improve the zero crossing distortion, the MOSFET turn-
on time should be increased near the AC line zero crossing
point. If a resistor is connected between the MOT and the
auxiliary winding, as shown in Figure 19, the function can be
implemented easily. Because the auxiliary winding voltage is
negatively proportional to the input voltage during the MOS-
FET turn-on time, the current I2 is proportional to the input
voltage (as shown in Figure 19). Therefore, the slope of the
internal ramp changes according to input voltage as the cur-
rent flowing out of the MOT pin changes, as shown in Figure
20. I2 current is maximum at the highest line voltage and the
zero crossing improvement is best when I2 is 100% ~ 200%
of I1. R2 value should be chosen by experiment.
⎛
⎞
⎟
⎠
Naux ⋅Vo
RZCD
=
− 5.8V /10mA
(24)
⎜
⎜
⎝
⎟
Np
Because the ZCD pin has some capacitance, the ZCD resis-
tor and the capacitor cause some delay for ZCD detection, as
shown in Figure 17. Because of this delay, the MOSFET is
not turned on when the inductor current reaches zero and the
MOSFET junction capacitor and the inductor resonate. The
inductor current changes its direction and flows negatively.
The peak value of this negative current is determined by
Equation 25. As shown in Equation 25, the negative current
increases as the input voltage is close to zero and COSS
increases. This negative current decreases average inductor
current and causes zero crossing distortion near the zero
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.3 • 1/11/07
8
AN6027
APPLICATION NOTE
3) Start-up Circuit Design
To start up the FAN7530, the start-up current must be sup-
plied through a start-up resistor. The resistor value is calcu-
lated by Equations 26 and 27. The start-up capacitor must
supply IC operating current before the auxiliary winding
supplies IC operating current, maintaining VCC voltage
higher than the UVLO voltage. The start-up capacitor is
determined by Equation 28.
Output
Voltage
1st
Input
Current
Vin(peak _min) −V
3rd
5th
th(st )max
RST
≤
(26)
IST max
Vin2(rms _max)
PR
=
≤ 1W
(27)
(28)
ST
RST
Idcc
CST
≥
Figure 18. Zero Crossing Distortion
2π ⋅fac ⋅HY
(ST )min
4) Current Sense Resistor Design
The CS pin voltage is highest when the AC line voltage is
lowest and the output power is maximum. The current sense
resistor is determined by Equations 29 and 31, limiting the
power loss of the resistor to under 1W.
L
D
VO
AC
IN
NAUX
VAUX
R2
RZCD
ZCD
I2
η ⋅V
0.8V
in(peak _min)
Rsense
<
= 0.8V
(29)
(30)
(31)
IL(peak _max)
4⋅Vo ⋅Io(max)
CO
VCC
2
FAN7529
⎛
⎞
Vo ⋅Io(max)
INV
PR
= 2⋅
⋅Rsense < 1W
⎜
⎜
⎝
⎟
⎟
⎠
MOT
I1
sense
η ⋅V
in(peak _min)
CS
COMP
R1
2
⎛
⎞
η ⋅V
1
2
in(peak _min)
Rsense
<
⋅
⎜
⎜
⎝
⎟
⎟
⎠
Vo ⋅Io(max)
GND
Figure 19. Zero Crossing Improvement Circuit
Ramp Slope
Change
Slope
Decrease
VAC
Slope Increase
VEAO
Ramp
Variable On-time
On-time Increase
On-time Decrease
Figure 20. On-Time Variation According to VAC
© 2006 Fairchild Semiconductor Corporation
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Rev. 1.0.3 • 1/11/07
9
AN6027
APPLICATION NOTE
ZCD pin and the ground to increase the delay time for the
MOSFET minimum voltage turn-on.
4. Design Example
A 100W converter is used here to illustrate the design proce-
dure using a design spreadsheet. Enter the system parameters
in the file to get the designed parameters. The system param-
eters are as follows:
4.7 Start-up Circuit Design
The maximum start-up resistor is 1.63MΩ and the minimum
is 140kΩ, as determined by Equations 26-27. The selection
is 330kΩ. The VCC capacitance must be larger than 7µF, cal-
culated by Equation 28, so the selected value is 47µF.
• Maximum output power
• Input voltage range
100W
90Vrms~264Vrms
• Output voltage
• AC line frequency
• PFC efficiency
• Minimum switching frequency
• Input displacement factor (IDF)
• Input capacitor ripple voltage
• Output voltage ripple
392V
60Hz
90%
37kHz
0.98
4.8 Current Sense Resistor Design
The maximum current sense resistance is 0.23Ω as a result
of Equation 31 and the selected value is 0.2Ω.
24V
8V
4.9 MOT Resistor Design
The MOT resistor is determined to get the maximum on-time
when the AC line voltage is lowest and the output power is
maximum. The calculated value is 20.44kΩ and the maxi-
mum on-time is 12.26µs. To improve THD performance, a
33kΩ resistor is used for the MOT resistor and a 370kΩ
resistor is connected between the MOT pin and the auxiliary
winding. The maximum on-time is determined by Equation
32 and the MOT resistor is determined by Equation 33.
4.1 Inductor Design
The boost inductor is determined by Equation 6. Calculate it
at both the lowest voltage and the highest voltage of the AC
line and choose the lower value. The calculated value in this
example is 403µH. To get the calculated inductor value,
EI30 core is used and the primary winding is 44 turns. The
air gap is 0.6mm at both legs of the EI core. The auxiliary
winding number, determined by Equation 7, is five; but if
more windings are used, the number is six.
2⋅L ⋅P
o
MOT =
⋅10−6
(32)
(33)
η ⋅V2
in(rms _min)
4.2 Input Capacitor Design
MOT
RMOT
>
×1012
The minimum input capacitance is determined by the input
voltage ripple specification. The calculated minimum input
capacitor value is 0.33µF. The maximum input capacitance
is restricted by the IDF. The calculated value is 0.77µF. The
selected value is 0.63µF (sum of all the capacitors connected
to the input side, C1, C2, C3, C4, and C5).
600
4.10 MOSFET Gate Drive Resistor Design
As shown in Figure 21, noise voltage can be added to the
internal ramp signal during MOSFET turn-on. Because of
this noise, the AC line current waveform can be distorted if
the error amplifier output voltage is close to 1V. It is recom-
mended to use higher resistor for MOSFET turn-on if there
is waveform distortion and use a turn-off diode to speed up
the turn-off process.
4.3 Output Capacitor Design
The minimum output capacitor is determined by Equation 14
and the calculated value is 85µF. The selected value for the
capacitor is 100µF.
4.4 MOSFET and Diode Selection
By calculating Equations 15-19, a 500V/13A MOSFET
FQPF13N50C is selected, and a 600V/1A diode BYV26C is
selected by the result of Equations 20-21.
Error Amp. Output
4.5 Output Voltage Sense Resistor and
Feedback Loop Design
Internal
Ramp Signal
Switching
Nosie
The upper output voltage sense resistor is chosen to be 2MΩ
and the bottom output voltage sense resistor is 12.6kΩ. The
error amplifier compensation capacitance must be larger
than 0.1µF, as calculated by Equation 23. Therefore, 0.22µF
capacitor is used.
IC OUT Signal
Figure 21. Turn-on Noise on Internal Ramp Signal
Figure 22 shows the designed application circuit diagram and
Table 2 shows the 100W demo board components list.
4.6 Zero Current Detection Resistor Design
The calculated value is 3.1kΩ and the selected value is
20kΩ. A 47pF ceramic capacitor is connected between the
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.3 • 1/11/07
10
AN6027
APPLICATION NOTE
T1
PFC OUTPUT
VAUX
D2
BD
C5
R4
R3
R5
R10
C9
D3
R6
C10
Q1
NTC
ZD1
C11
D1
C3 C4
C2
LF1
F1
FAN7530
R2
C1
V1
R11
R1
R8
C8
R7
C7
C6
AC INPUT
Figure 22. Application Circuit Schematic
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.3 • 1/11/07
11
AN6027
APPLICATION NOTE
Table 2. 100W Demo Board Part List
PART#
VALUE
Fuse
NOTE
PART#
VALUE
Capacitor
150nF/275V
NOTE
F1
250V/3A
TNR
C1
C2
Box Capacitor
AC
470nF/275V
Box Capacitor
Ceramic Capacitor
Electrolytic Capacitor
Ceramic Capacitor
MLCC
AC
V1
471
470V
C3,C4
C6
2.2nF/3kV
22µF/25V
47nF/50V
220nF
NTC
RT1
10D-9
Resistor
42kΩ
C7
C8
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
1/4W
1/4W
1/2W
1/2W
1/4W
1/4W
1/2W
1/4W
1/4W
1/4W
1/4W
C9
100µF/450V
12nF/100V
47pF/50V
Diode
Electrolytic Capacitor
Film Capacitor
370kΩ
330kΩ
150Ω
C10
C11
Ceramic Capacitor
20kΩ
BD
D1
KBL06
Fairchild
Fairchild
600V/1A
Fairchild
Fairchild
100Ω
1N4148
0.2Ω
D2
BYV26C
SB140
10kΩ
D3
10kΩ
ZD1
1N4746
2MΩ
Inductor
12.6kΩ
IC
T1
400µH(44T:6T)
EI3026
Primary: 0.2φ*10, from Pin 5 to Pin 3
Secondary: 0.2φ, from Pin 2 to Pin 4
MOSFET
IC1
FAN7530
Line Filter
38mH
LF1
Wire 0.45mm
Q1
FQPF13N50C
500V/13A
Table 3. Performance Data
PF
90V
110V
220V
264V
AC
AC
AC
AC
0.999
3.97%
90.3%
0.998
4.81%
90.1%
0.998
4.43%
92.7%
0.997
5.28%
90.8%
0.991
5.25%
94.7%
0.974
6.74%
91.7%
0.985
5.47%
95.2%
0.956
7.67%
92.5%
100W
THD
Efficiency
PF
50W
THD
Efficiency
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.3 • 1/11/07
12
AN6027
APPLICATION NOTE
Table 4. 200W Demo Board Part List (600µH, Wide Input Range Application)
PART#
VALUE
Fuse
NOTE
PART#
VALUE
Capacitor
470nF/275V
NOTE
F1
250V/5A
TNR
C1
C2
Box Capacitor
AC
470nF/275V
Box Capacitor
Ceramic Capacitor
Electrolytic Capacitor
Ceramic Capacitor
MLCC
AC
V1
471
470V
C3,C4
C6
2.2nF/3kV
47µF/25V
47nF/50V
220nF
NTC
RT1
10D-9
Resistor
37kΩ
C7
C8
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
1/4W
1/4W
1/2W
1/2W
1/4W
1/4W
1W
C9
220µF/450V
12nF/100V
47pF/50V
Diode
Electrolytic Capacitor
Film Capacitor
250kΩ
330kΩ
150Ω
C10
C11
Ceramic Capacitor
20kΩ
BD
D1
KBU8K
Fairchild
Fairchild
600V/3A
Fairchild
Fairchild
100Ω
1N4148
0.1Ω
D2
SUF30J
10kΩ
1/4W
1/4W
1/4W
1/4W
D3
SB140
10kΩ
ZD1
1N4746
2MΩ
Inductor
12.6kΩ
IC
T1
200µH(30T:3T)
PQ3230
Primary: 0.1φ*100, from Pin 5 to Pin 3
Secondary: 0.2φ, from Pin 2 to Pin 4
MOSFET
IC1
FAN7530
Line Filter
22mH
LF1
Wire 0.7mm
Q1
FDPF20N50
Fairchild
Table 5. Performance Data
PF
85V
115V
230V
265V
AC
AC
AC
AC
0.999
3.8%
0.998
4.3%
0.993
6.5%
0.990
6.5%
200W
150W
100W
THD
Efficiency
PF
91.8%
0.999
4.7%
94.8%
0.998
5.2%
96.9%
0.990
7.0%
97.3%
0.985
6.9%
THD
Efficiency
PF
93.3%
0.997
6.5%
95.5%
0.996
7.4%
96.9%
0.981
9.0%
97.0%
0.971
8.5%
THD
Efficiency
94.3%
95.3%
96.2%
96.0%
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.3 • 1/11/07
13
AN6027
APPLICATION NOTE
Table 6. 300W Wide Input Range Application Part List
PART#
VALUE
Fuse
NOTE
PART#
VALUE
Capacitor
NOTE
F1
250V/5A
TNR
C1
C2
680nF/275V
680nF/275V
Box Capacitor
AC
AC
Box Capacitor
Ceramic Capacitor
Electrolytic Capacitor
Ceramic Capacitor
MLCC
V1
471
470V
C3,C4
C6
2.2nF/3kV
47µF/25V
33nF/50V
220nF
NTC
RT1
6D-22
Resistor
60kΩ
C7
C8
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
1/4W
1/4W
1/2W
1/2W
1/4W
1/4W
1W
C9
33µF/450V
12nF/100V
9pF/50V
Diode
Electrolytic Capacitor
Film Capacitor
330kΩ
330kΩ
100Ω
C10
C11
Ceramic Capacitor
20kΩ
BD
D1
KBU8J
Fairchild
Fairchild
600V/3A
Fairchild
Fairchild
100Ω
1N4148
0.06Ω
10kΩ
D2
SUF30J
1/4W
1/4W
1/4W
1/4W
D3
SB140
10kΩ
ZD1
1N4746
2MΩ
Inductor
12.6kΩ
IC
T1
200µH(36T:3T)
PQ3535
Primary: 0.1φ, *100, from Pin 5 to Pin 3
Secondary: 0.2φ, from Pin 2 to Pin 4
MOSFET
IC1
FAN7530
Line Filter
40mH
LF1
Wire 1mm
Q1
FQA28N50
Fairchild
Table 7. Performance Data
PF
85V
115V
230V
265V
AC
AC
AC
AC
0.999
4.5%
0.998
4.7%
0.993
6.4%
0.988
6.5%
300W
225W
150W
75W
THD
Efficiency
PF
91.4%
0.999
3.9%
94.5%
0.998
4.7%
97.4%
0.989
6.1%
97.7%
0.982
6.2%
THD
Efficiency
PF
92.8%
0.998
4.8%
95.1%
0.997
5.8%
97.4%
0.978
7.4%
97.7%
0.963
7.4%
THD
Efficiency
PF
94.0%
0.994
9.3%
95.7%
0.989
10.8%
95.9%
97.0%
0.929
11.2%
95.3%
97.3%
0.885
12.0%
95.2%
THD
Efficiency
94.8%
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.3 • 1/11/07
14
AN6027
APPLICATION NOTE
Nomenclature
RST: start-up resistance
Rzcd: zero current detection resistance
tf: MOSFET current falling time
toff: switch off time
Ccomp: compensation capacitance
CIN: input capacitance
COUT: output capacitance
ton: switch on time
CST: start-up capacitance
TS: switching period
fac: AC line frequency
Vin (peak): input voltage peak value
fsw(max): maximum switching frequency
fsw(min): minimum switching frequency
fsw: switching frequency
Vin (peak_low): input voltage peak value at low line
Vin (peak_max): maximum input voltage peak value
Vin (peak_min): minimum input voltage peak value
Vin (rms): input voltage RMS value
HY(ST) min: minimum UVLO hysteresis
ID: boost diode current
Vin (rms_max): maximum input voltage RMS value
Vin (rms_min): minimum input voltage RMS value
Vin (t): input voltage
IDavg: diode average current
IDrms: diode RMS current
Iin (peak): input current peak value
Iin (peak_max): maximum of the input current peak value
Iin (rms): input current RMS value
Iin (t): input current
VO or VOUT: output voltage
ΔVin (max): maximum input voltage ripple
ΔVO (max): maximum output voltage ripple
η: converter efficiency
IL (t): inductor current
ω: AC line angular frequency
IL(peak) (t): inductor current peak value during one switching
cycle
IL(peak): inductor current peak value during one AC line
cycle
IL(peak_max): maximum inductor current peak value
IO (max): maximum output current
IO: output current
IQrms: MOSFET RMS current
ISTmax: maximum start-up supply current
L: boost inductance
Naux: auxiliary winding turn number
NP: boost inductor turn number
Pin: input power
PO(max): maximum output power
PO: output power
Rsense: current sense resistance
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.3 • 1/11/07
15
AN6027
APPLICATION NOTE
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used
herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or
(b) support or sustain life, or
(c) whose failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be reason
ably expected to result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.3 • 1/11/07
16
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