AN-6005 [FAIRCHILD]

MOSFET损耗计算,Synchronous buck MOSFET loss calculations with Excel model; MOSFET的损耗计算,同步降压MOSFET的损耗计算与Excel模型
AN-6005
型号: AN-6005
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

MOSFET损耗计算,Synchronous buck MOSFET loss calculations with Excel model
MOSFET的损耗计算,同步降压MOSFET的损耗计算与Excel模型

文件: 总7页 (文件大小:217K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
www.fairchildsemi.com  
AN-6005  
Synchronous buck MOSFET loss calculations  
with Excel model  
Jon Klein Power Management Applications  
Abstract  
The synchronous buck circuit is in widespread use to  
provide “point of use” high current, low voltage  
power for CPU’s, chipsets, peripherals etc.  
High-Side Losses:  
The power loss in any MOSFET is the combination  
of the switching losses and the MOSFET’s  
conduction losses.  
Typically used to convert from a 12V or 5V “bulk”  
supply, they provide outputs as low as 0.7V for low  
voltage CPUs made in sub-micron technologies.  
P
= P  
+ P  
COND  
(1)  
MOSFET  
SW  
Q1 (Figure 1) bears the brunt of the switching losses,  
since it swings the full input voltage with full current  
through it. In low duty cycle converters (for  
example: 12VIN to 1.8VOUT) switching losses tend to  
dominate.  
The majority of the power lost in the conversion  
process is due to losses in the power MOSFET  
switches. The profiles of loss for the High-Side and  
Low-Side MOSFET are quite different.  
These low output voltage converters have low duty  
cycles, concentrating the majority of the conduction  
loss in the low-side MOSFET.  
High-Side Conduction Losses:  
Calculating high-side conduction loss is  
straightforward as the conduction losses are just the  
I2R losses in the MOSFET times the MOSFET’s duty  
cycle:  
V IN  
High-Side  
Q1  
V
2
OUT  
P
= I  
R •  
DS(ON)  
(2)  
COND  
OUT  
V
IN  
L1  
SW NODE  
+
where RDS(ON) is @ the maximum operating  
MOSFET junction temperature (TJ(MAX) ).  
VOUT  
D1  
The maximum operating junction temperature is  
equation can be calculated by using an iterative  
technique. Since  
Low-Side  
Q2  
RDS(ON) rises with TJ and  
Figure 1. Synchronous Buck output stage  
TJ rises with PD (dissipated power) and  
PD is largely being determined by I2 x RDS(ON)  
The spreadsheet calculator iterates the die  
For the examples in the following discussion, we will  
be analyzing losses for the following synchronous  
buck converter:  
.
temperature and accounts for the MOSFET's positive  
RDS(ON) temperature coefficient. Iteration continues  
in the "DieTemp" custom function until the die  
temperature has stabilized to within 0.01°C.  
System Parameters  
VIN  
12  
1.5  
15  
V
V
VOUT  
IOUT  
FSW  
A
300  
kHz  
High-Side Switching Losses:  
The switching time is broken up into 5 periods (t1-t5)  
as illustrated in Figure 3. The top drawing in Figure  
3 shows the voltage across the MOSFET and the  
current through it. The bottom timing graph  
represents VGS as a function of time. The shape of  
this graph is identical to the shape of the QG curve  
contained in MOSFET datasheets, which assumes the  
gate is being driven with a constant current. The QG  
Table 1. Example Synchronous Buck  
A spreadsheet to aid in the estimation of synchronous  
buck losses is available on Fairchild’s web site on  
(click here to download):  
http://www.fairchildsemi.com/collateral/AN-  
6005.zip. Operation of the spreadsheet is described  
in the Appendix at the end of this document.  
1.0.1 01/04/2006  
Synchronous Buck Loss Calculation  
AN-6005  
notations indicate which QG is being charged during  
the corresponding time period.  
During this time the current is constant (at IOUT) and  
the voltage is falling fairly linearly from VIN to 0,  
therefore:  
VIN  
VDRIVE (VDD)  
V
I  
IN  
OUT  
D
E
= t3 •  
(4)  
t3  
CRSS  
RGATE  
CGS  
2
COSS  
RDRIVER  
During t4 and t5, the MOSFET is just fully  
HDRV  
SW  
G
S
enhancing the channel to obtain its rated RDS(ON) at a  
rated VGS. The losses during this time are very small  
compared to t2 and t3, when the MOSFET is  
simultaneously sustaining voltage and conducting  
current, so we can safely ignore them in the analysis.  
Figure 2. Drive Equivalent Circuit  
The switching loss for any given edge is just the  
power that occurs in each switching interval,  
multipied by the duty cycle of the switching interval:  
C
C
C
ISS  
ISS  
RSS  
VDS  
Switching losses  
are in Shaded  
section  
V
I  
IN  
OUT  
(
)
(
)
P
=
t2 + t3 F  
(5)  
(6)  
SW  
SW  
2
Now, all we need to determine are t2 and t3. Each  
period is determined by how long it takes the gate  
driver to deliver all of the charge required to move  
through that time period:  
ID  
Q
G(x)  
DRIVER  
VGS  
QGS  
QGD  
t
=
x
4.5V  
I
VSP  
VTH  
Most of the switching interval is spent in t3, which  
occurs at a voltage we refer to as “VSP”, or the  
“switching point” voltage. While this is not  
QG(SW )  
specifically specified in most MOSFET datasheets, it  
can be read from the Gate Charge graph, or  
approximated using the following equation:  
t1  
t2  
t3  
t4  
t5  
CISS = CGS + CRSS  
Figure 3. High-Side Switching losses and QG  
I
OUT  
V
V  
+
(7)  
SP  
TH  
G
M
The switching interval begins when the high-side  
MOSFET driver turns on and begins to supply  
current to Q1’s gate to charge its input capacitance.  
There are no switching losses until VGS reaches the  
MOSFET’s VTH. therefore Pt1 = 0.  
where GM is the MOSFET’s transconductance, and  
TH is its typical gate threshold voltage.  
V
With VSP known, the gate current can be determined  
by Ohm’s law on the circuit in Figure 2:  
When VGS reaches VTH, the input capacitance (CISS) is  
being charged and ID (the MOSFET’s drain current)  
is rising linearly until it reaches the current in L1 (IL)  
which is presumed to be IOUT. During this period (t2)  
the MOSFET is sustaining the entire input voltage  
across it, therefore, the energy in the MOSFET  
during t2 is:  
VDD - VSP  
IDRIVER(LH)  
=
=
(8A)  
RDRIVER(PULL-UP) + RGATE  
VSP  
IDRIVER(HL)  
(8B)  
RDRIVER(PULL-DOWN) + RGATE  
The rising time (L-H) and falling times (H-L) are  
treated separately, since IDRIVER can be different for  
each edge.  
V
I  
IN OUT  
E
= t2 •  
(3)  
t2  
2
The VGS excursion during t2 is from VTH to VSP.  
Now, we enter t3. At this point, IOUT is flowing  
Approximating this as VSP simplifies the calculation  
considerably and introduces no significant error.  
This approximation also allows us to use the QG(SW)  
term to represent the gate charge for a MOSFET to  
move through the switching interval. A few  
through Q1, and the VDS begins to fall. Now, all of  
the gate current will be going to recharge CGD. CGD is  
similar to the “Miller” capacitance of bipolar  
transistors, so t3 could be thought of as “Miller time”.  
2
1.0.1 01/04/2006  
AN-6005  
Synchronous Buck Loss Calculation  
MOSFET manufacturers specify QG(SW) on their data  
sheets. For those that don't, it can be approximated  
by:  
Driver dissipation calculates to :  
500 * 5  
2(8.5)  
P
=
=
= 147mW  
= 91mW  
(11E)  
DR(H-L)  
QGS  
QG(SW) QGD  
+
(9)  
500 * 2  
2(5.5)  
2
P
(11F)  
DR(L-H)  
so the switching times therefore are:  
P
= P  
+P = 238mW (11G)  
DR(L-H)  
DRIVER  
DR(H-L)  
Q
G(SW)  
t
t
=
=
(10A)  
(10B)  
S(LH)  
S(HL)  
I
DRIVER(L-H)  
2. The power to charge the MOSFET’s output  
capacitance:  
Q
G(SW)  
2
I
Coss V FSW  
DRIVER(H-L)  
IN  
PCOSS  
(11H)  
2
The switching loss discussion above can be  
summarized as:  
where COSS is the MOSFETs output capacitance,  
(CDS +CDG).  
V
IN XIOUT  
(
)
(
)
PSW  
=
FSW tS(L-H) + tS(HL) (10C)  
3. If an external schottky is used across Q2, the  
Schottky’s capacitance needs to be charged  
during the high-side MOSFET’s turn-on:  
2
There are several additional losses that are typically  
much smaller than the aforementioned losses.  
Although their proportional impact on efficiency is  
low, they can be significant because of where the  
dissipation occurs (for example, driver dissipation).  
They are listed in order of importance:  
2
CSCHOTTKY V FSW  
IN  
PC(SCHOTTKY)  
=
(12A)  
2
If a Schottky diode is not used:  
4. Reverse recover power for Q2’s body diode:  
1. The power to charge the gate:  
PQRR = QRR VIN FSW  
(12B)  
PGATE = QG X VDD XFSW  
(11A)  
where QRR is the body diode’s reverse recovery  
charge. If the MOSFET contains an integrated body  
diode (like SyncFET), the QRR figure in the  
datasheet is actually QOSS, or the charge required by  
the MOSFET’s COSS . If a SyncFETis used, then  
set QRR to 0 in the companion spreadsheet.  
Note that PGATE is the power from the VDD supply  
required to drive a MOSFET gate. It is independent  
of the driver's output resistance and includes both the  
rising and falling edges.  
P
GATE is distributed between RDRIVER, RGATE, and  
RDAMPING propoprtional to their resistances.  
Dissipation in the driver for the rising edge is:  
Low-Side Losses  
Low-side losses (PLS) are also comprised of  
conduction losses and switching losses.  
P
R  
DRIVER(PULL-UP)  
GATE  
P
=
(11B)  
(11C)  
DR(L-H)  
2(R  
)
TOTAL  
PLS = PSW + PCOND  
(13)  
where  
Switching losses are negligible, since Q2 switches on  
and off with only a diode drop across it, however for  
completeness we will include the analysis.  
RTOTAL = RDRIVER + RGATE + RDAMPING  
Similarly, dissipation in the driver for the falling edge  
is:  
Conduction losses for Q2 are given by:  
2
P
R  
DRIVER(PULL-DOWN)  
PCOND  
=
(
1D  
)
XIOUT XRDS(ON)  
(14)  
GATE  
P
=
(11D)  
DR(H-L)  
2(R  
)
TOTAL  
where RDS(ON) is the RDS(ON) of the MOSFET at the  
anticipated operating junction temperature and  
VOUT  
For an output stage (Driver + MOSFET) with the  
following parameters:  
D =  
is the duty cycle for the converter.  
VIN  
PGATE  
500 mW  
The junction temperature (TJ) of the MOSFET can be  
calculated if the junction to ambient thermal  
resistance (θJA) and maximum ambient temperature  
are known.  
RDRIVER (PULL-UP)  
RDRIVER (PULL-DOWN)  
RDAMPING  
5
2
2
RGATE  
1.5  
1.0.1 01/04/2006  
3
Synchronous Buck Loss Calculation  
AN-6005  
the RDS(ON) is typically 110% of the specified RDS(ON)  
.
TJ = TA + (PLS θJA  
)
(15)  
PCOND dominates PLS. Since RDS(ON) determines  
COND , and is a function of TJ, either an iterative  
The rising edge transition times for the low-side (t2  
and t3 in Figure 4) can now be calculated from the  
RC equations.  
P
calculation can be used, or TJ can be assumed to be  
some maximum number determined by the design  
goals. The calculations in the accompanying  
spreadsheet use TA and θJA iteratively to determine  
the low-side operating TJ at full current, assuming a  
MOSFET RDS(ON) temperature coefficient of  
0.4%/°C, which is typical for the MOSFETs used in  
this application.  
t2R = K2R(RDRIVER + RGATE )CISS  
(17A)  
where  
V
V
DRIVE  
DRIVE  
K
= ln  
ln  
(17B)  
(17C)  
2R  
V
V  
V
V  
DRIVE  
SP  
DRIVE TH  
t3R = K3R(RDRIVER + RGATE )CISS  
Low-side Switching Losses  
where  
C
ISS  
V
V
DRIVE  
DRIVE  
0.9V  
0
K
= ln  
ln  
3R  
V
V
V  
DRIVE  
SPEC  
DRIVE SP  
(17D)  
– IOUT  
x RDS(ON)  
ID  
and where CISS is the MOSFET’s input capacitance  
(CGS + CGD) when VDS is near 0V. If the MOSFET  
datasheet has no graph of capacitance vs. VDS, use  
1.25 times the typical CISS value, which is usually  
given with ½ of the rated VDS across the MOSFET.  
VDS  
0.6  
– IOUT  
t1  
t2  
t3  
The turn-off losses are the same, but in reverse, so  
the switching waveforms are:  
VDRIVER  
C
ISS  
0.9 x VSPEC  
0
VSP  
VGS  
– I x RDS(ON)  
VTH  
ID  
VDS  
0.6  
t
– I  
Figure 4. Low-Side turn-on switching loss  
waveforms  
t3  
t2  
t1  
VDRIVER  
Low-side switching losses for each edge can be  
calculated in a similar fashion to high-side switching  
losses:  
0.9 x VSPEC  
VSP  
VGS  
PSW(LS)  
VTH  
VF + IOUT 1.1RDS(ON)  
t2V + t3•  
IOUT Fsw  
F
2
(16)  
t
but instead of VIN as in eq. 3, we use VF , the schottky  
diode drop (approximated as 0.6V) in the equation.  
Also, there is almost no Miller effect for the low-side  
MOSFET, since VDS is increasing (becoming less  
negative) as we turn the device on, the gate driver is  
not having to supply charge to CGD. The voltage  
collapse for Q2 is caused by the RDS(ON) going from  
Figure 5. Low-Side turn-off switching loss  
waveforms  
The falling edge transition times for the low-side  
(t3 and t2 in Figure 5) can now be calculated from the  
RC equations:  
t3F = K3F (RDRIVER + RGATE )CISS  
(18A)  
0.6  
@ VGS = VSP, to 90% of VSPEC, the gate voltage  
where  
IOUT  
for the highest specified RDS(ON) . At 90% of VSPEC  
4
1.0.1 01/04/2006  
AN-6005  
Synchronous Buck Loss Calculation  
Q
0.9VSPEC  
VSP  
GS  
t
(20)  
K3 = ln  
(18B)  
(18C)  
TH  
F
2 I  
LDRV  
This approximation holds, since prior to reaching  
threshold, the gate voltage is low enough that ILDRV  
can be approximated with a constant current of  
t2F = K2F (RDRIVER + RGATE )CISS  
where  
VSP  
K2 = ln  
(18D)  
V
F
TH  
V
VDRIVER − ⎜  
TH  
2
ILDRV  
(21)  
RGATE + RDRIVER  
Dead-Time (Diode Conduction) Losses  
The dead-time is the amount of time that both  
QGS  
and typically QG(TH)  
.
MOSFETs are off. During this time the diode (body  
diode or parallel schottky diode) is in forward  
conduction. It's power loss is:  
2
The diode's total on-time on the falling edge is then:  
(
)
Q
R
+ R  
P
= t  
F V I  
OUT  
(19)  
GS GATE  
DRIVER  
DIODE  
DEADTIME  
SW  
F
t
t  
+
DELAY(F)  
DEADTIME(F)  
V
TH  
where tDEADTIME = tDEADTIME(R) + tDEADTIME(F), which  
are the deadtimes associated before the SW Node  
(Figure 1) rises, after Q2 turns off, and after SW  
Node falls, before Q2 turns on, respectively.  
V
DRIVER  
2
(22)  
On the rising edge, tDELAY(R) is usually much longer to  
allow the low-side MOSFET’s gate to discharge  
completely. This is necessary since charge is coupled  
into the low-side gate during the rising edge of the  
SW node. The peak of the resultant voltage “spike”  
at the low-side gate is the sum of the amplitude of the  
injected spike and the voltage the gate has discharged  
to when the SW node begins to rise. Sufficient delay  
is necessary to avoid having the resultant peak rise  
significantly above the low-side’s VTH , turning on  
both MOSFETs, and inducing “shoot-through”  
losses.  
To determine tDEADTIME, we need to consider how the  
driver controls the MOSFET gate drives. Most  
drivers use "adaptive dead-time circuits, which wait  
for the voltage of the opposite MOSFET to reach an  
"off" voltage before beginning to charge its own  
MOSFET. Most drivers add a fixed delay to prevent  
shoot-through, especially on the low to high  
transition.  
HDRV  
H.S. MOSFET  
CGD  
40nS  
6
5
4
3
2
1
0
14  
12  
10  
8
LDRV  
RGATE  
CGS  
1V  
G
SW NODE VOLTAGE  
RDamping  
RDRIVER  
LS MOSFET GATE  
6
4
2
Figure 6. Typical Adaptive Gate drive (low-high  
transition)  
0
-2  
For the tDEADTIME(F) the diode will be conducting the  
full load current from the time the switch node falls,  
until the Low-side MOSFET reaches threshold. This  
"deadtime" consists of 2 portions:  
0
20  
40  
60  
80  
t (nS)  
Figure 7. Coupled voltage spike on Low-side  
MOSFET gate from SW node rising edge  
1. tDELAY(F) : The driver’s built in delay time from  
detection of 1VGS at the high-side MOSFET  
gate until beginning of low-side MOSFET turn-  
on, plus  
The other component of deadtime on the rising edge  
is the time it takes for the high-side MOSFET’s gate  
to charge to VSP. This is typically less than 10% of  
tDELAY(R) so we will ignore it and set:  
2.  
tTH : the time for the driver to charge the low-  
side MOSFET's gate to reach threshold (VTH).  
tDEADTIME(R) tDELAY(R)  
(23)  
tTH can be approximated by:  
1.0.1 01/04/2006  
5
Synchronous Buck Loss Calculation  
AN-6005  
Summary of results  
A spreadsheet which contains MOSFET parameters  
is used to compute the losses for our example circuit  
(Table 1) using a 5V gate drive with 6pull-up and  
2pull-down strength.  
High-Side Low-Side  
MOSFET  
FDD6644 FDB6676 Total  
Switching Loss  
Conduction Loss  
Other Losses  
Total Losses  
Output Power  
Efficiency  
1.09  
0.21  
0.31  
1.15  
W
W
W
W
W
1.40  
1.36  
0.26  
3.02  
22.5  
88%  
1.30  
1.46  
Table 2. Results for 15A example (Table 1)  
It’s instructive to review the results in order to  
observe a few key points:  
Switching losses for the low-side MOSFET are  
only 15% of low-side MOSFET’s total losses.  
Unless the switching frequency is very high  
(above 1 Mhz.), the loss contribution due to  
diode conduction (deadtime loss) is minimal.  
High-side losses are dominated by switching  
losses since the duty cycle is low.  
6
1.0.1 01/04/2006  
AN-6005  
Synchronous Buck Loss Calculation  
Appendix: Using the efficiency and loss calculation spreadsheet tool  
The spreadsheet is contained in the following file:  
http://www.fairchildsemi.com/collateral/AN-6005.zip  
The spreadsheet implements the loss calculations described in this app note. To see the sheet in action press the  
"Run" button on the "EfficiencySummary" sheet.  
The controller/driver database models several Fairchild products driver products. A listing of these is found in the  
ControllerDriver tab.  
These detailed instructions can also be found in the " General Instructions" tab of the spreadsheet:  
Be sure to turn off Macro Protection in Excel to allow the custom functions and macros in this sheet to run.  
For Excel 2000, this is done through "Tools|Macro|Security". Set the level to "low".  
In Excel 97, you can do this through "Tools|Options. In the "General" tab, the "Macro Virus Protection" box  
should not be checked.  
Notes:  
RDS(ON) is a function of die temperature, and the die temperature is a function of Power Dissipation which is in  
turn dependent on RDS(ON). To solve for dissipation or die temperature, the conduction loss calculations in  
this spreadsheet use an iterative calculation method to arrive at the die temperature and dissipation.  
DieTemp function  
Tabs  
Function / Description  
Provides guidance on what MOSFET parametric data to enter in the "MOSFETDatabase" tab. This sheet is a  
hotlink destination from some of the column headings in the MOSFETDatabase table.  
Definitions  
Plots efficiency data from the table in EfficiencySummary tab.  
Plots power loss data from the table in EfficiencySummary tab.  
EfficiencyChart  
LossChart  
Database for the IC Controllers. Fairchild's portable PWM controllers are featured in this database. Any  
controller can be added by using the "Add" button and filling in the appropriate fields.  
Database for the MOSFETs. Many popular Fairchild MOSFETs are featured in this database. Any MOSFET  
can be added by using the "Add" button and filling in the appropriate fields.  
ControllerDriver  
MOSFETDatabase  
EfficiencySummary  
The main sheet where the system requirements and MOSFET choices can be entered, and the data is stored  
for graphing. To run the graphing routine, push the "RUN" button at the top of the sheet.  
The calculations contained in the "Synchronous buck MOSFET loss calculations" app note are programmed  
into this sheet. The EfficiencySummary macro uses this sheet as its calculator. If a particular operating point  
needs to be examined in more detail, then use this sheet, and enter the parameters by hand. Be sure to save a  
copy of this workbook before overwriting formulas in "Output" tab.  
Output  
Cells are color coded as follows:  
Indicates user input parameters  
Indicates calculated values that can be overwritten with selected values if desired.  
These fields default to the calculated value directly above them.  
These fields are written into, or contain formulae that were input on the "EfficiencySummary" sheet.  
Macro Security Note:  
"AN-6005 Switching Loss Calculation.xls" uses macros extensively. For the spreadsheet to operate properly, check  
the “Always trust macros from this source” box if a security warning appears, then click the “Enable Macros”  
button..  
This is only required the first time you run a Fairchild spreadsheet tool with macros.  
1.0.1 01/04/2006  
7

相关型号:

AN-6006

FAN5068 Component calculation and simulation tools
FAIRCHILD

AN-6024

Understanding Analog Video Signal Clamps, Bias, DC-Restore, and AC or DC Coupling Methods
FAIRCHILD

AN-6026

Design of Power Factor Correction Circuit
FAIRCHILD

AN-6027

Design of Power Factor Correction Circuit
FAIRCHILD

AN-6041

PCB Layout Considerations for Video Filter / Drivers
FAIRCHILD

AN-6047

FIN324C Reset and Standby
FAIRCHILD

AN-6067

Design and Application of Primary-Side Regulation (PSR) PWM Controller
FAIRCHILD

AN-6069

Application Review and Comparative Evaluation of Low-Side Gate Drivers
FAIRCHILD

AN-6073

Highly Integrated Green-Mode PWM Controller
FAIRCHILD

AN-6075

Compact Green-Mode Adapter
FAIRCHILD

AN-6076

Bootstrap Circuit for High-Voltage Gate-Drive IC
FAIRCHILD

AN-6077

Highly Integrated Green-Mode PWM Controller
FAIRCHILD