M66258FP [RENESAS]
8192 × 8-Bit Line Memory; 8192 × 8位直插式内存
| 型号： | M66258FP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8192 × 8-Bit Line Memory |
| 文件： | 总14页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M66258FP
8192 × 8-Bit Line Memory
REJ03F0252-0200
Rev.2.00
Sep 14, 2007
Description
The M66258FP is high speed line memory that uses high performance silicon gate CMOS process technology and
adopts the FIFO (First In First Out) structure consisting of 8192 words × 8 bits.
The M66258FP, performing reading and writing operations at different cycles independently and asynchronously, is
optimal for buffer memory to be used between equipment of different data processing speeds.
Features
•
•
•
•
•
•
•
•
Memory configuration:
High speed cycle:
High speed access:
Output hold:
8192 words × 8 bits configuration
20 ns (Min)
16 ns (Max)
3 ns (Min)
Reading and writing operations can be completely carried out independently and asynchronously
Variable length delay bit
Input/output:
Output:
TTL direct connection allowable
3 states
Application
Digital copying machine, laser beam printer, high speed facsimile, etc.
Block Diagram
Data inputs
D0 to D7
Data outputs
Q0 to Q7
13 14 15 16 21 22 23 24
1 2 3 4 9 10 11 12
Input buffer
Output buffer
RE
20
19
5
6
WE
Read
Write
enable input
enable input
Memory array
8192 × 8 bits
RRES
WRES
Write
reset input
Read
reset input
17
18
8
7
WCK
Write
clock input
RCK
Read
clock input
GND
VCC
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 1 of 13
M66258FP
Pin Arrangement
M66258FP
1
2
24
23
22
21
20
19
18
17
16
15
14
13
Q0
Q1
D0
D1
Data output
Data input
3
Q2
D2
4
Q3
D3
Read enable input
Read reset input
5
Write enable input
Write reset input
RE
WE
WRES
VCC
WCK
D4
6
RRES
GND
RCK
Q4
7
Read clock input
Data output
8
Write clock input
Data input
9
10
11
12
Q5
D5
Q6
D6
Q7
D7
(Top view)
Outline: 24P2U-A
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 2 of 13
M66258FP
Absolute Maximum Ratings
(Ta = 0 to 70°C, unless otherwise noted)
Item
Symbol
Ratings
−0.5 to +6.0
−0.5 to VCC + 0.5
−0.5 to VCC + 0.5
825
Unit
V
Conditions
Supply voltage
Input voltage
Output voltage
VCC
VI
Value based on the GND pin
V
VO
V
Power dissipation
Pd
mW
°C
Ta = 25°C
Storage temperature
Tstg
−65 to 150
Recommended Operating Conditions
Item
Symbol
VCC
Min
4.5
Typ
5.0
0
Max
Unit
V
Supply voltage
Supply voltage
5.5
GND
V
Operating temperature
Topr
0 to 70
°C
Electrical Characteristics
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted)
Item
Symbol
VIH
Min
2.0
Typ
Max
Unit
V
Test Conditions
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
High-level input current
VIL
0.8
V
VOH
VOL
V
CC − 0.8
V
IOH = −4 mA
0.55
1.0
V
IOL = 4 mA
VI = VCC
IIH
µA
WE, WRES, WCK,
RE, RRES, RCK,
D0 to D7
Low-level input current
IIL
−1.0
µA
VI = GND WE, WRES, WCK,
RE, RRES, RCK,
D0 to D7
Off-state high-level output current
Off-state low-level output current
IOZH
IOZL
ICC
5.0
−5.0
150
µA
µA
VO = VCC
VO = GND
Average supply current during
operation
mA
VI = VCC, GND, Output open
t
WCK, tRCK = 20 ns
Input capacitance
CI
10
15
pF
pF
f = 1 MHz
f = 1 MHz
Off-time output capacitance
CO
Function
When write enable input WE is set to "L", the contents of data inputs D0 to D7 are read in synchronization with a rising
edge of write clock input WCK to perform writing operation. When this is the case, the write address counter is also
incremented simultaneously.
When WE is set to "H", the writing operation is inhibited and the write address counter stops.
When write reset input WRES is set to "L", the write address counter is initialized.
When read enable input RE is set to "L", the contents of memory are output to data outputs Q0 to Q7 in synchronization
with a rising edge of read clock input RCK to perform reading operation. When this is the case, the read address
counter is incremented simultaneously.
When RE is set to "H", the reading operation is inhibited and the read address counter stops. The outputs are placed in
a high impedance state.
When read reset input RRES is set to "L", the read address counter is initialized.
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 3 of 13
M66258FP
Switching Characteristics
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted)
Item
Access time
Symbol
Min
3
Typ
Max
16
Unit
ns
tAC
tOH
Output hold time
ns
Output enable time
Output disable time
tOEN
3
16
ns
tODIS
3
16
ns
Timing Requirements
(Ta = 0 to 70°C, VCC = 5 V ± 10%, GND = 0 V, unless otherwise noted)
Item
Symbol
tWCK
Min
20
8
Typ
Max
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Write clock (WCK) cycle
Write clock (WCK) "H" pulse width
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
tWCKH
tWCKL
tRCK
8
20
8
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
Input data setup time for WCK
Input data hold time for WCK
Reset setup time for WCK/RCK
Reset hold time for WCK/RCK
Reset non-selection setup time for WCK/RCK
Reset non-selection hold time for WCK/RCK
WE setup time for WCK
tRCKH
tRCKL
tDS
8
4
tDH
3
tRESS
tRESH
tNRESS
tNRESH
tWES
tWEH
tNWES
tNWEH
tRES
4
3
4
3
4
WE hold time for WCK
3
WE non-selection setup time for WCK
WE non-selection hold time for WCK
RE setup time for RCK
4
3
4
RE hold time for RCK
tREH
3
RE non-selection setup time for RCK
RE non-selection hold time for RCK
Input pulse up/down time
tNRES
tNREH
tr, tf
4
3
Data hold time*
tH
Notes: Perform reset operation after turning on power supply.
For 1 line access, the following conditions must be satisfied:
*
WE high-level period ≤ 20 ms − 8192 • tWCK − WRES low-level period
RE high-level period ≤ 20 ms − 8192 • tRCK − RRES low-level period
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 4 of 13
M66258FP
Switching Characteristics Measurement Circuit
VCC
RL = 1 kΩ
Qn
SW1
CL = 30 pF: tAC, tOH
Qn
SW2
CL = 5 pF: tOEN, tODIS
RL = 1 kΩ
Input pulse level:
0 to 3 V
Input pulse up/down time: 3 ns
Judging voltage Input: 1.3 V
Output: 1.3 V (However, tODIS (LZ) is judged with 10% of the output amplitude, while tODIS (HZ) is
judged with 90% of the output amplitude)
Load capacitance CL includes the floating capacity of connected lines and input capacitance of probe.
Item
SW1
Close
Open
Close
Open
SW2
Open
Close
Open
Close
tODIS (LZ)
tODIS (HZ)
tOEN (ZL)
tOEN (ZH)
tODIS and tOEN Measurement Condition
3 V
RCK
1.3 V
1.3 V
GND
3 V
RE
GND
tODIS (HZ)
tOEN (ZH)
VOH
90%
1.3 V
Qn
tODIS (LZ)
tOEN (ZL)
Qn
1.3 V
VOL
10%
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 5 of 13
M66258FP
Operation Timing
Write Cycle
n cycle
n + 1 cycle
n + 2 cycle
Disable cycle
n + 3 cycle n + 4 cycle
WCK
tWCK
tWCKH tWCKL tWEH tNWES
tNWEH tWES
WE
tDS tDH
(n)
(n + 1)
(n + 2)
(n + 3)
(n + 4)
Dn
WRES = "H"
Write Reset Cycle
n − 1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
2 cycle
WCK
tWCK
tNRESH tRESS
tRESH tNRESS
WRES
tDS tDH
(n − 1)
(n)
(0)
(1)
(2)
Dn
WE = "L"
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 6 of 13
M66258FP
Matters that Needs Attention when WCK Stops
n cycle
n + 1 cycle
n cycle
Disable cycle
WCK
tWCK
tNWES
WE
tDS tDH
tDS tDH
Dn
(n)
(n)
Period for writing data (n)
into memory
Period for writing data (n)
into memory
WRES = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level
period of n + 1 cycle. The writing operation is complete at the falling edge after n + 1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n + 1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 7 of 13
M66258FP
Read Cycle
n cycle
n + 1 cycle
n + 2 cycle
Disable cycle
n + 3 cycle n + 4 cycle
RCK
tRCK
tRCKH tRCKL tREH tNRES
tNREH tRES
tAC
RE
tODIS
tOEN
HIGH-Z
(n)
(n + 1)
(n + 2)
(n + 3)
tOH
(n + 4)
Qn
RRES = "H"
Read Reset Cycle
n − 1 cycle
n cycle
Reset cycle
0 cycle
1 cycle
2 cycle
RCK
tRCK
tNRESH tRESS
tRESH tNRESS
RRES
tAC
(n − 1)
(n)
(0)
(0)
(0)
tOH
(1)
(2)
Qn
RE = "L"
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 8 of 13
M66258FP
Variable Length Delay Bit
1 Line (8192 Bits) Delay
Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK
before read cycle to easily make 1 line delay.
8192 cycle 8193 cycle 8194 cycle
0 cycle
1 cycle
2 cycle
8190 cycle 8191 cycle
(0')
(1')
(2')
WCK
RCK
tRESS tRESH
WRES
RRES
tDS tDH
tDS tDH
(0)
(1)
(2)
(8189)
(8190)
(8191)
(0')
(1')
(1)
(2')
(2)
(3')
(3)
Dn
Qn
tAC
tOH
8192 cycle
(0)
WE, RE = "L"
n-bit Delay Bit
(Reset at cycles according to the delay length)
n cycle n + 1 cycle n + 2 cycle n + 3 cycle
(0') (1') (2') (3')
0 cycle
1 cycle
2 cycle
n − 2 cycle n − 1 cycle
WCK
RCK
tRESS tRESH
tRESS tRESH
WRES
RRES
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 3)
(n − 2)
(n − 1)
(0')
(1')
(1)
(2')
(2)
(3')
(3)
Dn
Qn
tAC
tOH
m cycle
(0)
WE, RE = "L"
m ≥ 3
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 9 of 13
M66258FP
n-bit Delay 2
(Slides input timings of WRES and RRES at cycles according to the delay length)
0 cycle
1 cycle
2 cycle n − 2 cycle n − 1 cycle n cycle n + 1 cycle n + 2 cycle n + 3 cycle
WCK
RCK
tRESS tRESH
WRES
RRES
tRESS tRESH
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 2)
(n − 1)
(n)
(n + 1)
(n + 2)
(n + 3)
Dn
Qn
tAC
tOH
m cycle
(0)
(1)
(2)
(3)
WE, RE = "L"
n-bit Delay 3
(Slides address by disabling RE in the period according to the delay length)
0 cycle
1 cycle
2 cycle
n − 1 cycle
n cycle
n + 1 cycle n + 2 cycle n + 3 cycle
WCK
RCK
tRESS tRESH
WRES
RRES
tNREH tRES
RE
tDS tDH
tDS tDH
(0)
(1)
(2)
(n − 2)
(n − 1)
(n)
(n + 1)
(n + 2)
(n + 3)
Dn
tAC
tOH
m cycle
HIGH-Z
(0)
(1)
(2)
(3)
Qn
WE, RE = "L"
m ≥ 3
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 10 of 13
M66258FP
Reading Shortest n-cycle Write Data "n"
(Reading side n − 1 cycle starts after the end of writing side n − 1 cycle)
When the reading side n − 1 cycle starts before the end of the writing side n + 1 cycle, output Qn of n cycle is made
invalid. In the following diagram, reading operation of n − 1 cycle is invalid.
n cycle
n + 1 cycle
n + 2 cycle
n + 3 cycle
WCK
Dn
(n)
(n +1)
(n +2)
(n +3)
n − 2 cycle
n − 1 cycle
n cycle
RCK
Qn
Invalid
(n)
Reading Longest n-cycle Write Data "n": 1 Line Delay
(When writing side n-cycle <2>* starts, reading side n cycle <1>* then starts)
Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle
<2>* overlap each other.
n cycle <1>*
0 cycle <2>*
n cycle <2>*
WCK
Dn
(n − 1) <1>*
(n) <1>*
(0) <2>*
(n − 1) <2>*
(n) <2>*
n cycle <0>*
0 cycle <1>*
n cycle <1>*
RCK
Qn
(n − 1) <0>*
(n) <0>*
(0) <1>*
(n − 1) <1>*
(n) <1>*
Note: <0>*, <1>* and <2>* indicate value of lines.
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 11 of 13
M66258FP
Application Example
Sub Scan Resolution Compensation Circuit with Laplacian Filter
N
M66258
n line image data
D0 Q0
to
to
B
D7 Q7
(n + 1) line
image data
Compensated
image data
× 2
1 line
delay
× K
M66258
D0 Q0
A
(n + 1) line
image data
to
to
D7 Q7
1 line
delay
Main scan direction
A
X
B
(n − 1) line
n line
N' = N + K { (N − A) + (N − B) }
= N + K {2N − (A + B)}
(n + 1) line
K: Laplacian coefficient
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 12 of 13
M66258FP
Package Dimensions
24P2U-A
Plastic 24pin 375mil SSOP
EIAJ Package Code
SSOP24-P-375-0.80
JEDEC Code
—
Weight(g)
0.4
Lead Material
Cu Alloy
e
b2
24
13
F
Recommended Mount Pad
Dimension in Millimeters
Symbol
1
12
Min
—
0.1
—
0.3
0.23
10.2
7.4
—
10.0
0.5
—
—
—
—
0°
—
—
1.27
Nom
—
Max
2.65
0.3
—
0.45
0.3
10.4
7.6
—
A
A
A
A
1
2
0.2
2.3
0.35
0.25
10.3
7.5
0.8
10.3
0.7
1.4
0.75
—
—
—
0.5
9.53
—
D
G
b
c
D
E
e
A2
A1
e
b
y
HE
10.6
0.9
—
L
L1
z
—
Z1
0.9
0.1
8°
—
—
y
c
z
b2
Z1
Detail G
Detail F
e1
I
2
—
REJ03F0252-0200 Rev.2.00 Sep 14, 2007
Page 13 of 13
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
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but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
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document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
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result of errors or omissions in the information included in this document.
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(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
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rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
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any other inquiries.
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Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
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© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.0
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