AN-9719 [FAIRCHILD]
Power Switch (FPS?) FSL1x7 to Low- Power Supplies; 功率开关（FPS ？ ） FSL1x7到低电源
| 型号： | AN-9719 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Power Switch (FPS?) FSL1x7 to Low- Power Supplies |
| 文件： | 总12页 (文件大小：660K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
AN-9719
Applying Fairchild Power Switch (FPS™) FSL1x7 to
Low- Power Supplies
The FSL-series has
a
built-in synchronized slope
1. Introduction
compensation to achieve stable peak-current-mode control.
The proprietary external line compensation ensures constant
output power limit over a wide AC input voltage range,
90VAC to 264VAC, and helps optimize the power stage.
The highly integrated FSL-series consists of an integrated
current-mode Pulse Width Modulator (PWM) and an
avalanche-rugged 700V SenseFET. It is specifically
designed for high-performance offline Switched Mode
Power Supplies (SMPS) with minimal external components.
Many protection functions; such as open–loop / overload
protection (OLP), over-voltage protection (OVP), and over-
temperature protection (OTP); are fully integrated into FSL-
series. These features improve the SMPS reliability without
increasing system cost.
The features of the integrated PWM controller include a
proprietary green-mode function providing off-time
modulation to linearly decrease the switching frequency at
light-load conditions to minimize standby power
consumption. The PWM controller is manufactured using
the BiCMOS process to further reduce power consumption.
The green mode and burst mode functions with a low
operating current (2mA in green mode) maximize light-load
efficiency so that the power supply can meet stringent
standby power regulations.
Compared to a discrete MOSFET and controller or RCC
switching converter solution, the FSL-series reduces total
component count, converter size, and weight while
increasing efficiency, productivity, and system reliability.
These devices provide a basic platform for design of cost-
effective flyback converters.
Figure 1. Typical Application Circuit
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
www.fairchildsemi.com
AN-9719
APPLICATION NOTE
2. Device Block Description
2.1 Startup Circuit
2.3 Green Mode Operation
For startup, the HV pin is connected to the line input or bulk
capacitor through external resistor RHV, as shown in Figure
2. Typical startup current is 3.5mA and it charges the VDD
capacitor (CDD) through resistor RHV. The startup current
The FSL-series uses feedback voltage (VFB) as an indicator
of the output load and modulates the PWM frequency, as
shown in Figure 4, such that the switching frequency
decreases as load decreases. In heavy-load conditions, the
switching frequency is 100kHz. Once VFB decreases below
turns off when the VDD capacitor voltage reaches VDD-ON
.
The VDD capacitor maintains VDD until the auxiliary
winding of the transformer provides the operating current.
VFB-N (2.5V), the PWM frequency starts to linearly decrease
from 100kHz to 18kHz to reduce the switching losses. As
VFB decreases below VFB-G (2.4V), the switching frequency
is fixed at 18kHz and FSL-series enters “deep” green mode
to reduce the standby power consumption. As VFB decreases
below VFB-ZDC (2.1V), FSL-series enters into burst-mode
operation. When VFB drops below VFB-ZDC, FSL-series stops
switching and the output voltage starts to drop, which
causes the feedback voltage to rise. Once VFB rises above
V
FB-ZDC, switching resumes. Burst mode alternately enables
and disables switching, thereby reducing switching loss to
improve power saving, as shown in Figure 5.
Figure 2. Startup Circuit
2.2 Soft-Start
The FSL-series has internal soft-start circuit that slowly
increases the SenseFET current during startup. The typical
soft-start time is 5ms, during which the VLimit level is
increased in six steps to smoothly establish the required
output voltage, as shown in Figure 3. It also helps prevent
transformer saturation and reduce stress on the secondary
diode during startup.
Figure 4. PWM Frequency
Figure 3. Soft-Start Function
Figure 5. Bust-Mode Operation
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
www.fairchildsemi.com
2
AN-9719
APPLICATION NOTE
2.5.3 Overload Protection (OLP)
2.4 Constant Power Control
When the upper branch of the voltage divider for the shunt
regulator (KA431 shown) is open circuit, as shown in
Figure 7, or an output over-current or short occurs; there is
no current flowing through the opto-coupler transistor. VFB
(feedback voltage) pulls up to 6V. When the feedback
voltage is above 4.6V for longer than 56ms, OLP is
triggered. This protection is also triggered when the SMPS
output drops below the nominal value longer than 56ms due
to the overload condition.
To constantly limit the output power of the converter, high /
low line compensation is included. Sensing the converter
input voltage through the VIN pin, the high / low line
compensation function generates a line-voltage-dependent
peak-current-limit threshold voltage for constant power
control, as shown in Figure 6.
Figure 6. Constant Power Control
2.5 Protection Functions
The FSL-series provides full protection functions to prevent
the power supply and the load from being damaged. The
protection features is shown in Table 1.
Table 1. Protection Functions
FSL127H
FSL137H
Figure 7. OLP Operator
OVP
OTP
Latch
Latch
Latch
Latch
OLP
Auto Restart
Latch
Auto Restart
Latch
VIN-H
VIN-L
Auto Restart
Auto Restart
2.5.1 VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents IC damage caused by
over voltage on the VDD pin. The OVP is triggered when
VDD reaches 28V. It has debounce time (typically 130µs) to
prevent false trigger by switching noise.
2.5.2 Over-Temperature Protection (OTP)
The SenseFET and the control IC integration make
temperature detection of the SenseFET easier. When the
junction temperature exceeds approximately 142°C, thermal
shutdown is activated.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
www.fairchildsemi.com
3
AN-9719
APPLICATION NOTE
3. Design Example
[STEP-2] Determine Input Capacitor (CIN) and Input
Voltage Range
Flyback converters have two kinds of operation modes;
Continuous Conduction Mode (CCM) and Discontinuous
Conduction Mode (DCM). Each has its own advantages and
disadvantages. In general, DCM generates lower stress for
the rectifier diodes, since the diodes are operating at zero
current just before becoming reverse biased and the reverse
recovery loss is minimized. The transformer size can be
reduced using DCM because the average energy storage is
low compared to CCM. However, DCM causes high RMS
current, which severely increases the conduction loss of the
MOSFET for low line condition. For standby auxiliary
power supply applications with low output voltage and
minimal reverse recovery of Schottky diode, it is typical to
design the converter such that the converter operates in
CCM to maximize efficiency.
It is typical to select the input capacitor as 2~3μF per watt
of peak input power for the universal input range (85-
265VRMS) and 1μF per watt of peak input power for the
European input range (195V-265VRMS). With the input
capacitor chosen, the minimum input capacitor voltage at
nominal-load condition is obtained as:
ꢉ
ꢊꢋ
· ꢘ1 ꢝ ꢞꢟꢠꢛ
(2)
ꢗ
ꢓ
ꢌ
2 · ꢘꢓ
ꢔꢕꢖꢛꢜ ꢝ
ꢙꢊꢋꢚ
ꢔꢕꢖ
ꢊꢋ
ꢡꢊꢋ · ꢢ
ꢙ
where DCH is the input capacitor charging duty ratio defined
in Figure 8, which is typically about 0.2.
The maximum input capacitor voltage is given as:
(3)
ꢓ
ꢌ √2ꢓ
ꢙꢊꢋꢚ
ꢔꢣꢤ
ꢔꢣꢤ
ꢊꢋ
This section presents a design procedure using the Figure 1
schematic as a reference. An offline SMPS with 12W
nominal output power has been selected as the example.
[STEP-1] Define the System Specifications
When designing
a
power supply, the following
specifications should be determined first:
Figure 8. Input Capacitor Voltage Waveform
Line Voltage Range (Vꢀꢁꢂꢃ
Line Frequency (fL)
and Vꢀꢁꢂꢃ
)
ꢄꢅꢆ
ꢄꢇꢈ
Nominal Output Power (PO)
Estimate Efficiencies for Nominal Load (η).
The power conversion efficiency must be estimated to
calculate the input power for nominal load condition. If
no reference data is available, set η = 0.7~0.75 for low-
voltage output applications and η = 0.8~0.85 for high-
voltage output applications.
With the estimated efficiency, the input power for peak
load condition is given by:
ꢉꢍ
ꢉ
ꢊꢋ
ꢌ
(1)
η
[STEP-3] Determine the Reflected Output Voltage (VRO
)
When the MOSFET is turned off, the input voltage (VIN),
together with the output voltage reflected to the primary
(VRO), are imposed across the MOSFET, as shown in Figure
9. With a given VRO, the maximum duty cycle (DMAX) and
the nominal MOSFET voltage (VDSNOM) are obtained as:
ꢓꢪꢍ
ꢞꢧꢨꢩ
ꢌ
(4)
ꢓꢪꢍ ꢫ ꢓ
ꢔꢕꢖ
ꢊꢋ
ꢓꢬꢭ
ꢌ ꢓ
ꢫ ꢓ
(5)
(6)
ꢖꢮꢔ
ꢔꢣꢤ
ꢪꢍ
ꢊꢋ
ꢓ
· ꢘꢓ ꢫ ꢓ ꢛ
ꢍ ꢯ
ꢔꢣꢤ
ꢊꢋ
ꢓꢬꢍ
ꢌ
ꢫ ꢓꢍ
ꢖꢮꢔ
ꢓꢪꢍ
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
www.fairchildsemi.com
4
AN-9719
APPLICATION NOTE
Figure 9. Output Voltage Reflected to the Primary
As can be seen in Equation 5, the voltage stress across
MOSFET can be reduced by reducing VRO. However, this
increases the voltage stresses on the rectifier diodes in the
secondary side, as shown in Equation 6. Therefore, VRO
should be determined by a balance between the voltage
stresses of MOSFET and diode. Especially for low output
voltage applications, the rectifier diode forward-voltage
drop is a dominant factor determining the power supply
efficiency. Therefore, the reflected output voltage should be
determined such that rectifier diode forward voltage can be
minimized. Table 2 shows the forward-voltage drop for
Schottky diodes with different voltage rating.
[STEP-4] Determine the Transformer Primary-Side
Inductance (LM)
The transformer primary-side inductance is determined for
the minimum input voltage and nominal-load condition.
With the DMAX from Step-3, the primary-side inductance
(LM) of the transformer is obtained as:
The actual drain voltage and diode voltage rise above the
nominal voltage is due to the leakage inductance of the
transformer as shown in Figure 9. It is typical to set VRO
NOM
NOM
such that VDS
and VDO
are 70~80% of voltage
ratings of MOSFET and diode, respectively.
ꢘꢓ
· ꢞꢧꢨꢩꢛꢜ
ꢔꢕꢖ
ꢊꢋ
(7)
ꢲꢧ
ꢌ
2 · ꢉ · ꢢ · ꢴꢪꢯ
ꢊꢋ
ꢭꢳ
Table 2. Diode Forward-Voltage Drop for Different
Voltage Ratings (3A Schottky Diode)
where fSW is the switching frequency and KRF is the ripple
factor at minimum input voltage and nominal load
condition, defined as shown in Figure 10.
V
RRM
V
F
Part Name
SB320
SB330
SB340
SB350
SB360
SB380
SB3100
20V
30V
40V
50V
60V
80V
For DCM operation, KRF = 1, and, for CCM operation, KRF
< 1. The ripple factor is closely related to the transformer
size and the RMS value of the MOSFET current. Even
though the conduction loss in the MOSFET can be reduced
by reducing the ripple factor, too small a ripple factor forces
an increase in transformer size. When designing the flyback
0.5V
0.74V
0.85V
converter to operate in CCM, it is reasonable to set KRF
=
100V
0.25-0.5 for the universal input range and KRF = 0.4-0.8 for
the European input range.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
www.fairchildsemi.com
5
AN-9719
APPLICATION NOTE
[STEP-5] Choose the Proper FPS Considering Input
Power and Peak Drain Current
Once LM is calculated from equation (7) after choosing KRF,
the peak and RMS current of the MOSFET for the minimum
input voltage and nominal load condition are obtained as:
∆ꢵ
With the resulting maximum peak drain current of the
MOSFET (IDSPK) from Equation 8, choose the proper FPS
for which the pulse-by-pulse current limit level (ILIM) is
ꢵꢬꢭ ꢌ ꢵꢚꢬꢟ
ꢫ
ꢶꢷ
(8)
2
higher than IDSPK. Since FPS has ±10% tolerance of ILIM
,
ꢜ
there should be some margin when choosing the proper FPS
device. The FSL-series lineup with proper power rating is
summarized in Table 3.
∆ꢵ
ꢞꢧꢨꢩ
3
ꢘ
ꢛꢜ
ꢗ
ꢵꢬꢭ
ꢌ
ꢓ
ꢺ3 ꢵꢚꢬꢟ ꢫ ꢻ ꢼ ꢽ
2
ꢸꢔꢹ
(9)
where:
Table 3. Lineup of FSL1x7-Series with Power Rating
ꢉ
ꢊꢋ
ꢵꢚꢬꢟ
and
ꢌ
(10)
(11)
ILIM at VIN=1.2V
85-265VAC
· ꢞ
ꢔꢕꢖ
ꢧꢨꢩ
ꢊꢋ
Product
Open Frame
Min.
0.51A
0.74A
Typ.
0.61A
0.84A
Max.
0.71A
0.94A
FSL127H
FSL137H
16W
19W
ꢓ
· ꢞ
ꢔꢕꢖ
ꢧꢨꢩ
ꢊꢋ
∆ꢵ ꢌ
ꢲꢧ · ꢢ
ꢭꢳ
ΔI
2IEDC
KRF
=
[STEP-6] Determine the Minimum Primary Turns
ΔI
With a given magnetic core, the minimum number of turns
for the transformer primary side to avoid the core saturation
is given by:
PK
IDS
ꢲꢧ · ꢵꢙꢧ
ꢌ
ꢾ 10ꢦ
(12)
ꢔꢕꢖ
ꢭꢨ · ꣃ
Figure 10. MOSFET Current and Ripple Factor (KRF)
where Ae is the cross-sectional area of the core in mm2, ILIM
is the pulse-by-pulse current limit level, and BSAT is the
saturation flux density in Tesla.
The pulse-by-pulse current limit level is included in
Equation 12 because the inductor current reaches the pulse-
by-pulse current limit level during the load transient or
overload condition. Figure 11 shows the typical
characteristics of ferrite core from TDK (PC40). Since the
saturation flux density (BSAT) decreases as temperature
increases, the high-temperature characteristics should be
considered. If there is no reference data, use BSAT =0.3 T.
Figure 11.Typical B-H Characteristics of Ferrite Core
(TDK/PC40)
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
www.fairchildsemi.com
6
AN-9719
APPLICATION NOTE
[STEP-7] Determine the Number of Turns for each
Winding
Figure 12 shows a simplified diagram of the transformer.
First calculate the turn ratio (n) between the primary-side
and the secondary-side from the reflected output voltage
(VRO) determined in Step-3 as:
[STEP-8] Determine the Wire Diameter for Each Winding
Based on the RMS Current of Winding
ꢓꢪꢍ
(13)
꣎ ꢌ
ꢌ
The maximum RMS current of the secondary winding is
obtained as:
ꢭ ꢓꢍ ꢫ ꢓ
ꢯ
where NP and NS are the number of turns for primary-side
and secondary-side, respectively; VO is the output voltage;
and VF is the output diode (DO) forward-voltage drop.
1 ꢝ ꢞꢧꢨꢩ
(15)
ꢵꢭꢚꢟ
ꢌ ꣎ · ꢵꢬꢭꢸꢔꢹꢗ
ꢸꢔꢹ
ꢞꢧꢨꢩ
The current density is typically 3~5A/mm2 when the wire is
long (>1m). When the wire is short with a small number of
turns, a current density of 5~10A/mm2 is acceptable. Avoid
using wire with a diameter larger than 1mm to avoid severe
eddy current or ac losses. For high-current output, it is better
to use parallel windings with multiple strands of thinner
wire to minimize skin effect.
Next, determine the proper integer for NS such that the
resulting NP is larger than NPMIN obtained from Equation 12.
The number of turns for the auxiliary winding for VDD
supply is determined as:
꣏
ꢓꢬꢬ ꢫ ꢓ
ꢯꢨ
ꢨ ꢌ
· ꢭ꣐
(14)
ꢓꢍ ꢫ ꢓ
ꢯ
where VDD is the supply voltage nominal value and VFA is
the forward-voltage drop of DDD as defined in Figure 12.
Since VDD increases as the output load increases, set VDD at
5~8V higher than VDD UVLO level (8V) to avoid the over-
voltage protection condition during the peak-load operation.
[STEP-9] Choose the Rectifier Diode in the Secondary-
Side Based on the Voltage and Current Ratings
The maximum reverse voltage and the RMS current of the
rectifier diode are obtained as:
ꢓ
ꢔꢣꢤ
ꢊꢋ
(16)
ꢓꢬꢍ ꢌ ꢓꢍ ꢫ
꣎
1 ꢝ ꢞꢧꢨꢩ
ꢞꢧꢨꢩ
(17)
ꢵꢬꢍ
ꢌ ꣎ · ꢵꢬꢭꢸꢔꢹꢗ
ꢸꢔꢹ
Figure 12. Simplified Transformer Diagram
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
www.fairchildsemi.com
7
AN-9719
APPLICATION NOTE
The typical voltage and current margins for the rectifier
diode are as follows:
Notice that there is a right-half-plane (RHP) zero (ωRZ) in
the control-to-output transfer function of Equation 21.
Because the RHP zero reduces the phase by 90 degrees, the
crossover frequency should be placed below the RHP zero.
(18)
ꢓꢪꢪꢧ ꢱ 1.2 · ꢓꢬꢍ
ꢵꢯ ꢱ 1.8 · ꢵꢬꢍ
(19)
ꢸꢔꢹ
Figure 13 shows the variation of a CCM flyback converter
control-to-output transfer function for different input
voltages. This figure shows the system poles and zeros with
the DC gain change for different input voltages. The gain is
highest at the high input voltage condition and the RHP zero
is lowest at the low input voltage condition.
where VRRM is the maximum reverse voltage and IF is the
current rating of the diode.
[STEP-10] Feedback Circuit Configuration
Figure 13. CCM Flyback Converter Control-to-Output
Transfer Function Variation for Different Input Voltage
Since FSL-series employs current-mode control, the
feedback loop can be implemented with a one-pole and one-
zero compensation circuit.
Figure 14 shows the variation of a CCM flyback converter
control-to-output transfer function for different loads. Note
that the DC gain changes for different loads and the RHP
zero is the lowest at the full-load condition.
The current control factor of FPS, K, is defined as:
ꢵꢙꢊꢧ
ꢵꢙꢊꢧ
2.5
ꢴ ꢌ
ꢌ
(20)
ꢓ
ꢹꢣ꣓
ꢯ꣒
SAT
where ILIM is the pulse-by-pulse current limit and VFB is
the feedback saturation voltage, typically 2.5V.
As described in Step-4, it is typical to design the flyback
converter to operate in CCM for heavy-load condition. For
CCM operation, the control-to-output transfer function of a
flyback converter using current mode control is given by:
꣖
ꢓꢍ
꣔꣕ꢟ
ꢌ
꣖
ꢓ
ꢯ꣒
(21)
ꢘ
⁄
ꢛ ꢘ ꢛ
⁄
ꢛꢘ
⁄
ꢴ · ꣗ꢙ · ꢓ ꢭ
1 ꢫ ꣘ ꣙ 1 ꢝ ꣘ ꣙ꢪ
ꢊꢋ
ꢌ
·
ꢘ
⁄
ꢛ
2ꢓꢪꢍ ꢫ ꢓ
1 ꢫ ꣘ ꣙
ꢊꢋ
Figure 14. CCM Flyback Converter Control-to-Output
Transfer Function Variation for Different Loads
where RL is the load resistance.
The pole and zeros of Equation 21 are obtained as:
When the input voltage and the load current vary over a wide
range, it is not easy to determine the worst case for the
feedback loop design. The gain, together with zeros and
poles, varies according to the operating conditions. Even
though the converter is designed to operate in CCM or at the
boundary of DCM and CCM in the minimum input voltage
and full-load condition; the converter enters into DCM,
changing the system transfer functions as the load current
decreases and/or input voltage increases.
ꢘ
ꢛꢜ
꣗ꢙ 1 ꢝ ꢞ
1
꣙ ꢌ
, ꣙ꢪ
ꢌ
꣎ ꣙
ꢘ
⁄
ꢛꢜ
ꢞꢲꢧ ꢭ
꣗ꢟꢡꢍ
ꢘ
ꢛ
1 ꢫ ꢞ
(22)
ꢌ
꣗ꢙꢡꢍ
here D is the duty cycle of the FPS and RC is the ESR of CO.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
www.fairchildsemi.com
8
AN-9719
APPLICATION NOTE
One simple and practical way to address this problem is
designing the feedback loop for low input voltage and full-
load condition with enough phase and gain margin. When
the converter operates in CCM, the RHP zero is lowest in
low input voltage and full-load condition. The gain
increases only about 6dB as the operating condition is
changed from the lowest input voltage to the highest input
voltage condition under universal input condition. When the
operating mode changes from CCM to DCM, the RHP zero
disappears, making the system stable. Therefore, by
designing the feedback loop with more than 45 degrees of
phase margin in low input voltage and full-load condition,
the stability over all the operating ranges can be guaranteed.
Figure 15 is a typical feedback circuit mainly consisting of a
shunt regulator and a photo-coupler. R1 and R2 form a
voltage divider for output voltage regulation. RF and CF are
for control-loop compensation. The maximum source
current of the FB pin is about 1mA. The phototransistor
must be capable of sinking this current to pull the FB level
down at no load. The value of RD, is determined by:
ꢓꢍ ꢝ ꢓꢍꢬ ꢝ ꢓꢨ
· ꢡ꣗ ꢱ ꢵꢯ꣒
(23)
꣗ꢬ
where VOPD is the forward-voltage drop of the photodiode
(~1.2V); VKA is the minimum cathode-to-anode voltage of
KA431 (2.5V); and CTR is the current transfer rate of the
opto-coupler.
[STEP-11] Design Input Voltage Sensing Circuit
Figure 16 shows a resistive voltage divider with low-pass
filter for line-voltage detection of the VIN pin. FSL-series
devices start and enable the latch function when the VIN
voltage reaches 1.03V. If latch protection is triggered, the
VIN voltage is used for release latch protection as the VIN
voltage drops below 0.7V. It is typical to use 100:1 voltage
divider for VIN level.
6V
+
-
Figure 16. Input Voltage Sensing
Figure 15. Feedback Circuit
The feedback compensation network transfer function of
Figure 15 is obtained as:
꣖
⁄
꣙ꢊ 1 ꢫ ꣘ ꣙ꢟ
ꢓ
ꢯ꣒
ꢌ ꢝ
·
(24)
꣖
ꢓꢍ
⁄
1 ꢫ ꣘ ꣙ꢟ
꣘
where
꣗ꢯ꣒
1
1
꣙ꢊ ꢌ
, ꣙ꢟ
ꢌ
꣎ ꣙ꢟ ꢌ
ꢘ
ꢛ
꣗꣐꣗ꢬꢡꢯ
꣗ꢯ ꢫ ꣗꣐ ꢡꢯ
꣗ꢯ꣒ꢡꢯ꣒
(25)
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
www.fairchildsemi.com
9
AN-9719
APPLICATION NOTE
4. Printed Circuit Board Layout
High-frequency switching current / voltage makes printed
circuit board layout a very important design task. Good PCB
layout minimizes excessive EMI and helps the power supply
survive during surge/ESD tests.
GND2→3→1 are suggestions for ESD tests where the
earth ground is not available on the power supply. In the
ESD discharge path, the charge goes from the secondary,
through the transformer stray capacitance, to GND3,
then GND1, and back to mains. It should be noted that
control circuits should not be placed on the discharge
path. Point discharge for common-mode choke (see
Figure 17) can decrease high-frequency impedance and
increase ESD immunity.
4.1 Guidelines
To get better EMI performance and reduce line-frequency
ripple, the output of the bridge rectifier should be connected
to capacitor CDC first, then to the switching circuits.
Should a Y-cap between primary and secondary be
required, connect this Y-cap to the positive terminal of
The high-frequency current loop is in CDC – Transformer
– Drain pin – CDC. The area enclosed by this current loop
should be as small as possible. Keep the traces (especially
2→1 in Figure 17) short, direct, and wide. High-voltage
traces related the drain and RCD snubber should be kept
far away from control circuits to prevent unnecessary
interference.
CDC. If this Y-cap is connected to primary ground, it
should be connected to the negative terminal of CDC
(GND1) directly. Point discharge of this Y-cap also
helps for ESD. In addition, the creepage distance
between these two pointed ends should be at least 5mm
according to safety requirements.
As indicated by 2, the ground of control circuits should
be connected first, then route other traces.
As indicated by 3, the area enclosed by the transformer
auxiliary winding, DDD and CDD should also be kept
small. Place CDD close to the controller for good
decoupling.
Figure 17. Layout Considerations
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
www.fairchildsemi.com
10
AN-9719
APPLICATION NOTE
5. Design Summary
5.1 Schematic
Figure 18 shows the final schematic of the 12W power supply of the design example.
Figure 18. Design Example
5.2 Transformer Specification
Figure 19.Transformer Specification
Core: EEL-16 (Ae=19.2mm2)
Bobbin: EEL-16
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
www.fairchildsemi.com
11
AN-9719
APPLICATION NOTE
Pin (S → F)
5 → 4
Wire
Turns
Na
0.3φ×1
13
Insulation : Polyester Tape t = 0.025mm, 2 Layers
Np 2 → 1
Insulation : Polyester Tape t = 0.025mm, 2 Layers
4 → -
Insulation : Polyester Tape t = 0.025mm, 2 Layers
Ns 8 → 10
0.26φ×1
COPPER SHIELD
0.35φ×1
75
1.2
13
-
Insulation : Polyester Tape t = 0.025mm, 3 Layers
Pin
Specification
Remark
100kHz, 1V
1－2
1－2
Inductance
Leakage
600μH ± 10%
Short All Other Pins
< 30 μH Maximum
Related Datasheets
FSL127H — Green Mode Fairchild Power Switch (FPS™)
FSL137H— Green Mode Fairchild Power Switch (FPS™)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b)
support or sustain life, or (c) whose failure to perform when
properly used in accordance with instructions for use provided
in the labeling, can be reasonably expected to result in
significant injury to the user.
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
© 2010 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 11/2/10
www.fairchildsemi.com
12
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