VND810TR-E [STMICROELECTRONICS]

5A 2 CHANNEL, BUF OR INV BASED PRPHL DRVR, PDSO16, SO-16;
VND810TR-E
型号: VND810TR-E
厂家: ST    ST
描述:

5A 2 CHANNEL, BUF OR INV BASED PRPHL DRVR, PDSO16, SO-16

驱动 光电二极管 接口集成电路 驱动器
文件: 总20页 (文件大小:201K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
VND810-E  
DOUBLE CHANNEL HIGH SIDE DRIVER  
Figure 1. Package  
Table 1. General Features  
Type  
R
I
V
CC  
DS(on)  
out  
VND810-E  
160 m(*)  
3.5A (*)  
36 V  
(*) Per each channel  
CMOS COMPATIBLE INPUTS  
OPEN DRAIN STATUS OUTPUTS  
ON STATE OPEN LOAD DETECTION  
OFF STATE OPEN LOAD DETECTION  
SHORTED LOAD PROTECTION  
UNDERVOLTAGE AND OVERVOLTAGE  
SHUTDOWN  
PROTECTION AGAINST LOSS OF GROUND  
VERY LOW STAND-BY CURRENT  
REVERSE BATTERY PROTECTION (**)  
IN COMPLIANCE WITH THE 2002/95/EC  
EUROPEAN DIRECTIVE  
SO-16  
DESCRIPTION  
Active current limitation combined with thermal  
shutdown and automatic restart protects the  
device against overload. The device detects open  
load condition both in on and off state. Output  
The VND810-E is a monolithidevice designed in  
STMicroelectronics VIPower M0-3 Technology,  
intended for driving any kind of load with one side  
connected to groun
shorted to V is detected in the off state. Device  
automatically turns off in case of ground pin  
disconnection.  
Active V  
pin voltage clamp protects the device  
CC  
CC  
against low energy spikes (see ISO7637 transient  
compatibility table).  
Table 2. Order Codes  
Package  
Tube  
Tape and Reel  
VND810-E  
VND810TR-E  
SO-16  
Note: (**) See application schematic at page 9  
Rev. 1  
1/20  
October 2004  
VND810-E  
Figure 2. Block Diagram  
Vcc  
Vcc  
CLAMP  
OVERVOLTAGE  
UNDERVOLTAGE  
GND  
CLAMP 1  
OUTPUT1  
OUTPUT2  
INPUT1  
DRIVER 1  
CLAMP 2  
STATUS1  
CURRENT LIMITER 1  
OPENLOAD ON 1  
DRIVER 2  
LOGIC  
OVERTEMP. 1  
CURRENT LIMITER 2  
OPENLOAD O
INPUT2  
OPENLOAD OFF 1  
STATUS2  
OPENLOAD OFF 2  
OVERTEMP. 2  
Table 3. Absolute Maximum Ratings  
Symbol  
Parameter  
Value  
Unit  
V
V
DC Supply Voltage  
41  
- 0.3  
CC  
- V  
Reverse DC Supply Voltage  
DC Reverse Grond Pin Current  
DC Output Crent  
V
CC  
GND  
OUT  
- I  
- 200  
mA  
A
I
Internally Limited  
- 6  
- I  
Reverse DC Output Current  
DC Input Current  
A
OUT  
I
IN  
+/- 10  
mA  
mA  
I
DC Status Current  
+/- 10  
stat  
Electrostatic Discharge (Human Body Model:  
R=1.5KΩ; C=100pF)  
4000  
4000  
5000  
5000  
V
V
V
V
- INPUT  
V
ESD  
MAX  
- STATUS  
- OUTPUT  
- V  
CC  
Maximum Switching Energy  
(L=1.5mH; R =0; V =13.5V; T =150ºC;  
jstart  
E
26  
mJ  
L
bat  
I =5A)  
L
P
Power Dissipation T =25°C  
8.3  
W
°C  
°C  
°C  
tot  
C
T
Junction Operating Temperature  
Case Operating Temperature  
Storage Temperature  
Internally Limited  
- 40 to 150  
j
T
c
T
- 55 to 150  
stg  
2/20  
VND810-E  
Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins  
1
V
CC  
V
CC  
16  
V
N.C.  
GND  
CC  
OUTPUT 1  
OUTPUT 1  
OUTPUT 2  
OUTPUT 2  
INPUT 1  
STATUS 1  
STATUS 2  
INPUT 2  
V
CC  
V
CC  
8
V
CC  
9
Connection / Pin Status N.C. Output  
Input  
Floating  
X
X
X
X
X
To Ground  
Through 10Kresistor  
Figure 4. Current and Voltage Conventions  
IS  
VF1 (*)  
IIN1  
VCC  
VCC  
INPUT 1  
ISTAT1  
IOUT1  
VOUT1  
VIN1  
OUTPUT 1  
STATUS 1  
IIN2  
VSTAT1  
INPUT 2  
IOUT2  
VOUT2  
TAT2  
VI2  
OUTPUT 2  
STATUS 2  
GND  
VSTAT2  
IGND  
(*) V = V  
- V during reverse battery condition  
OUTn  
Fn  
CCn  
Table 4. Thermal Data  
Symbol  
Parameter  
Value  
Unit  
°C/W  
°C/W  
R
thj-lead  
thj-amb  
Thermal Resistance Junction-lead  
Thermal Resistance Junction-ambient  
15  
(1)  
(2)  
R
77  
57  
2
Note: 1. When mounted on a standard single-sided FR-4 board with 0.5cm of Cu (at least 35µm thick) connected to all V pins. Horizontal  
CC  
mounting and no artificial air flow.  
2
Note: 2. When mounted on a standard single-sided FR-4 board with 4cm of Cu (at least 35µm thick) connected to all V pins. Horizontal  
CC  
mounting and no artificial air flow.  
3/20  
VND810-E  
ELECTRICAL CHARACTERISTICS  
(8V<V <36V; -40°C < T <150°C, unless otherwise specified)  
CC  
j
(Per each channel)  
Table 5. Power Output  
Symbol  
(**)  
Parameter  
Test Conditions  
Min.  
5.5  
3
Typ.  
13  
4
Max.  
36  
Unit  
V
V
Operating Supply Voltage  
CC  
V
(**) Undervoltage Shut-down  
5.5  
V
USD  
V
(**)  
Overvoltage Shut-down  
On State Resistance  
36  
V
OV  
I
=1A; T =25°C  
160  
320  
mΩ  
mΩ  
OUT  
j
R
ON  
I
=1A; V >8V  
CC  
OUT  
12  
40  
µA  
Off State; V =13V; V =V  
=0V  
OUT  
CC  
IN  
Off State; V =13V; V =V  
T =25°C  
j
=0V;  
OUT  
CC  
IN  
I (**)  
S
Supply Current  
12  
25  
7
µA  
On State; V =13V; V =5V; I  
=0A  
OUT  
CC  
IN  
mA  
I
I
I
I
Off State Output Current  
Off State Output Current  
Off State Output Current  
Off State Output Current  
V =V =0V  
OUT  
50  
0
µA  
µA  
µA  
µA  
L(off1)  
L(off2)  
L(off3)  
L(off4)  
IN  
V =0V; V  
=3.5V  
-75  
IN  
OUT  
V =V  
=0V; V =13V; T =125C  
OUT  
5
IN  
CC  
j
V =V  
=0V; V =13V; T 5°C  
OUT  
3
IN  
CC  
j
Note: (**) Per device.  
Table 6. Protection (see note 1)  
Symbol  
Parameter  
Test Conditions  
Min.  
150  
135  
7
Typ.  
Max.  
Unit  
°C  
T
Shut-down Temperature  
Reset Temperature  
Thermal Hysteresis  
175  
200  
TSD  
T
°C  
R
T
15  
5
°C  
hyst  
Status Dy in Overload  
Conditions  
T >T  
j
TSD  
t
20  
µs  
SDL  
3.5  
7.5  
7.5  
A
A
I
Current limitation  
lim  
5.5V<V <36V  
CC  
Turn-off Output Clamp  
Voltage  
V
41  
-
V
55  
-
CC  
CC  
V
I
=1A; L=6mH  
V -48  
CC  
V
demag  
OUT  
Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be  
used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration  
and number of activation cycles  
Table 7. V - Output Diode  
CC  
Symbol  
Parameter  
Test Conditions  
=0.5A; T=150°C  
Min  
Typ  
Max  
Unit  
V
F
Forward on Voltage  
-I  
OUT  
0.6  
V
j
4/20  
VND810-E  
ELECTRICAL CHARACTERISTICS (continued)  
Table 8. Status Pin  
Symbol  
Parameter  
Test Conditions  
= 1.6 mA  
STAT  
Min  
Typ  
Max  
Unit  
V
V
Status Low Output Voltage I  
Status Leakage Current  
0.5  
10  
STAT  
I
Normal Operation; V  
= 5V  
STAT  
µA  
LSTAT  
Status Pin Input  
Capacitance  
C
Normal Operation; V  
= 5V  
STAT  
100  
8
pF  
STAT  
I
= 1mA  
6
6.8  
V
V
STAT  
V
Status Clamp Voltage  
I
SCL  
= - 1mA  
-0.7  
STAT  
Table 9. Switching (V =13V)  
CC  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Unit  
R =13from V rising edge to  
L
IN  
t
Turn-on Delay Time  
30  
µs  
d(on)  
d(off)  
V
OUT  
=1.3V  
R =13from V falling edge to  
L
IN  
t
Turn-off Delay Time  
µs  
V
OUT  
=11.7V  
See  
R =13from V  
=1.3V to  
L
OUT  
dV  
dV  
/dt  
Turn-on Voltage Slope  
relative  
diagram  
See  
relative  
diagram  
V/µs  
OUT (on)  
V
OUT  
=10.4V  
R =13from V  
=11.7V to  
OUT  
L
/dt  
OUT (off)  
Turn-off Voltage Slope  
V/µs  
V
OUT  
=1.3V  
Table 10. Openload Detection  
Symbol  
Parameter  
Openload ON State  
Detection Threshold  
Openload ON State  
Detection Delay  
Test Conditions  
Min  
Typ  
Max  
Unit  
I
OL  
V =5V  
20  
40  
80  
mA  
N  
t
I =0A  
OUT  
200  
µs  
DOL(on)  
Openload OFF ate  
Voltage tection  
Threshol
V
OL  
V =0V  
IN  
1.5  
2.5  
3.5  
V
Openload Detection Delay  
at Turn Off  
t
1000  
µs  
DOL(off)  
Table 11. Logic Input  
Symbol  
Parameter  
Test Conditions  
= 1.25V  
Min  
Typ  
Max  
Unit  
V
V
Input Low Level  
1.25  
IL  
I
Low Level Input Current  
Input High Level  
V
V
1
µA  
V
IL  
IN  
V
IH  
3.25  
I
IH  
High Level Input Current  
Input Hysteresis Voltage  
= 3.25V  
10  
8
µA  
V
IN  
V
I(hyst)  
0.5  
6
I
I
= 1mA  
6.8  
V
IN  
V
ICL  
Input Clamp Voltage  
= -1mA  
-0.7  
V
IN  
5/20  
VND810-E  
Figure 5.  
OPEN LOAD STATUS TIMING (with external pull-up)  
OVERTEMP STATUS TIMING  
I
< I  
OL  
OUT  
V > V  
OUT OL  
T > T  
j
TSD  
V
INn  
V
INn  
V
STAT n  
V
STAT n  
t
t
SDL  
SDL  
t
t
DOL(off)  
DOL(on)  
Table 12. Truth Table  
CONDITIONS  
INPUT  
OUTPUT  
SENSE  
L
H
L
H
H
H
Normal Operation  
Current Limitation  
L
H
H
L
X
X
H
) H  
) L  
(T < T  
(T > T  
j
j
TSD  
TSD  
L
H
L
L
H
L
Overtemperature  
Undervoltage  
Overvoltage  
L
H
L
L
X
X
L
H
L
L
H
H
L
H
H
H
L
H
Output Voltage >
L
H
L
H
H
L
Output Current < I  
OL  
6/20  
VND810-E  
Figure 6. Switching Time Waveforms  
V
OUTn  
90%  
80%  
dV /dt  
OUT (off)  
dV /dt  
OUT (on)  
10%  
t
V
INn  
t
d(on)  
t
d(off)  
t
Table 13. Electrical Transient Requirements On V  
ISO T/R 7637/1  
Pin  
CC  
TEST LEVELS  
III  
I
II  
IV  
Delays and  
Impedance  
Test Pulse  
1
2
-25 V  
+V  
-25 V  
-50 V  
+50 V  
-50 V  
-75 V  
+75 V  
-100 V  
+75 V  
-6 V  
-100 V  
+100 V  
-150 V  
+100 V  
-7 V  
2 ms 10 Ω  
0.2 ms 10 Ω  
0.1 µs 50 Ω  
0.1 µs 50 Ω  
100 ms, 0.01 Ω  
400 ms, 2 Ω  
3a  
3b  
4
+25 V  
-4 V  
+50 V  
-5 V  
5
+26.5 V  
+46.5 V  
+66.5 V  
+86.5 V  
SO T/R 7637/1  
Test Pulse  
TEST LEVELS RESULTS  
I
II  
C
C
C
C
C
E
III  
C
C
C
C
C
E
IV  
C
C
C
C
C
E
1
2
C
C
C
C
C
C
3a  
3b  
4
5
CLASS  
CONTENTS  
C
E
All functions of the device are performed as designed after exposure to disturbance.  
One or more functions of the device is not performed as designed after exposure and cannot be  
returned to proper operation without replacing the device.  
7/20  
VND810-E  
Figure 7. Waveforms  
NORMAL OPERATION  
INPUT  
n
OUTPUT VOLTAGE  
n
STATUS  
n
UNDERVOLTAGE  
V
V
USDhyst  
CC  
V
USD  
INPUT  
n
OUTPUT VOLTAGE  
n
STATUS  
n
undefined  
OVERVOLTAGE  
V
>V  
CC OV  
V
<V  
CC OV  
V
CC  
INPUT  
n
OUTPUT VOLTAGE  
n
STATUS  
n
OPEN LOAD with external pull-up  
INPUT  
n
V
>V  
OL  
OUT  
OUTPUVOLTAGE  
n
V
OL  
STATUS  
n
OPEN LOAD without external pull-up  
INPUT  
n
OUTPUT VOLTAGE  
n
STATUS  
n
OVERTEMPERATURE  
T
T
TSD  
R
T
j
INPUT  
n
OUTPUT CURRENT  
n
STATUS  
n
8/20  
VND810-E  
Figure 8. Application Schematic  
+5V +5V  
+5V  
V
CC  
R
prot  
STATUS1  
D
ld  
R
prot  
µC  
INPUT1  
OUTPUT1  
R
prot  
STATUS2  
R
prot  
INPUT2  
OUTPUT2  
GND  
R
GND  
D
V
GND  
GND  
If the calculated power dissipation leads to a large  
resistor or several devices have to share the same  
resistor then the ST suggests to utilize Solution 2 (see  
below).  
GND PROTECTION NETWORK AGAINST  
REVERSE BATTERY  
Solution 1: Resistor in e ground line (R  
can be used with any type of load.  
only). This  
GND  
Solution 2: A diode (D  
) in the ground line.  
GND  
The following is n indication on how to dimension the  
A resistor (R  
GND  
=1kΩ) should be inserted in parallel to  
GND  
R
resistor.  
GND  
D
if the device will be driving an inductive load.  
1) R  
2) R  
600mV / I  
.
S(on)max  
)
GND  
GND  
G
This small signal diode can be safely shared amongst  
several different HSD. Also in this case, the presence of  
the ground network will produce a shift ( 600mV) in the  
input threshold and the status output values if the  
microprocessor ground is not common with the device  
ground. This shift will not vary if more than one HSD  
shares the same diode/resistor network.  
Series resistor in INPUT and STATUS lines are also  
required to prevent that, during battery voltage transient,  
the current exceeds the Absolute Maximum Rating.  
Safest configuration for unused INPUT and STATUS pin  
is to leave them unconnected.  
≥ (−V ) / (-I  
CC  
were -I  
is the DC reverse ground pin current and can  
GND  
bfound in the absolute maximum rating section of the  
device’s datasheet.  
Power Dissipation in R  
(when V <0: during reverse  
CC  
GND  
battery situations) is:  
2
P = (-V ) /R  
D
CC  
GND  
This resistor can be shared amongst several different  
HSD. Please note that the value of this resistor should be  
calculated with formula (1) where I  
becomes the  
S(on)max  
sum of the maximum on-state currents of the different  
devices.  
LOAD DUMP PROTECTION  
Please note that if the microprocessor ground is not  
D
is necessary (Voltage Transient Suppressor) if the  
common with the device ground then the R  
will  
ld  
GND  
produce a shift (I  
* R  
) in the input thresholds  
GND  
load dump peak voltage exceeds V  
max DC rating.  
S(on)max  
CC  
and the status output values. This shift will vary  
The same applies if the device will be subject to  
transients on the V line that are greater than the ones  
depending on how many devices are ON in the case of  
CC  
several high side drivers sharing the same R  
.
GND  
shown in the ISO T/R 7637/1 table.  
9/20  
VND810-E  
positive supply voltage (V ) like the +5V line used to  
supply the microprocessor.  
The external resistor has to be selected according to the  
following requirements:  
1) no false open load indication when load is connected:  
µC I/Os PROTECTION:  
PU  
If a ground protection network is used and negative  
transient are present on the V line, the control pins will  
be pulled negative. ST suggests to insert a resistor (R  
in line to prevent the µC I/Os pins to latch-up.  
CC  
)
prot  
in this case we have to avoid V  
to be higher than  
OUT  
The value of these resistors is a compromise between  
the leakage current of µC and the current required by the  
HSD I/Os (Input levels compatibility) with the latch-up  
limit of µC I/Os.  
V
; this results in the following condition  
Olmin  
V
OUT  
=(V /(R +R ))R <V  
PU L PU L Olmin.  
2) no misdetection when load is disconnected: in this  
case the V has to be higher than V ; this  
OUT  
OLmax  
-V  
/I  
R  
(V  
-V -V  
) / I  
results in the following condition R <(V  
V
)/  
CCpeak latchup  
prot  
OHµC IH GND  
IHmax  
PU  
PU– OLmax  
I
.
L(off2)  
Calculation example:  
Because I  
may significantly increase if V  
is  
PU  
s(OFF)  
out  
For V  
= - 100V and I  
20mA; V 4.5V  
OHµC  
CCpeak  
latchup  
pulled high (up to several mA), the pull-up resistor R  
should be connected to a supply that is switched OFF  
when the module is in standby.  
5kΩ ≤ R  
65k.  
prot  
Recommended R  
value is 10kΩ.  
prot  
The values of V  
, V  
and I  
are available in  
L(off2)  
OLmin  
OLmax  
the Electrical Characteristics section.  
OPEN LOAD DETECTION IN OFF STATE  
Off state open load detection requires an external pull-up  
resistor (R ) connected between OUTPUT pin and a  
PU  
Figure 9. Open Load detection in off state  
V batt.  
VPU  
VC
RPU  
DRIVER  
+
IL(off2)  
INPUT  
LOGIC  
OUT  
+
-
R
STATUS  
VOL  
RL  
GROUND  
10/20  
VND810-E  
Figure 10. Off State Output Current  
Figure 13. High Level Input Current  
IL(off1) (uA)  
Iih (uA)  
1.6  
5
1.44  
4.5  
Off state  
Vin=3.25V  
1.28  
1.12  
0.96  
0.8  
Vcc=36V  
Vin=Vout=0V  
4
3.5  
3
2.5  
2
0.64  
0.48  
0.32  
0.16  
0
1.5  
1
0.5  
0
-50  
-25  
0
25  
50  
75  
100 125 150  
175  
175  
175  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
175  
175  
Tc (ºC)  
Tc (°C)  
Figure 11. Input Clamp Voltage  
Figure 14. Status Lakage Current  
Vicl (V)  
Ilstat (uA)  
8
0.05  
7.8  
Iin=1mA  
7.6  
0.04  
7.4  
7.2  
7
Vstat=5V  
0.03  
6.8  
6.6  
6.4  
6.2  
6
0.02  
0.01  
0
-50  
-25  
0
2
50  
75  
100  
125  
150  
-50  
-25  
0
25  
50  
75  
100 125 150  
Tc (°C)  
Tc (°C)  
Figure 12. Status Low Output Voltage  
Figure 15. Status Clamp Voltage  
Vstat (V)  
Vscl (V)  
0.8  
8
7.8  
0.7  
Istat=1mA  
Istat=1.6mA  
7.6  
0.6  
7.4  
7.2  
7
0.5  
0.4  
0.3  
0.2  
0.1  
0
6.8  
6.6  
6.4  
6.2  
6
-50  
-25  
0
25  
50  
75  
100  
125  
150  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
Tc (°C)  
Tc (°C)  
11/20  
VND810-E  
Figure 16. On State Resistance Vs T  
Figure 19. On State Resistance Vs V  
case  
CC  
Ron (mOhm)  
Ron (mOhm)  
300  
400  
275  
350  
Iout=0.5A  
250  
Iout=0.5A  
300  
Tc= 150°C  
Vcc=8V; 13V & 36V  
225  
250  
200  
175  
150  
200  
150  
100  
50  
Tc= 25°C  
125  
100  
Tc= - 40°C  
75  
0
50  
-50  
-25  
0
25  
50  
75  
100 125  
150  
175  
5
10  
15  
20  
25  
30  
35  
40  
Tc (°C)  
Vcc (V)  
Figure 17. Openload On State Detection  
Figure 20. OpenloOff State Detection  
Threshold  
Threshold  
Iol (mA)  
Vol (V)  
60  
5
55  
4.5  
Vin=0V  
Vcc=13V  
50  
4
Vin=5V  
45  
3.5  
3
40  
35  
30  
25  
20  
15  
10  
2.5  
2
1.5  
1
0.5  
0
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
Tc (°C)  
Tc (°C)  
Figure 8. Input High Level  
Figure 21. Input Low Level  
Vih (V)  
Vil (V)  
3.6  
2.6  
3.4  
3.2  
3
2.4  
2.2  
2
2.8  
2.6  
2.4  
2.2  
2
1.8  
1.6  
1.4  
1.2  
1
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
Tc (°C)  
Tc (°C)  
12/20  
VND810-E  
Figure 22. Input Hysteresis Voltage  
Figure 25. Overvoltage Shutdown  
Vhyst (V)  
Vov (V)  
1.5  
50  
1.4  
1.3  
1.2  
1.1  
1
48  
46  
44  
42  
40  
38  
36  
34  
32  
30  
0.9  
0.8  
0.7  
0.6  
0.5  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
Tc (°C)  
Tc (°C)  
Figure 23. Turn-on Voltage Slope  
Figure 26. Turn-ofoltage Slope  
dVout/dt(on) (V/ms)  
dVout/dt(off) (V/ms
1000  
500  
900  
450  
Vcc=13V  
Rl=13Ohm  
Vcc=13V  
Rl=13Ohm  
800  
400  
700  
350  
600  
500  
400  
300  
200  
100  
0
300  
250  
200  
150  
100  
50  
0
-50  
-25  
0
5  
50  
75  
100 125 150 175  
-50  
-25  
0
25  
50  
75  
100 125  
150  
175  
Tc (ºC)  
Tc (ºC)  
Figure 24. I  
Vs T  
case  
LIM  
Ilim (A)  
10  
9
8
7
6
5
4
3
2
1
0
Vcc=13V  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
Tc (°C)  
13/20  
VND810-E  
Figure 27. Maximum turn off current versus load inductance  
LMAX (A)  
I
10  
A
B
1
0.1  
1
10  
100  
L(mH)  
A = Single Pulse at T  
=150ºC  
Values are generated with R =0Ω  
L
Jstart  
B= Repetitive pulse at T  
=00ºC  
Jstart  
In case of repetitive pulses, T  
(at beginning of  
jstart  
each demagnetization) of every pulse must not  
exceed the temperature specified above for  
curves B and C.  
C= Repetitive Pulse at T  
=125ºC  
Jst  
Conditions:  
V
=13.5V  
CC  
V , I  
IN  
L
Demagnetization  
Demagnetization  
Demagnetization  
t
14/20  
VND810-E  
PowerSO-10™ Thermal Data  
Figure 28. SO-16 PC Board  
Layout condition of R and Z measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=1.6mm,  
th  
th  
2
2
Cu thickness=35µm, Copper areas: 0.26cm , 4cm ).  
Figure 29. R  
Vs PCB copper area in open box free air condition  
thj-amb  
RTH j-am b  
(°C/W)  
85  
80  
75  
70  
65  
60  
55  
50  
45  
40  
0
1
2
3
4
5
PCB Cu heatsink area (cm^2)  
15/20  
VND810-E  
Figure 30. SO-16 Thermal Impedance Junction Ambient Single Pulse  
ZTH (°C/W)  
1000  
100  
10  
2
0.26 cm  
2
4 cm  
1
0.1  
0.01  
0.0001 0.001  
0.01  
0.1  
1
10  
100  
1000  
Time (s)  
Figure 31. Thermal fittinmodel of a double  
channel HSD in SO6  
Pulse calculation formula  
ZTHδ = RTH δ + ZTHtp(1 δ)  
δ = tp T  
where  
Table 14. Thermal Parameter  
2
Area/island (cm )  
0.5  
0.35  
1.8  
4
25  
4
Tj_1  
C1  
R1  
C1  
R1  
C2  
R2  
C3  
R3  
C4  
R4  
C5  
R5  
C6  
R6  
R1 (°C/W)  
R2 (°C/W)  
R3 ( °C/W)  
R4 (°C/W)  
R5 (°C/W)  
R6 (°C/W)  
C1 (W.s/°C)  
Pd1  
4.5  
C2  
Tj_2  
10  
R2  
16  
Pd2  
48  
0.0001  
T_amb  
C2 (W.s/°C)  
C3 (W.s/°C)  
C4 (W.s/°C)  
C5 (W.s/°C)  
C6 (W.s/°C)  
7.00E-04  
6.00E-03  
0.2  
0.7  
2
16/20  
VND810-E  
PACKAGE MECHANICAL  
Table 15. SO-16 Mechanical Data  
Symbol  
millimeters  
Typ  
Min  
Max  
A
a1  
a2  
b
b1  
C
1.75  
0.2  
1.65  
0.46  
0..25  
0.1  
0.35  
0.19  
0.5  
c1  
D
E
45° (typ.)  
9.8  
5.8  
10  
6.2  
e
e3  
F
G
L
1.27  
8.89  
3.8  
4.6  
0.5  
4.0  
5.3  
1.27  
0.62  
M
S
8° (max.)  
Figure 32. SO-16 Package Dimensions  
17/20  
VND810-E  
Figure 33. SO-16 Suggested Pad Layout And Tube Shipment (no suffix)  
B
Base Q.ty  
50  
1000  
532  
3.2  
6
C
A
Bulk Q.ty  
Tube length (± 0.5)  
A
B
C (± 0.1)  
0.6  
All dimensions are in mm.  
Figure 34. Tape And Reel Shipment (suffix “TR”)  
REEL DIMESIONS  
.All dimensions are in mm.  
Base Q.ty  
Bulk Q.ty  
A (max)  
B (min)  
C (± 0.2)  
F
1000  
1000  
330  
1.5  
13  
20.2  
16.4  
60  
G (+ 2 / -0)  
N (min)  
T (max)  
22.4  
TAPE DIMENSIONS  
According to Electrnic Industries Association  
(EIA) Standar481 rev. A, Feb 1986  
Tape wdth  
W
P0 (± 0.1)  
P
16  
4
TaHole Spacing  
Component Spacing  
Hole Diameter  
8
D (± 0.1/-0) 1.5  
Hole Diameter  
D1 (min)  
F (± 0.05)  
K (max)  
1.5  
7.5  
6.5  
2
Hole Position  
Compartment Depth  
Hole Spacing  
P1 (± 0.1)  
End  
All dimensions are in mm.  
Start  
Top  
No components  
500mm min  
Components  
No components  
500mm min  
cover  
tape  
Empty components pockets  
saled with cover tape.  
User direction of feed  
18/20  
VND810-E  
REVISION HISTORY  
Date  
Revision  
Description of Changes  
Oct. 2004  
1
- First Issue  
19/20  
VND810-E  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is  
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are  
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products  
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics.  
All other names are the property of their respective owners  
2004 STMicroelectronics - All rights reserved  
STMicroelectronics group of companies  
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -  
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America  
www.st.com  
20/20  

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