VND830LSP [STMICROELECTRONICS]
Double channel high-side driver; 双通道高侧驱动器
| 型号： | VND830LSP |
| 厂家： | 
ST |
| 描述： | Double channel high-side driver |
| 文件： | 总27页 (文件大小：400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND830LSP
Double channel high-side driver
Features
Type
RDS(on)
IOUT
VCC
60 mΩ(1)
18 A(1)
36 V
10
VND830LSP
1. Per each channel.
1
PowerSO-10
■ CMOS compatible inputs
■ Open drain status outputs
■ On-state open-load detection
■ Off-state open-load detection
■ Shorted load protection
Description
The VND830LSP is a monolithic device designed
using|STMicroelectronics™ VIPower™ M0-3
Technology. The VND830LSP is intended for
driving any type of multiple load with one side
connected to ground.
■ Undervoltage and overvoltage shutdown
■ Loss of ground protection
■ Very low standby current
The Active V pin voltage clamp protects the
CC
■ Reverse battery protection
device against low energy spikes (see ISO7637
transient compatibility table). Active current
limitation combined with thermal shutdown and
automatic restart protects the device against
overload.
The open-load threshold is aimed at detecting the
5 W / 12 V standard bulb as an open-load fault in
the on-state.
The device detects the open-load condition in
both the on and off-state. In the off-state the
device detects if the output is shorted to V . The
CC
device automatically turns off in the case where
the ground pin becomes disconnected.
Table 1.
Device summary
Package
Order codes
Tape and reel
Tube
PowerSO-10
VND830LSP
VND830LSP13TR
October 2010
Doc ID 9431 Rev 4
1/27
www.st.com
1
Contents
VND830LSP
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
2.2
2.3
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16
3.1.1
3.1.2
Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 16
Solution 2: a diode (D ) in the ground line . . . . . . . . . . . . . . . . . . . . 17
GND
3.2
3.3
3.4
3.5
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 19
4
5
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1
PowerSO-10 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
5.2
5.3
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PowerSO-10 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27
Doc ID 9431 Rev 4
VND830LSP
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
- output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
Switching (V = 13 V; T = 25 °C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
j
Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 9431 Rev 4
3/27
List of figures
VND830LSP
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching time waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13.
I
vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LIM
case
Figure 14. On-state resistance vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CC
Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. On-state resistance vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
case
Figure 18. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 19. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23. Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. PowerSO-10 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 28.
R
vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 20
thj-amb
Figure 29. Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 30. Thermal fitting model of a double channel HSD in PowerSO-10 . . . . . . . . . . . . . . . . . . . . 21
Figure 31. PowerSO-10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 32. PowerSO-10 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 33. PowerSO-10 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 34. PowerSO-10 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4/27
Doc ID 9431 Rev 4
VND830LSP
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
Vcc
Vcc
CLAMP
OVERVOLTAGE
UNDERVOLTAGE
GND
CLAMP 1
OUTPUT1
INPUT1
STATUS1
DRIVER 1
CLAMP 2
CURRENT LIMITER 1
OPEN LOAD ON 1
DRIVER 2
LOGIC
OUTPUT2
OVERTEMP. 1
CURRENT LIMITER 2
OPEN LOAD ON 2
INPUT2
OPEN LOAD OFF 1
STATUS2
OPEN LOAD OFF 2
OVERTEMP. 2
Figure 2.
Configuration diagram (top view)
OUTPUT 1
OUTPUT 1
N.C.
5
4
3
6
7
8
9
GROUND
INPUT 1
STATUS 1
STATUS 2
INPUT 2
OUTPUT 2
OUTPUT 2
2
1
10
11
V
CC
Table 2.
Suggested connections for unused and not connected pins
Connection / pin
Status
N.C.
Output
Input
Floating
X
X
X
X
Through 10KΩ
To ground
X
resistor
Doc ID 9431 Rev 4
5/27
Electrical specifications
VND830LSP
2
Electrical specifications
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document.
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
- VCC
- IGND
IOUT
- IOUT
IIN
DC supply voltage
41
- 0.3
V
V
Reverse DC supply voltage
DC reverse ground pin current
DC output current
- 200
mA
A
Internally limited
- 6
Reverse DC output current
DC input current
A
+/- 10
mA
mA
ISTAT
DC Status current
+/- 10
Electrostatic discharge (human body model: R = 1.5 KΩ;
C = 100 pF)
– INPUT
– STATUS
– OUTPUT
– VCC
4000
4000
5000
5000
V
V
V
V
VESD
Maximum switching energy
EMAX
52
mJ
(L = 0.14 mH; RL = 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C;
IL = 14 A)
Ptot
Tj
Power dissipation (per island) at Tlead = 25 °C
Junction operating temperature
Case operating temperature
74
W
Internally limited
- 40 to 150
- 55 to 150
°C
Tc
Tstg
Storage temperature
°C
6/27
Doc ID 9431 Rev 4
VND830LSP
Electrical specifications
2.2
Thermal data
Table 4.
Symbol
Thermal data (per island)
Parameter
Value
Unit
Rthj-lead Thermal resistance junction-lead
Rthj-amb Thermal resistance junction-ambient
2
°C/W
°C/W
52(1)
37(2)
1. When mounted on a standard single-sided FR-4 board with 0.5 cm2 of Cu (at least 35 µm thick) connected
to all VCC pins. Horizontal mounting and no artificial air flow.
2. When mounted on a standard single-sided FR-4 board with 6 cm2 of Cu (at least 35 µm thick) connected to
all VCC pins. Horizontal mounting and no artificial air flow.
2.3
Electrical characteristics
Values specified in this section are for 8 V < V < 36 V; -40 °C < T < 150 °C, unless
CC
j
otherwise stated.
Figure 3.
Current and voltage conventions
I
S
VF1 (*)
I
V
IN1
CC
V
CC
INPUT 1
I
I
STAT1
V
OUT1
IN1
OUTPUT 1
OUTPUT 2
STATUS 1
INPUT 2
I
V
OUT1
V
IN2
STAT1
I
OUT2
I
V
STAT2
IN2
V
OUT2
STATUS 2
GND
V
STAT2
I
GND
Note:
= V
V
- V
during reverse battery condition.
Fn
CCn
OUTn
Doc ID 9431 Rev 4
7/27
Electrical specifications
VND830LSP
Table 5.
Symbol
Power output
Parameter
Test conditions
Min. Typ. Max. Unit
Operating supply
voltage
VCC
5.5
13
4
36
V
VUSD
VOV
Undervoltage shutdown
Overvoltage shutdown
3
5.5
V
V
36
IOUT = 2A; Tj = 25°C
60
mΩ
RON
On-state resistance
Supply current
IOUT = 2A; VCC > 8V
120 mΩ
Off-state; VCC = 13 V;
VIN = VOUT = 0 V
12
12
5
40
25
7
µA
µA
Off-state; VCC = 13 V;
VIN = VOUT = 0 V;
Tj = 25 °C
IS
On-state; VCC = 13 V; VIN = 5 V;
IOUT = 0 A
mA
IL(off1)
IL(off2)
Off-state output current VIN = VOUT = 0 V
0
50
0
µA
µA
Off-state output current VIN = 0V; VOUT = 3.5 V
-75
V
IN = VOUT = 0 V; VCC = 13 V;
IL(off3)
Off-state output current
Off-state output current
5
3
µA
µA
Tj = 125 °C
VIN = VOUT = 0 V; VCC = 13 V;
IL(off4)
Tj = 25 °C
Table 6.
Symbol
Protections
Parameter
Test conditions
Min. Typ. Max. Unit
TTSD
TR
Shutdown temperature
Reset temperature
Thermal hysteresis
150
135
7
175
200
°C
°C
°C
Thyst
15
Status delay in overload
conditions
tSDL
Tj > TTSD
CC = 13 V
20
µs
V
18
23
29
29
A
A
Ilim
Current limitation
5.5 V < VCC < 36 V
IOUT = 2 A; L = 6 mH
VCC - VCC - VCC
41 48 55
-
Vdemag Turn-off output clamp voltage
V
Note:
To ensure long term reliability under heavy overload or short circuit conditions, protection
and related diagnostic signals must be used together with a proper software strategy. If the
device is subjected to abnormal conditions, this software must limit the duration and number
of activation cycles.
8/27
Doc ID 9431 Rev 4
VND830LSP
Electrical specifications
Min. Typ. Max. Unit
Table 7.
Symbol
V
- output diode
Parameter
CC
Test conditions
VF
Forward on voltage
- IOUT = 1.3 A; Tj = 150 °C
—
—
0.6
V
Table 8.
Symbol
Switching (V = 13 V; T = 25 °C)
CC j
Parameter
Test conditions
Min.
Typ.
Max. Unit
RL = 6.5 Ω from VIN rising
edge to VOUT = 1.3 V
(see Figure 5)
td(on)
Turn-on delay time
Turn-off delay time
5
30
60
70
µs
µs
RL = 6.5 Ω from VIN falling
edge to VOUT = 11.7 V
(see Figure 5)
td(off)
10
0.15
0.1
30
RL = 6.5 Ω from VOUT = 1.3 V
dVOUT/dt(on) Turn-on voltage slope to VOUT = 10.4 V
See
Figure 10
1.5 V/µs
0.75 V/µs
(see Figure 5)
RL = 6.5 Ω from VOUT = 11.7 V
dVOUT/dt(off) Turn-off voltage slope to VOUT = 1.3 V
See
Figure 12
(see Figure 5)
Table 9.
Symbol
Logic inputs
Parameter
Test conditions
Min.
Typ.
Max. Unit
VIL
IIL
Input low level
1.25
V
µA
V
Low level input current
Input high level
VIN = 1.25 V
1
VIH
IIH
3.25
High level input current
VIN = 3.25 V
10
8
µA
V
VI(hyst) Input hysteresis voltage
0.5
6
IIN = 1 mA
6.8
V
VICL Input clamp voltage
IIN = -1 mA
-0.7
V
Table 10. Status pin
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
VSTAT
ILSTAT
CSTAT
Status low output voltage
Status leakage current
ISTAT = 1.6 mA
0.5
10
100
8
V
µA
pF
V
Normal operation; VSTAT = 5V
Status pin Input capacitance Normal operation; VSTAT = 5V
ISTAT = 1 mA
6
6.8
VSCL
Status clamp voltage
ISTAT = - 1 mA
-0.7
V
Doc ID 9431 Rev 4
9/27
Electrical specifications
VND830LSP
Table 11.
Symbol
Open-load detection
Parameter
Test conditions
Min. Typ. Max. Unit
IOL
Open-load on-state detection threshold VIN = 5 V
0.6
0.9
1.2
A
tDOL(on) Open-load on-state detection delay
IOUT = 0 A
IN = 0 V
200
µs
Open-load off-state voltage detection
VOL
V
1.5
2.5
3.5
V
threshold
tDOL(off) Open-load detection delay at turn-off
1000
µs
Figure 4.
Status timings
OPEN LOAD STATUS TIMING (with external pull-up)
< I
OVER TEMP STATUS TIMING
T > T
I
V
> V
OL
OUT
OL
OUT
j
TSD
V
INn
V
V
INn
V
STATn
STATn
t
t
SDL
SDL
t
DOL(off)
t
DOL(on)
Figure 5.
Switching time waveforms
10/27
Doc ID 9431 Rev 4
VND830LSP
Electrical specifications
Status
Table 12. Truth table
Conditions
Input
Output
L
L
H
H
Normal operation
Current limitation
H
H
L
H
H
L
X
X
H
(Tj < TTSD) H
(Tj > TTSD) L
L
L
L
H
L
Overtemperature
Undervoltage
H
L
L
L
X
X
H
L
L
L
H
H
Overvoltage
H
L
H
H
L
Output voltage > VOL
Output current < IOL
H
H
L
L
H
L
H
H
Table 13. Electrical transient requirements
ISO T/R
7637/1
Test level
I
II
III
IV
Delays and impedance
Test pulse
1
2
- 25V(1)
+ 25V(1)
- 25V(1)
+ 25V(1)
- 4V(1)
- 50V(1)
+ 50V(1)
- 50V(1)
+ 50V(1)
- 5V(1)
- 75V(1)
+ 75V(1)
- 100V(1)
+ 75V(1)
- 6V(1)
- 100V(1)
+ 100V(1)
- 150V(1)
+ 100V(1)
- 7V(1)
2ms, 10Ω
0.2ms, 10Ω
0.1µs, 50Ω
0.1µs, 50Ω
100ms, 0.01Ω
400ms, 2Ω
3a
3b
4
5
+ 26.5V(1)
+ 46.5V(2)
+ 66.5V(2)
+ 86.5V(2)
1. All functions of the device are performed as designed after exposure to disturbance.
2. One or more functions of the device is not performed as designed after exposure and cannot be returned to
proper operation without replacing the device.
Doc ID 9431 Rev 4
11/27
Electrical specifications
Figure 6.
VND830LSP
Waveforms
NORMAL OPERATION
UNDERVOLTAGE
INPUT
n
LOAD VOLTAGE
n
STATUS
n
V
V
USDhyst
CC
V
USD
INPUT
n
LOAD VOLTAGE
STATUS
n
undefined
OVERVOLTAGE
V
<V
OV
V
> V
OV
CC
CC
V
CC
INPUT
n
LOAD VOLTAGE
n
STATUS
n
OPEN LOAD with external pull-up
INPUT
n
V
> V
OL
OUT
LOAD VOLTAGE
n
V
OL
STATUS
n
OPEN LOAD without external pull-up
INPUT
n
LOAD VOLTAGE
n
STATUS
n
OVERTEMPERATURE
T
T
TSD
R
T
j
INPUT
n
LOAD CURRENT
n
STATUS
n
12/27
Doc ID 9431 Rev 4
VND830LSP
Electrical specifications
2.4
Electrical characteristics curves
Figure 7.
Off-state output current
Figure 8.
High level input current
Iih (µA)
IL(off1)
1.35
6
5.25
4.5
3.75
3
1.2
1.05
0.9
Off State
Vcc=13V
Vin=Vout=0V
Vin=3.25V
0.75
0.6
2.25
1.5
0.75
0
0.45
0.3
0.15
0
-50
-25
0
25
50
75
100 125 150
175
-50
-25
0
25
50
75
100 125 150
175
Tc (ºC)
Tc (ºC)
Figure 9.
Input clamp voltage
Figure 10. Turn-on voltage slope
Vicl (V)
8
dVout/dt(on) (V/ms)
800
7.8
7.6
7.4
7.2
7
700
Iin=1mA
Vcc=13V
Rl=6.5Ohm
600
500
400
300
200
100
0
6.8
6.6
6.4
6.2
6
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100 125
150
175
Tc (°C)
Tc (ºC)
Figure 11. Overvoltage shutdown
Figure 12. Turn-off voltage slope
dVout/dt(off) (V/ms)
800
Vov (V)
50
48
46
44
42
40
38
36
34
32
30
700
Vcc=13V
Rl=6.5Ohm
600
500
400
300
200
100
0
-50
-25
0
25
50
75
100 125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (°C)
Doc ID 9431 Rev 4
13/27
Electrical specifications
VND830LSP
Figure 13. I
vs T
Figure 14. On-state resistance vs V
LIM
case
CC
Ilim (A)
35
Ron (mOhm)
160
32.5
30
140
Vcc=13V
Iout=2A
120
27.5
25
100
Tc=150ºC
22.5
20
80
60
Tc=25ºC
17.5
15
40
Tc= -40ºC
20
0
12.5
10
-50
-25
0
25
50
75
100 125 150
175
0
5
10
15
20
25
30
35
40
Tc (ºC)
Vcc (V)
Figure 15. Input high level
Figure 16. Input hysteresis voltage
Vih (V)
4
Vhyst (V)
1.5
3.8
3.6
3.4
3.2
3
1.4
1.3
1.2
1.1
1
2.8
2.6
2.4
2.2
2
0.9
0.8
0.7
0.6
0.5
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (°C)
Figure 17. On-state resistance vs T
Figure 18. Input low level
case
Vil (V)
2.25
Ron (mOhm)
100
90
2.125
2
Iout=2A
Vcc=13V
80
70
1.875
1.75
1.625
1.5
60
50
40
30
20
10
0
1.375
1.25
-50
-25
0
25
50
75
100 125 150 175
-50
-25
0
25
50
75
100 125
150
175
Tc (ºC)
Tc (ºC)
14/27
Doc ID 9431 Rev 4
VND830LSP
Electrical specifications
Figure 19. Status leakage current
Figure 20. Status low output voltage
Ilstat (µA)
0.07
Vstat (V)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.06
Istat=1.6mA
Vstat=5V
0.05
0.04
0.03
0.02
0.01
0
0
-50
-25
0
25
50
75
100 125 150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (ºC)
Figure 21. Status clamp voltage
Figure 22. Open-load on-state detection
threshold
Iol (A)
2
Vscl (V)
8
7.8
1.75
Istat=1mA
Vin=5V
1.5
7.6
7.4
7.2
7
1.25
1
6.8
6.6
6.4
6.2
6
0.75
0.5
0.25
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100 125 150
175
Tc (°C)
Tc (ºC)
Figure 23. Open-load off-state voltage
detection threshold
Vol (V)
5
4.5
Vin=0V
4
3.5
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Doc ID 9431 Rev 4
15/27
Application information
VND830LSP
3
Application information
Figure 24. Application schematic
+5V +5V
+5V
VCC
Rprot
STATUS1
Dld
Rprot
μC
INPUT1
OUTPUT1
Rprot
STATUS2
Rprot
INPUT2
OUTPUT2
GND
RGND
DGND
VGND
3.1
GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1
Solution 1: a resistor in the ground line (R
only)
GND
This can be used with any type of load.
The following show how to dimension the R
resistor:
GND
1.
2.
R
R
≤ 600 mV / 2 (I
≥ ( -V ) / ( -I
)
S(on)max
GND
GND
)
CC
GND
where - I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device datasheet.
Power dissipation in R
(when V < 0 during reverse battery situations) is:
CC
GND
2
P = ( -V ) / R
D
CC
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
becomes the sum of the
S(on)max
16/27
Doc ID 9431 Rev 4
VND830LSP
Application information
Please note that, if the microprocessor ground is not shared by the device ground, then the
R
produces a shift (I
* R
) in the input thresholds and the status output
GND
S(on)max
GND
values. This shift varies depending on how many devices are ON in the case of several high
side drivers sharing the same R
.
GND
If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.
3.1.2
Solution 2: a diode (D
) in the ground line
GND
A resistor (R
= 1 kΩ) should be inserted in parallel to D if the device is driving an
GND
GND
inductive load. This small signal diode can be safely shared amongst several different HSD.
Also in this case, the presence of the ground network produces a shift (≈600 mV) in the
input threshold and the status output values if the microprocessor ground is not common
with the device ground. This shift not varies if more than one HSD shares the same
diode/resistor network. Series resistor in INPUT and STATUS lines are also required to
prevent that, during battery voltage transient, the current exceeds the Absolute Maximum
Rating. Safest configuration for unused INPUT and STATUS pin is to leave them
unconnected.
3.2
3.3
Load dump protection
D is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
ld
V
maximum DC rating. The same applies if the device is subject to transients on the V
CC
CC
line that are greater than those shown in the ISO T/R 7637/1 table.
MCU I/O protection
If a ground protection network is used and negative transients are present on the V line,
CC
the control pins are pulled negative. ST suggests to insert a resistor (R ) in line to prevent
prot
the microcontroller I/O pins from latching up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os:
- V
/ I
≤ R
≤ (V
- V - V
) / I
CCpeak latchup
prot
OHμC
IH
GND IHmax
Example
For the following conditions:
V
I
= -100 V
CCpeak
≥ 20 mA
≥ 4.5 V
latchup
V
OHμC
5 kΩ ≤ R
≤ 65 kΩ.
prot
Recommended values are:
= 10 kΩ
R
prot
Doc ID 9431 Rev 4
17/27
Application information
VND830LSP
3.4
Open-load detection in off-state
Off-state open-load detection requires an external pull-up resistor (R ) connected between
PU
OUTPUT pin and a positive supply voltage (V ) like the +5 V line used to supply the
PU
microprocessor.
The external resistor has to be selected according to the following requirements:
1) no false open-load indication when load is connected: in this case we have to avoid V
OUT
to be higher than V
; this results in the following condition
Olmin
V
= (V / (R + R ))R < V
PU L PU L Olmin.
OUT
2) no misdetection when load is disconnected: in this case the V
has to be higher than
OUT
V
; this results in the following condition R < (V - V
) / I
.
OLmax
PU
PU
OLmax
L(off2)
Because I
may significantly increase if V is pulled high (up to several mA), the pull-
out
s(OFF)
up resistor R should be connected to a supply that is switched OFF when the module is in
PU
standby.
Figure 25. Open-load detection in off-state
V batt.
V
PU
VCC
R
PU
DRIVER
+
IL(off2)
INPUT
LOGIC
OUT
+
-
R
STATUS
VOL
RL
GROUND
18/27
Doc ID 9431 Rev 4
VND830LSP
Application information
3.5
Maximum demagnetization energy (VCC = 13.5 V)
Figure 26. Maximum turn-off current versus load inductance
I LM AX (A)
100
10
A
B
C
1
0,01
0,1
1
10
100
L(mH)
A = single pulse at T
= 150 °C
Jstart
B= repetitive pulse at T
= 100 °C
Jstart
Jstart
C= repetitive pulse at T
= 125 °C
V , I
IN
L
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with R = 0Ω.
L
In case of repetitive pulses, T
(at beginning of each demagnetization) of every pulse must not exceed the temperature
jstart
specified above for curves B and C.
Doc ID 9431 Rev 4
19/27
Package and PCB thermal data
VND830LSP
4
Package and PCB thermal data
4.1
PowerSO-10 thermal data
Figure 27. PowerSO-10 PC board
Note:
Layout condition of R and Z measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu thickness =
35 µm, Copper areas: from minimum pad lay-out to 8 cm ).
th
th
2
Figure 28. R
vs PCB copper area in open box free air condition
thj-amb
RTHj_amb (°C/W)
55
Tj-Tamb=50°C
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
20/27
Doc ID 9431 Rev 4
VND830LSP
Package and PCB thermal data
Figure 29. Thermal impedance junction ambient single pulse
ZTH (°C/W)
1000
100
10
1
0.5 cm2
6 cm2
0.1
0.0001 0.001
0.01
0.1
1
10
100
1000
Time (s)
Equation 1: pulse calculation formula
ZTHδ = RTH ⋅ δ + ZTHtp(1 – δ)
δ = tp ⁄ T
where
Figure 30. Thermal fitting model of a double channel HSD in PowerSO-10
Tj_1
C1
R1
C1
R1
C2
R2
C3
R3
C4
R4
C5
R5
C6
R6
Pd1
C2
Tj_2
R2
Pd2
T_amb
Doc ID 9431 Rev 4
21/27
Package and PCB thermal data
VND830LSP
Table 14. Thermal parameters
Area / island (cm2)
Footprint
6
R1 (°C/W)
R2 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.15
0.8
0.7
0.8
12
37
22
0.0006
2.1E-03
0.013
0.3
0.75
3
5
22/27
Doc ID 9431 Rev 4
VND830LSP
Package and packing information
5
Package and packing information
5.1
5.2
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
PowerSO-10 mechanical data
Figure 31. PowerSO-10 package dimensions
B
0.10
E
A B
10
H
E
E2
E4
1
SEATING
PLANE
DETAIL "A"
e
B
A
C
0.25
D
=
=
=
=
h
D1
SEATING
PLANE
A
F
A1
L
A1
DETAIL "A"
α
Doc ID 9431 Rev 4
23/27
Package and packing information
VND830LSP
Table 15. PowerSO-10 mechanical data
mm
Dim.
Min.
3.35
3.4
Typ.
Max.
3.65
3.6
A
A(1)
A1
B
0
0.10
0.60
0.53
0.55
0.32
9.60
7.60
9.50
7.60
7.50
6.10
6.30
0.40
0.37
0.35
0.23
9.40
7.40
9.30
7.20
7.30
5.90
5.90
B(1)
C
C(1)
D
D1
E
E2
E2(1)
E4
E4(1)
e
1.27
F
1.25
1.20
1.35
1.40
F(1)
H
13.80
13.85
14.40
14.35
H(1)
h
0.50
L
1.20
0.80
0°
1.80
1.10
8°
L(1)
α
α(1)
2°
8°
1. Muar only POA P013P.
24/27
Doc ID 9431 Rev 4
VND830LSP
Package and packing information
5.3
PowerSO-10 packing information
Figure 32. PowerSO-10suggested Figure 33. PowerSO-10 tube shipment
pad layout
(no suffix)
14.6 - 14.9
CASABLANCA
MUAR
B
10.8 - 11
6.30
C
A
C
A
0.67 - 0.73
0.54 - 0.6
B
1
2
3
10
9
All dimensions are in mm.
Base Q.ty Bulk Q.ty Tube length (± 0.5)
8
9.5
A
B
C (± 0.1)
0.8
7
4
5
1.27
6
Casablanca
Muar
50
50
1000
1000
532
532
10.4 16.4
4.9 17.2
0.8
Figure 34. PowerSO-10 tape and reel shipment (suffix “TR”)
Reel dimensions
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
600
600
330
1.5
13
20.2
24.4
60
G (+ 2 / -0)
N (min)
T (max)
30.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
24
4
Tape Hole Spacing
Component Spacing
Hole Diameter
P0 (± 0.1)
P
24
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
1.5
1.5
11.5
6.5
2
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
All dimensions are in mm.
End
Start
Top
No components
500mm min
Components
No components
500mm min
cover
tape
Empty components pockets
saled with cover tape.
User direction of feed
Doc ID 9431 Rev 4
25/27
Revision history
VND830LSP
6
Revision history
Table 16. Document revision history
Date
Revision
Changes
09-Sep-2004
1
Initial release.
Current and voltage convention update (page 2).
Configuration diagram (top view) & suggested connections for unused
and n.c. pins insertion (page 2).
6 cm2 Cu condition insertion in thermal data table (page 3).
VCC - output diode section update (page 4).
Protections note insertion (page 4).
03-Mar-2008
2
Revision history table insertion (page 18).
Disclaimers update (page 19).
Document reformatted and restructured.
Added contents, list of tables and figures.
Added ECOPACK® packages information.
09-Dec-2008
08-Oct-2010
3
4
Updated Figure 5: Switching time waveforms.
26/27
Doc ID 9431 Rev 4
VND830LSP
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Doc ID 9431 Rev 4
27/27
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