VND830-E [STMICROELECTRONICS]

DOUBLE CHANNEL HIGH SIDE DRIVER; 双通道高侧驱动器
VND830-E
型号: VND830-E
厂家: ST    ST
描述:

DOUBLE CHANNEL HIGH SIDE DRIVER
双通道高侧驱动器

驱动器
文件: 总20页 (文件大小:271K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
VND830-E  
DOUBLE CHANNEL HIGH SIDE DRIVER  
Figure 1. Package  
Table 1. General Features  
Type  
R
I
V
CC  
DS(on)  
out  
VND830-E  
60m(*)  
6A (*)  
36V  
(*) Per each channel  
CMOS COMPATIBLE INPUTS  
OPEN DRAIN STATUS OUTPUTS  
ON STATE OPEN LOAD DETECTION  
OFF STATE OPEN LOAD DETECTION  
SHORTED LOAD PROTECTION  
UNDERVOLTAGE AND OVERVOLTAGE  
SHUTDOWN  
LOSS OF GROUND PROTECTION  
VERY LOW STAND-BY CURRENT  
REVERSE BATTERY PROTECTION (**)  
IN COMPLIANCE WITH THE 2002/95/EC  
EUROPEAN DIRECTIVE  
SO-16L  
DESCRIPTION  
The VND830-E is a monolithic device made by  
Active current limitation combined with thermal  
shutdown and automatic restart protects the  
device against overload. The device detects open  
load condition both is on and off state. Output  
using  
STMicroelectronics  
VIPower  
M0-3  
Technology, intended for driving any kind of load  
with one side connected to ground. Active V pin  
CC  
voltage clamp protects the devices against low  
shorted to V is detected in the off state. Device  
CC  
energy  
spikes  
(see  
ISO7637  
transient  
automatically turns off in case of ground pin  
disconnection.  
compatibility table).  
Table 2. Order Codes  
Package  
Tube  
Tape and Reel  
VND830-E  
VND830TR-E  
SO-16L  
Note: (*) See application schematic at page 9  
Rev. 3  
1/20  
February 2005  
VND830-E  
Figure 2. Block Diagram  
VCC  
VCC  
CLAMP  
OVERVOLTAGE  
UNDERVOLTAGE  
CLAMP 1  
GND  
OUTPUT1  
OUTPUT2  
INPUT1  
DRIVER 1  
CLAMP 2  
STATUS1  
CURRENT LIMITER 1  
OPENLOAD ON 1  
DRIVER 2  
LOGIC  
OVERTEMP. 1  
CURRENT LIMITER 2  
OPENLOAD ON 2  
INPUT2  
OPENLOAD OFF 1  
STATUS2  
OPENLOAD OFF 2  
OVERTEMP. 2  
Table 3. Absolute Maximum Ratings  
Symbol  
Parameter  
Value  
Unit  
V
V
CC  
DC Supply Voltage  
41  
- 0.3  
- V  
Reverse DC Supply Voltage  
DC Reverse Ground Pin Current  
DC Output Current  
V
CC  
GND  
OUT  
- I  
- 200  
mA  
A
I
Internally Limited  
- 6  
- I  
OUT  
Reverse DC Output Current  
DC Input Current  
A
I
IN  
+/- 10  
mA  
mA  
I
DC Status Current  
+/- 10  
STAT  
Electrostatic Discharge (Human Body Model:  
R=1.5KΩ; C=100pF)  
- INPUT  
4000  
4000  
5000  
5000  
V
V
V
V
V
ESD  
MAX  
- STATUS  
- OUTPUT  
- V  
CC  
Maximum Switching Energy  
E
102  
mJ  
(L=1.8mH; R =0; V =13.5V; T =150ºC;  
jstart  
L
L
bat  
I =9A)  
P
Power Dissipation T  
=25°C  
8.3  
W
°C  
°C  
°C  
tot  
lead  
T
Junction Operating Temperature  
Case Operating Temperature  
Storage Temperature  
Internally Limited  
- 40 to 150  
j
T
c
T
- 55 to 150  
stg  
2/20  
VND830-E  
Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins  
1
VCC  
VCC  
16  
OUTPUT 1  
OUTPUT 1  
OUTPUT 1  
OUTPUT 2  
OUTPUT 2  
OUTPUT 2  
VCC  
N.C.  
GND  
INPUT 1  
STATUS 1  
STATUS 2  
INPUT 2  
VCC  
8
9
Connection / Pin Status N.C. Output  
Input  
Floating  
X
X
X
X
X
To Ground  
Through 10Kresistor  
Figure 4. Current and Voltage Conventions  
I
S
V
F1  
(*)  
I
IN1  
V
CC  
V
CC  
INPUT 1  
I
OUT1  
I
STAT1  
V
IN1  
OUTPUT 1  
STATUS 1  
INPUT 2  
V
OUT1  
I
V
IN2  
STAT1  
I
OUT2  
I
V
IN2  
STAT2  
OUTPUT 2  
V
OUT2  
STATUS 2  
GND  
V
STAT2  
I
GND  
(*) V = V  
- V  
during reverse battery condition  
Fn  
CCn  
OUTn  
Table 4. Thermal Data  
Symbol  
Parameter  
Value  
Unit  
°C/W  
°C/W  
R
R
Thermal resistance junction-lead  
Thermal resistance junction-ambient  
(MAX)  
(MAX)  
15  
thj-lead  
65 (*)  
48 (**)  
thj-amb  
(*)  
2
Note: When mounted on a standard single-sided FR-4 board with 0.5cm of Cu (at least 35µm thick) connected to all V pins. Horizontal  
CC  
mounting and no artificial air flow.  
(**)  
2
Note:  
When mounted on a standard single-sided FR-4 board with 6 cm of Cu (at least 35µm thick) connected to all V pins. Horizontal  
CC  
mounting and no artificial air flow.  
3/20  
VND830-E  
ELECTRICAL CHARACTERISTICS  
(8V<V <36V; -40°C< T <150°C, unless otherwise specified)  
CC  
j
(Per each channel)  
Table 5. Power Output  
Symbol  
(**)  
Parameter  
Test Conditions  
Min.  
5.5  
3
Typ.  
13  
4
Max.  
36  
Unit  
V
V
CC  
Operating Supply Voltage  
V
(**) Undervoltage Shut-down  
5.5  
V
USD  
V
(**)  
Overvoltage Shut-down  
On State Resistance  
36  
V
OV  
I
I
=2A; T =25 °C  
60  
mΩ  
mΩ  
OUT  
j
R
ON  
=2A; V > 8V  
120  
OUT  
CC  
12  
40  
µA  
Off State; V =13V; V =V  
=0V  
OUT  
CC  
IN  
Off State; V =13V; V =V  
T =25°C  
j
=0V;  
OUT  
CC  
IN  
I (**)  
S
Supply Current  
12  
5
25  
7
µA  
mA  
On State; V =13V; V =5V; I  
=0A  
OUT  
CC  
IN  
I
Off State Output Current  
Off State Output Current  
Off State Output Current  
Off State Output Current  
V =V =0V  
OUT  
0
50  
0
µA  
µA  
µA  
µA  
L(off1)  
IN  
I
V =0V; V  
=3.5V  
-75  
L(off2)  
IN  
OUT  
I
V =V  
=0V; V =13V; T =125°C  
OUT  
5
L(off3)  
IN  
CC  
j
I
V =V  
=0V; V =13V; T =25°C  
OUT  
3
L(off4)  
IN  
CC  
j
Note: (**) Per device.  
Table 6. Protection (Per each channel) (See note 1)  
Symbol  
Parameter  
Test Conditions  
Min.  
150  
135  
7
Typ.  
Max.  
Unit  
°C  
T
Shut-down Temperature  
Reset Temperature  
Thermal Hysteresis  
175  
200  
TSD  
T
°C  
R
T
15  
9
°C  
hyst  
SDL  
Status Delay in Overload  
Conditions  
T >T  
j
TSD  
T
20  
µs  
V
CC  
=13V  
6
15  
15  
A
A
I
Current limitation  
lim  
5.5V < V < 36V  
CC  
Turn-off Output Clamp  
Voltage  
V
I
=2A; L= 6mH  
V
-41  
V
-48  
V -55  
CC  
V
demag  
OUT  
CC  
CC  
Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be  
used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration  
and number of activation cycles  
Table 7. V - Output Diode  
CC  
Symbol  
Parameter  
Test Conditions  
=1.3A; T =150°C  
Min  
Typ  
Max  
Unit  
V
F
Forward on Voltage  
-I  
OUT  
0.6  
V
j
4/20  
VND830-E  
ELECTRICAL CHARACTERISTICS (continued)  
Table 8. Status Pin  
Symbol  
Parameter  
Test Conditions  
= 1.6 mA  
STAT  
Min  
Typ  
Max  
Unit  
V
V
I
Status Low Output Voltage  
Status Leakage Current  
I
0.5  
10  
STAT  
Normal Operation; V  
= 5V  
STAT  
µA  
LSTAT  
Status Pin Input  
Capacitance  
C
Normal Operation; V  
= 5V  
STAT  
100  
8
pF  
STAT  
I
I
= 1mA  
6
6.8  
V
V
STAT  
V
Status Clamp Voltage  
SCL  
= - 1mA  
-0.7  
STAT  
Table 9. Switching (V =13V)  
CC  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Unit  
R =6.5from V rising edge to  
OUT  
L
IN  
t
Turn-on Delay Time  
30  
µs  
d(on)  
V
=1.3V  
R =6.5from V falling edge to  
OUT  
L
IN  
t
Turn-off Delay Time  
30  
µs  
d(off)  
V
=11.7V  
See  
R =6.5from V  
OUT  
=1.3V to  
L
OUT  
dV/dt  
Turn-on Voltage Slope  
relative  
diagram  
See  
relative  
diagram  
V/µs  
(on)  
V
=10.4V  
R =6.5from V  
=11.7V to  
L
OUT  
dV/dt  
Turn-off Voltage Slope  
V/µs  
(off)  
V
OUT  
=1.3V  
Table 10. Openload Detection  
Symbol  
Parameter  
Openload ON State  
Detection Threshold  
Openload ON State  
Detection Delay  
Test Conditions  
Min  
Typ  
Max  
Unit  
I
V =5V  
50  
100  
200  
mA  
OL  
IN  
t
t
I =0A  
OUT  
200  
3.5  
µs  
V
DOL(on)  
Openload OFF State  
Voltage Detection  
Threshold  
V
OL  
V =0V  
IN  
1.5  
2.5  
Openload Detection  
Delay at Turn Off  
1000  
µs  
DOL(off)  
Table 11. Logic Input  
Symbol  
Parameter  
Input Low Level  
Test Conditions  
Min  
Typ  
Max  
Unit  
V
V
I
1.25  
IL  
Low Level Input Current V = 1.25V  
1
µA  
V
IL  
IN  
V
Input High Level  
3.25  
IH  
High Level Input Cur-  
rent  
I
V
= 3.25V  
10  
8
µA  
IH  
IN  
Input Hysteresis Volt-  
age  
0.5  
6
V
hyst  
V
I
I
= 1mA  
6.8  
V
V
IN  
V
Input Clamp Voltage  
ICL  
= -1mA  
-0.7  
IN  
5/20  
VND830-E  
Table 12. Truth Table  
CONDITIONS  
INPUT  
OUTPUT  
SENSE  
L
H
L
H
H
H
Normal Operation  
Current Limitation  
L
H
H
L
X
X
H
) H  
) L  
(T < T  
(T > T  
j
j
TSD  
TSD  
L
H
L
L
H
L
Overtemperature  
Undervoltage  
Overvoltage  
L
H
L
L
X
X
L
H
L
L
H
H
L
H
H
H
L
H
Output Voltage > V  
OL  
L
H
L
H
H
L
Output Current < I  
OL  
Figure 5. Switching time Waveforms  
V
OUTn  
90%  
80%  
dV /dt  
OUT (off)  
dV  
/dt  
OUT (on)  
10%  
t
V
INn  
t
d(on)  
t
d(off)  
t
6/20  
VND830-E  
Table 13. Electrical Transient Requirements On V  
ISO T/R 7637/1  
Pin  
CC  
TEST LEVELS  
III  
Test Pulse  
I
II  
IV  
Delays and  
Impedance  
1
2
-25 V  
+25 V  
-25 V  
-50 V  
+50 V  
-50 V  
-75 V  
+75 V  
-100 V  
+75 V  
-6 V  
-100 V  
+100 V  
-150 V  
+100 V  
-7 V  
2 ms 10 Ω  
0.2 ms 10 Ω  
0.1 µs 50 Ω  
0.1 µs 50 Ω  
100 ms, 0.01 Ω  
400 ms, 2 Ω  
3a  
3b  
4
+25 V  
-4 V  
+50 V  
-5 V  
5
+26.5 V  
+46.5 V  
+66.5 V  
+86.5 V  
ISO T/R 7637/1  
Test Pulse  
TEST LEVELS RESULTS  
I
II  
C
C
C
C
C
E
III  
C
C
C
C
C
E
IV  
C
C
C
C
C
E
1
2
C
C
C
C
C
C
3a  
3b  
4
5
CLASS  
CONTENTS  
C
E
All functions of the device are performed as designed after exposure to disturbance.  
One or more functions of the device is not performed as designed after exposure and cannot be  
returned to proper operation without replacing the device.  
7/20  
VND830-E  
Figure 6. Waveforms  
NORMAL OPERATION  
INPUT  
n
OUTPUT VOLTAGE  
n
STATUS  
n
UNDERVOLTAGE  
V
V
USDhyst  
CC  
V
USD  
INPUT  
n
OUTPUT VOLTAGE  
n
STATUS  
n
undefined  
OVERVOLTAGE  
V
<V  
OV  
CC  
V
CC  
INPUT  
n
OUTPUT VOLTAGE  
n
STATUS  
n
OPEN LOAD with external pull-up  
INPUT  
n
V
OUT  
>V  
OL  
OUTPUT VOLTAGE  
n
V
OL  
STATUS  
n
OPEN LOAD without external pull-up  
INPUT  
n
OUTPUT VOLTAGE  
n
STATUS  
n
OVERTEMPERATURE  
T
TSD  
T
R
T
j
INPUT  
n
OUTPUT CURRENT  
n
STATUS  
n
8/20  
VND830-E  
Figure 7. Application Schematic  
+5V +5V  
+5V  
V
CC  
R
prot  
STATUS1  
D
ld  
R
prot  
µC  
INPUT1  
OUTPUT1  
R
prot  
STATUS2  
R
prot  
INPUT2  
OUTPUT2  
GND  
R
GND  
D
V
GND  
GND  
If the calculated power dissipation leads to a large  
resistor or several devices have to share the same  
resistor then the ST suggest to utilize Solution 2 (see  
below).  
GND PROTECTION NETWORK AGAINST  
REVERSE BATTERY  
Solution 1: Resistor in the ground line (R  
can be used with any type of load.  
only). This  
GND  
Solution 2: A diode (D  
) in the ground line.  
GND  
The following is an indication on how to dimension the  
A resistor (R  
GND  
=1kΩ) should be inserted in parallel to  
GND  
R
resistor.  
GND  
D
if the device will be driving an inductive load.  
1) R  
2) R  
600mV / I  
.
S(on)max  
)
GND  
GND  
GND  
This small signal diode can be safely shared amongst  
several different HSD. Also in this case, the presence of  
the ground network will produce a shift (j600mV) in the  
input threshold and the status output values if the  
microprocessor ground is not common with the device  
ground. This shift will not vary if more than one HSD  
shares the same diode/resistor network.  
Series resistor in INPUT and STATUS lines are also  
required to prevent that, during battery voltage transient,  
the current exceeds the Absolute Maximum Rating.  
≥ (−V ) / (-I  
CC  
where -I  
is the DC reverse ground pin current and can  
GND  
be found in the absolute maximum rating section of the of  
the device’s datasheet.  
Power Dissipation in R  
(when V <0: during reverse  
CC  
GND  
battery situations) is:  
2
P = (-V ) /R  
D
CC  
GND  
This resistor can be shared amongst several different  
HSD. Please note that the value of this resistor should be  
Safest configuration for unused INPUT and STATUS pin  
is to leave them unconnected.  
calculated with formula (1) where I  
becomes the  
S(on)max  
sum of the maximum on-state currents of the different  
devices.  
LOAD DUMP PROTECTION  
Please note that if the microprocessor ground is not  
D
is necessary (Voltage Transient Suppressor) if the  
ld  
common with the device ground then the R  
will  
GND  
load dump peak voltage exceeds V  
max DC rating.  
CC  
produce a shift (I  
* R  
) in the input thresholds  
GND  
S(on)max  
The same applies if the device will be subject to  
and the status output values. This shift will vary  
transients on the V line that are greater than the ones  
CC  
depending on many devices are ON in the case of several  
shown in the ISO T/R 7637/1 table.  
high side drivers sharing the same R  
.
GND  
9/20  
VND830-E  
.µC I/Os PROTECTION:  
supply the microprocessor.  
The external resistor has to be selected according to the  
following requirements:  
If a ground protection network is used and negative  
transient are present on the V line, the control pins will  
CC  
be pulled negative. ST suggests to insert a resistor (R  
)
prot  
1) no false open load indication when load is connected:  
in line to prevent the µC I/Os pins to latch-up.  
in this case we have to avoid V  
to be higher than  
OUT  
The value of these resistors is a compromise between the  
leakage current of µC and the current required by the  
HSD I/Os (Input levels compatibility) with the latch-up  
limit of µC I/Os.  
V
; this results in the following condition  
Olmin  
V =(V /(R +R ))R <V  
OUT PU L PU L Olmin.  
2) no misdetection when load is disconnected: in this  
case the V has to be higher than V ; this  
-V  
/I  
R  
(V  
-V -V  
) / I  
CCpeak latchup  
prot  
OHµC IH GND IHmax  
OUT  
OLmax  
Calculation example:  
results in the following condition R <(V  
V
)/  
PU  
PU– OLmax  
For V  
= - 100V and I  
20mA; V 4.5V  
OHµC  
CCpeak  
latchup  
I
.
L(off2)  
5kΩ ≤ R  
65k.  
prot  
Because I  
may significantly increase if V  
is  
s(OFF)  
out  
Recommended R  
value is 10kΩ.  
prot  
pulled high (up to several mA), the pull-up resistor R  
PU  
should be connected to a supply that is switched OFF  
when the module is in standby.  
OPEN LOAD DETECTION IN OFF STATE  
Off state open load detection requires an external pull-up  
The values of V  
, V  
and I  
are available in  
L(off2)  
OLmin  
OLmax  
resistor (R ) connected between OUTPUT pin and a  
PU  
the Electrical Characteristics section.  
positive supply voltage (V ) like the +5V line used to  
PU  
Figure 8. Open Load detection in off state  
V batt.  
VPU  
VCC  
RPU  
DRIVER  
+
IL(off2)  
INPUT  
LOGIC  
OUT  
+
-
R
STATUS  
VOL  
RL  
GROUND  
10/20  
VND830-E  
Figure 9. Off State Output Current  
Figure 12. High Level Input Current  
IL(off1) (uA)  
2.5  
Iih (uA)  
5
2.25  
4.5  
Off state  
Vcc=36V  
Vin=3.25V  
2
4
Vin=Vout=0V  
1.75  
3.5  
3
1.5  
1.25  
1
2.5  
2
0.75  
0.5  
0.25  
0
1.5  
1
0.5  
0
-50  
-25  
0
25  
50  
75  
100 125 150  
175  
175  
175  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
175  
175  
Tc (°C)  
Tc (°C)  
Figure 10. Input Clamp Voltage  
Figure 13. Status Leakage Current  
Vicl (V)  
8
Ilstat (uA)  
0.05  
7.8  
Iin=1mA  
7.6  
0.04  
7.4  
7.2  
7
Vstat=5V  
0.03  
6.8  
6.6  
6.4  
6.2  
6
0.02  
0.01  
0
-50  
-25  
0
25  
50  
75  
100  
125  
150  
-50  
-25  
0
25  
50  
75  
100 125 150  
Tc (°C)  
Tc (°C)  
Figure 11. Status Low Output Voltage  
Figure 14. Status Clamp Voltage  
Vstat (V)  
0.8  
Vscl (V)  
8
7.8  
0.7  
Istat=1mA  
Istat=1.6mA  
7.6  
0.6  
7.4  
7.2  
7
0.5  
0.4  
0.3  
0.2  
0.1  
0
6.8  
6.6  
6.4  
6.2  
6
-50  
-25  
0
25  
50  
75  
100  
125  
150  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
Tc (°C)  
Tc (°C)  
11/20  
VND830-E  
Figure 15. Overvoltage Shutdown  
Figure 18. I Vs T  
LIM case  
Vov (V)  
50  
Ilim (A)  
20  
48  
46  
44  
42  
40  
38  
36  
34  
32  
30  
18  
16  
14  
12  
10  
8
Vcc=13V  
6
4
2
0
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
175  
175  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
175  
40  
Tc (°C)  
Tc (°C)  
Figure 16. Turn-on Voltage Slope  
Figure 19. Turn-off Voltage Slope  
dVout/dt(on) (V/ms)  
800  
dVout/dt(off) (V/ms)  
600  
700  
550  
Vcc=13V  
Vcc=13V  
Rl=6.5Ohm  
Rl=6.5Ohm  
600  
500  
500  
400  
300  
200  
100  
0
450  
400  
350  
300  
250  
200  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
Tc (ºC)  
Tc (ºC)  
Figure 17. On State Resistance Vs T  
Figure 20. On State Resistance Vs V  
case  
CC  
Ron (mOhm)  
160  
Ron (mOhm)  
120  
Tc=150°C  
110  
140  
Iout=2A  
100  
90  
Vcc=8V; 13V & 36V  
120  
80  
100  
80  
60  
40  
20  
0
70  
60  
Tc=25°C  
50  
40  
Tc= - 40°C  
30  
20  
Iout=5A  
10  
0
-50  
-25  
0
25  
50  
75  
100 125  
150  
5
10  
15  
20  
25  
30  
35  
Tc (°C)  
Vcc (V)  
12/20  
VND830-E  
Figure 21. Input High Level  
Figure 24. Input Low Level  
Vih (V)  
3.6  
Vil (V)  
2.6  
3.4  
3.2  
3
2.4  
2.2  
2
2.8  
2.6  
2.4  
2.2  
2
1.8  
1.6  
1.4  
1.2  
1
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
Tc (°C)  
Tc (°C)  
Figure 22. Openload On State Detection  
Threshold  
Figure 25. Openload Off State Detection  
Threshold  
Vol (V)  
5
Iol (mA)  
150  
4.5  
140  
Vin=0V  
4
Vcc=13V  
Vin=5V  
130  
3.5  
3
120  
2.5  
2
110  
100  
90  
1.5  
1
80  
0.5  
0
70  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
-50  
-25  
0
25  
50  
75  
100 125 150 175  
Tc (° C)  
Tc (°C)  
Figure 23. Input Hysteresis Voltage  
Vhyst (V)  
1.5  
1.4  
1.3  
1.2  
1.1  
1
0.9  
0.8  
0.7  
0.6  
0.5  
-50  
-25  
0
25  
50  
75  
100  
125  
150  
175  
Tc (°C)  
13/20  
VND830-E  
Figure 26. SO-16L Maximum turn off current versus load inductance  
LMAX (A)  
I
100  
10  
1
A
B
C
0.1  
1
10  
100  
L(mH)  
A = Single Pulse at T  
=150ºC  
Values are generated with R =0Ω  
L
Jstart  
B= Repetitive pulse at T  
=100ºC  
Jstart  
In case of repetitive pulses, T  
(at beginning of  
jstart  
each demagnetization) of every pulse must not  
exceed the temperature specified above for  
curves B and C.  
C= Repetitive Pulse at T  
=125ºC  
Jstart  
Conditions:  
V
=13.5V  
CC  
V , I  
IN  
L
Demagnetization  
Demagnetization  
Demagnetization  
t
14/20  
VND830-E  
SO-16L Thermal Data  
Figure 27. SO-16L PC Board  
Layout condition of R and Z measurements (PCB FR4 area= 41mm x 48mm, PCB thickness=2mm,  
th  
th  
2
2
Cu thickness=35µm, Copper areas: 0.5cm , 6cm ).  
Figure 28. R  
Vs PCB copper area in open box free air condition  
thj-amb  
RTH j-amb (°C/W)  
70  
65  
60  
55  
50  
45  
40  
0
1
2
3
4
5
6
7
PCB Cu heatsink area (cm^2)  
15/20  
VND830-E  
Figure 29. SO-16L Thermal Impedance Junction Ambient Single Pulse  
ZTH (°C/W)  
1000  
100  
10  
Footprint  
2
6 cm  
1
0.1  
0.01  
0.0001 0.001  
0.01  
0.1  
1
10  
100  
1000  
Time (s)  
Figure 30. Thermal fitting model of a double  
channel HSD in SO-16L  
Pulse calculation formula  
ZTHδ = RTH ⋅ δ + ZTHtp(1 – δ)  
δ = tp T  
where  
Table 14. Thermal Parameter  
2
Area/island (cm )  
Footprint  
6
22  
5
Tj_1  
C1  
R1  
C1  
R1  
C2  
R2  
C3  
R3  
C4  
R4  
C5  
R5  
C6  
R6  
R1 (°C/W)  
0.05  
0.3  
R2 (°C/W)  
Pd1  
R3 ( °C/W)  
R4 (°C/W)  
2.2  
C2  
Tj_2  
12  
R2  
R5 (°C/W)  
15  
Pd2  
R6 (°C/W)  
37  
C1 (W.s/°C)  
C2 (W.s/°C)  
C3 (W.s/°C)  
C4 (W.s/°C)  
C5 (W.s/°C)  
C6 (W.s/°C)  
0.001  
5.00E-03  
0.02  
0.3  
T_amb  
1
3
16/20  
VND830-E  
PACKAGE MECHANICAL  
Table 15. SO-16L Mechanical Data  
Symbol  
millimeters  
Typ  
Min  
Max  
A
a1  
a2  
b
b1  
C
2.65  
0.2  
2.45  
0.49  
0.32  
0.1  
0.35  
0.23  
0.5  
c1  
D
E
45° (typ.)  
10.1  
10.0  
10.5  
10.65  
e
e3  
F
1.27  
8.89  
7.4  
0.5  
7.6  
L
1.27  
0.75  
M
S
8° (max.)  
Figure 31. SO-16L Package Dimensions  
17/20  
VND830-E  
Figure 32. SO-16L Tube Shipment (No Suffix)  
Base Q.ty  
50  
1000  
532  
3.5  
Bulk Q.ty  
Tube length (± 0.5)  
C
B
A
B
13.8  
0.6  
C (± 0.1)  
All dimensions are in mm.  
A
Figure 33. Tape And Reel Shipment (Suffix “TR”)  
REEL DIMENSIONS  
Base Q.ty  
Bulk Q.ty  
A (max)  
B (min)  
C (± 0.2)  
F
1000  
1000  
330  
1.5  
13  
20.2  
16.4  
60  
G (+ 2 / -0)  
N (min)  
T (max)  
22.4  
TAPE DIMENSIONS  
According to Electronic Industries Association  
(EIA) Standard 481 rev. A, Feb 1986  
Tape width  
W
16  
4
Tape Hole Spacing  
Component Spacing  
Hole Diameter  
P0 (± 0.1)  
P
12  
1.5  
1.5  
7.5  
6.5  
2
D (± 0.1/-0)  
D1 (min)  
F (± 0.05)  
K (max)  
P1 (± 0.1)  
Hole Diameter  
Hole Position  
Compartment Depth  
Hole Spacing  
End  
r
Start  
Top  
No components  
500mm min  
Components  
No components  
500mm min  
cover  
tape  
Empty components pockets  
saled with cover tape.  
User direction of feed  
18/20  
VND830-E  
REVISION HISTORY  
Date  
Revision  
Description of Changes  
value correction: 60minstead of 35mΩ.  
- Iol curve changed.  
Nov. 2004  
Feb. 2005  
2
3
- R  
DS(on)  
19/20  
VND830-E  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted  
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject  
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not  
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics.  
All other names are the property of their respective owners  
© 2005 STMicroelectronics - All rights reserved  
STMicroelectronics group of companies  
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -  
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America  
www.st.com  
20/20  

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