VND830ASP-E [STMICROELECTRONICS]
DOUBLE CHANNEL HIGH SIDE DRIVER;
| 型号： | VND830ASP-E |
| 厂家： | 
ST |
| 描述： | DOUBLE CHANNEL HIGH SIDE DRIVER 驱动 |
| 文件： | 总27页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND830ASP-E
Double channel high-side solid state relay
Features
Type
RDS(on)
IOUT
VCC
10
VND830ASP-E
1. Per channel
60 mΩ
6 A(1)
36 V(1)
1
PowerSO-10
®
■ ECOPACK : lead free and RoHS compliant
■ Automotive Grade: compliance with AEC
Description
guidelines
■ Very low standby current
■ CMOS compatible input
■ Proportional load current sense
■ Current sense disable
The VND830ASP-E is a monolithic device made
using STMicroelectronics™ VIPower™ M0-3
technology. It is intended for driving any kind of
load with one side connected to ground. Active
V
pin voltage clamp protects the device against
CC
low energy spikes (see ISO7637 transient
compatibility table).
■ Thermal shutdown protection and diagnosis
■ Undervoltage shutdown
■ Overvoltage clamp
This device has two channels in high-side
configuration; each channel has an analog sense
output on which the sensing current is
proportional (according to a known ratio) to the
corresponding load current.
■ Load current limitation
Built-in thermal shutdown and outputs current
limitation protect the chip from overtemperature
and short circuit. Device turns-off in case of
ground pin disconnections.
Table 1.
Device summary
Package
Order codes
Tape and reel
Tube
Power-SO-10™
VND830ASP-E
VND830ASPTR-E
September 2013
Doc ID 17605 Rev 2
1/27
www.st.com
1
Contents
VND830ASP-E
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
2.2
2.3
2.4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 17
3.1.1
3.1.2
Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 17
Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 18
3.2
3.3
3.4
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PowerSO-10 maximum demagnetization energy (VCC = 13.5 V) . . . . . . . 19
4
5
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1
PowerSO-10 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
5.2
5.3
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PowerSO-10 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27
Doc ID 17605 Rev 2
VND830ASP-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Switching (V = 13 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CC
Logic input (channel 1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
V
- output diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Truth table (per each channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical transient requirements on V pin (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CC
Electrical transient requirements on V pin (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CC
Electrical transient requirements on V pin (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CC
Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Doc ID 17605 Rev 2
3/27
List of figures
VND830ASP-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Switching characteristics (resistive load R = 6.5 Ω). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
L
I
/I
versus I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
OUT SENSE
OUT
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14.
I
vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LIM
case
Figure 15. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. On-state resistance vs T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
case
Figure 18. On-state resistance vs V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CC
Figure 19. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
(1)
Figure 20. Maximum turn- off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
(1)
Figure 21. PowerSO-10 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22. Rthj-amb vs PCB copper area in open box free air condition. . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23. PowerSO-10 thermal impedance junction ambient single pulse. . . . . . . . . . . . . . . . . . . . . 21
Figure 24. Thermal fitting model of a double channel HSD in PowerSO-10 . . . . . . . . . . . . . . . . . . . . 21
Figure 25. PowerSO-10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 26. PowerSO-10 suggested pad layout and tube shipment (no suffix). . . . . . . . . . . . . . . . . . . 25
Figure 27. Tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4/27
Doc ID 17605 Rev 2
VND830ASP-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block diagram
VCC
OVERVOLTAGE
UNDERVOLTAGE
V
CLAMP
CC
PwCLAMP 1
DRIVER 1
OUTPUT 1
ILIM1
INPUT 1
Vdslim1
Ot1
LOGIC
IOUT1
CURRENT
SENSE 1
K
INPUT 2
GND
PwCLAMP 2
DRIVER 2
OUTPUT 2
Ot1
Ot2
ILIM2
OVERTEMP. 1
OVERTEMP. 2
Vdslim2
Ot2
IOUT2
CURRENT
SENSE 2
K
Figure 2.
Configuration diagram (top view)
5
4
3
OUTPUT 2
OUTPUT 2
N.C.
6
7
GROUND
INPUT 2
INPUT 1
C.SENSE1
C.SENSE2
8
9
OUTPUT 1
OUTPUT 1
2
1
10
11
VCC
PowerSO-10
Doc ID 17605 Rev 2
5/27
Electrical specifications
VND830ASP-E
2
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VCC
VCC
IOUT1
IIN1
OUTPUT1
CURRENT SENSE 1
OUTPUT2
INPUT1
VOUT1
ISENSE1
VIN1
VSENSE1
IOUT2
IIN2
VIN2
VOUT2
INPUT2
ISENSE2
CURRENT SENSE 2
GROUND
VSENSE2
IGND
2.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 2 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics sure program and other relevant quality
document.
Table 2.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VCC
-VCC
- IGND
IOUT
IR
DC supply voltage
41
V
V
Reverse supply voltage
DC reverse ground pin current
Output current
-0.3
-200
mA
A
Internally limited
-6
Reverse output current
Input current
A
IIN
+/- 10
mA
-3
V
V
VCSENSE Current sense maximum voltage
+15
6/27
Doc ID 17605 Rev 2
VND830ASP-E
Electrical specifications
Table 2.
Absolute maximum ratings (continued)
Parameter
Symbol
Value
Unit
Electrostatic discharge (Human Body Model:
R = 1.5 Ω; C = 100 pF)
– INPUT
4000
2000
5000
5000
V
V
V
V
VESD
– CURRENT SENSE
– OUTPUT
– VCC
Maximum switching energy
EMAX
100
mJ
(L = 1.8 mH; RL = 0 Ω; Vbat= 13.5 V;
Tjstart = 150 °C; IL = 9 A)
Ptot
Tj
Power dissipation at Tc = 25 °C
Junction operating temperature
Case operating temperature
Storage temperature
74
W
°C
°C
°C
Internally limited
-40 to 150
Tc
TSTG
-55 to 150
2.2
Thermal data
Table 3.
Symbol
Thermal data
Parameter
Value
Unit
Rthj-case
Rthj-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
1.3
°C/W
°C/W
51.2(1)
1. When mounted on a standard single sided FR-4 board with 0.5 cm2 of Cu (at least 35 µm thick). Horizontal
mounting and no artificial air flow.
Doc ID 17605 Rev 2
7/27
Electrical specifications
VND830ASP-E
2.3
Electrical characteristics
Values specified in this section are for 8 V < V < 36 V; -40 °C < Tj < 150 °C, unless
CC
otherwise specified. (Per each channel).
Table 4.
Symbol
Power
Parameter
Operating supply voltage
Test conditions
Min. Typ.
Max. Unit
VCC
5.5
3
13
4
36
V
V
VUSD Undervoltage shutdown
5.5
VOV
Overvoltage shutdown
36
V
I
OUT = 2 A; Tj = 25 °C
60
120
55
mΩ
mΩ
V
RON
On-state resistance
IOUT = 2 A; Tj = 150 °C
ICC = 20 mA(1)
Vclamp Clamp voltage
41
48
12
Off-state; VCC = 13 V;
VIN = VOUT = 0 V
40
25
7
µA
µA
Off-state; VCC=13V;
VIN = VOUT = 0 V; Tj = 25 °C
IS
Supply current
12
On-state; VIN = 5 V; VCC = 13 V;
IOUT = 0 A; RSENSE = 3.9 kΩ
mA
VIN = VOUT = 0 V; VCC = 36 V;
Tj = 125 °C
IL(off1) Off-state output current
IL(off2) Off-state output current
IL(off3) Off-state output current
0
50
0
µA
µA
µA
VIN = 0 V; VOUT = 3.5 V
-75
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125 °C
5
V
IN = VOUT = 0 V; VCC = 13 V;
IL(off4) Off-state output current
3
µA
Tj = 25 °C
1. Vclamp and VOV are correlated. Typical difference is 5 V.
Table 5.
Symbol
Switching (V = 13 V)
CC
Parameter
Test conditions
Min
Typ
Max Unit
RL = 6.5 Ω from VIN rising edge
td(on)
td(off)
Turn-on delay time
Turn-on delay time
-
30
30
-
-
-
-
µs
µs
to VOUT = 1.3 V
RL = 6.5 Ω from VIN falling
edge to VOUT = 11.7 V
-
-
-
RL = 6.5 Ω from VOUT = 1.3 V
to VOUT = 10.4 V
See
Figure 15
(dVOUT/dt)on Turn-on voltage slope
(dVOUT/dt)off Turn-off voltage slope
V/µs
V/µs
RL = 6.5 Ω from VOUT = 11.7 V
to VOUT = 1.3 V
See
Figure 16
8/27
Doc ID 17605 Rev 2
VND830ASP-E
Electrical specifications
Table 6.
Logic input (channel 1, 2)
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
VIL
IIL
Input low level voltage
Low level input current
Input high level voltage
High level input current
1.25
V
µA
V
VIN = 1.25 V
VIN = 3.25 V
1
VIH
IIH
3.25
10
8
µA
V
VI(hyst) Input hysteresis voltage
0.5
6
I
I
IN = 1 mA
IN = -1 mA
6.8
V
VICL
Input clamp voltage
-0.7
V
Table 7.
Symbol
V
- output diode
CC
Parameter
Test conditions
Min
Typ
Max Unit
0.6
VF
Forward on voltage -IOUT = 2 A; Tj = 150 °C
-
-
V
Table 8.
Symbol
Protection
Parameter
Test conditions
CC = 13 V
Min.
Typ.
Max. Unit
V
6
9
15
15
A
A
Ilim
DC short circuit current
5.5 V < VCC <36 V
Thermal shutdown
temperature
TTSD
TR
150
175
200
°C
Thermal reset temperature
135
7
°C
°C
THYST Thermal hysteresis
15
Turn-off output voltage
IOUT = 2 A; VIN = 0 V;
L = 6 mH
Vdemag
clamp
VCC-41 VCC-48 VCC-55
V
Output voltage drop
limitation
VON
IOUT = 10 mA
50
mV
Doc ID 17605 Rev 2
9/27
Electrical specifications
VND830ASP-E
(1)
Table 9.
Symbol
Current sense
Parameter
Test conditions
Min
Typ
Max
Unit
IOUT1 or IOUT2 = 0.05 A;
K0
K1
IOUT SENSE
/I
VSENSE = 0.5 V; other channels
open; Tj = -40 °C...150 °C
600
1300
2000
IOUT1 or IOUT2 = 0.25 A;
VSENSE = 0.5 V; other channels
open; Tj = -40 °C...150 °C
IOUT SENSE
/I
1000
-10
1400
1900
+10
IOUT1 or IOUT2 = 0.25 A;
VSENSE = 0.5 V; other channels
open; Tj = -40 °C...150 °C
dK1/K1
Current sense ratio drift
%
%
%
IOUT1 or IOUT2 = 1.6 A; VSENSE = 4 V;
other channels open; Tj = -40 °C
K2
IOUT SENSE
/I
1280
1300
1500
1500
1800
1780
Tj = 25 °C...150 °C
I
OUT1 or IOUT2 = 1.6 A; VSENSE = 4 V;
dK2/K2
Current sense ratio drift
other channels open;
Tj = -40 °C...150 °C
-6
+6
IOUT1 or IOUT2 = 2.5 A; VSENSE = 4 V;
other channels open; Tj = -40 °C
K3
IOUT SENSE
/I
1280
1340
1500
1500
1680
1600
Tj = 25 °C...150 °C
I
OUT1 or IOUT2 = 2.5 A; VSENSE = 4 V;
dK3/K3
Current sense ratio drift
other channels open;
Tj = -40 °C...150 °C
-6
+6
VIN = 0 V; IOUT = 0 A; VSENSE = 0 V;
Tj = -40 °C...150 °C
0
0
2
4
5
µA
µA
V
Analog sense leakage
current
ISENSE
VIN = 5 V; IOUT = 0 A; VSENSE = 0 V;
Tj = -40 °C...150 °C
10
VCC = 5.5 V; IOUT1,2 = 1.3 A;
RSENSE = 10 kΩ
Max analog sense output
voltage
VSENSE
VCC > 8 V, IOUT1,2 = 2.5 A;
RSENSE = 10 kΩ
V
Sense voltage in
overtemperature condition
VSENSEH
VCC = 13 V; RSENSE = 3.9 kΩ
5.5
V
Analog sense output
RVSENSEH impedance in
overtemperature condition
VCC = 13 V; Tj > TTSD
All channels open
;
400
Ω
Current sense delay
response
(2)
tDSENSE
to 90% ISENSE
500
µs
1. 9 V ≤ VCC ≤ 16 V (see Figure 4)
2. Current sense signal delay after positive input slope.
Sense pin doesn’t have to be left floating.
10/27
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VND830ASP-E
Electrical specifications
Figure 4.
Switching characteristics (resistive load R = 6.5 Ω)
L
VOUT
90%
80%
tr
dVOUT/dt(off)
dVOUT/dt(on)
10%
tf
t
ISENSE
90%
t
t
DSENSE
INPUT
td(on)
td(off)
t
Figure 5.
I
/I
versus I
OUT SENSE
OUT
Iout/Isense
2250
2000
1750
1500
1250
1000
750
A
B
C
D
E
500
0.0
0.5
1.0
1.5
Iout [A]
2.0
2.5
3.0
: Max, Tj = -40 °C to 150 °C
A
: Max, Tj = 25 °C to 150 °C
B
: Typical, Tj = -40 °C to 150 °C
C
: Min, Tj = 25 °C to 150 °C
D
: Min, Tj = -40 °C to 150 °C
E
Doc ID 17605 Rev 2
11/27
Electrical specifications
VND830ASP-E
Sense
Table 10. Truth table (per each channel)
Conditions
Input
Output
L
L
0
Normal operation
Overtemperature
Undervoltage
H
H
Nominal
L
L
L
0
H
VSENSEH
L
L
L
0
0
H
L
L
L
0
0
Overvoltage
H
L
H
H
L
L
L
0
Short circuit to GND
(Tj<TTSD
)
)
0
(Tj>TTSD
VSENSEH
L
H
H
0
Short circuit to VCC
H
< Nominal
Negative output voltage
clamp
L
L
0
12/27
Doc ID 17605 Rev 2
VND830ASP-E
Electrical specifications
Table 11.
Electrical transient requirements on V pin (part 1)
CC
Test levels
ISO T/R 7637/1
test pulse
Delays and
impedance
I
II
III
IV
1
2
-25 V
+25 V
-25 V
-50 V
+50 V
-50 V
-75 V
+75 V
-100 V
+75 V
-6 V
-100 V
+100 V
-150 V
+100 V
-7 V
2 ms, 10 Ω
0.2 ms, 10 Ω
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
3a
3b
4
+25 V
-4 V
+50 V
-5 V
5
+26.5 V
+46.5 V
+66.5 V
+86.5 V
Table 12. Electrical transient requirements on V pin (part 2)
CC
Test levels results
ISO T/R 7637/1
Test pulse
I
II
III
IV
1
2
C
C
C
C
C
C
C
C
C
C
C
E
C
C
C
C
C
E
C
C
C
C
C
E
3a
3b
4
5
Table 13. Electrical transient requirements on V pin (part 3)
CC
Class
Contents
All functions of the device are performed as designed after exposure to
disturbance.
C
One or more functions of the device is not performed as designed after exposure
to disturbance and cannot be returned to proper operation without replacing the
device.
E
Doc ID 17605 Rev 2
13/27
Electrical specifications
Figure 6.
VND830ASP-E
Waveforms
NORMAL OPERATION
INPUT
n
LOAD CURRENT
n
SENSE
n
UNDERVOLTAGE
V
CC
V
USDhyst
V
USD
INPUT
n
LOAD CURRENT
n
SENSE
n
OVERVOLTAGE
V
OV
V
CC
V
CC > VOV
VCC < VOV
INPUT
n
LOAD CURRENT
n
SENSE
n
SHORT TO GROUND
INPUT
n
LOAD CURRENT
n
LOAD VOLTAGE
n
SENSE
n
SHORT TO V
CC
INPUT
n
LOAD VOLTAGE
n
LOAD CURRENT
n
SENSE
n
<Nominal
<Nominal
OVERTEMPERATURE
T
TSD
T
j
T
R
INPUT
n
LOAD CURRENT
n
V
R
SENSEH
SENSE
n
I
=
SENSE
SENSE
14/27
Doc ID 17605 Rev 2
VND830ASP-E
Electrical specifications
2.4
Electrical characteristics curves
Figure 7.
Off-state output current
Figure 8.
High level input current
Iih (uA)
IL(off1) (uA)
5
4.5
4
8
7
6
5
4
3
2
Vin=3.25V
Off state
Vcc=13V
Vin=Vout=0V
3.5
3
2.5
2
1.5
1
1
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (ºC)
Figure 9.
Input clamp voltage
Figure 10. Input high level
Vih (V)
3.6
Vicl (V)
8
7.8
7.6
7.4
7.2
7
3.4
Iin=1mA
Vcc=13V
3.2
3
2.8
2.6
2.4
2.2
2
6.8
6.6
6.4
6.2
6
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (ºC)
Figure 11. Input low level
Figure 12. Input hysteresis voltage
Vil (V)
2.6
Vhyst (V)
1.5
1.4
2.4
Vcc=13V
Vcc=13V
1.3
2.2
1.2
1.1
1
2
1.8
1.6
1.4
1.2
1
0.9
0.8
0.7
0.6
0.5
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (ºC)
Doc ID 17605 Rev 2
15/27
Electrical specifications
VND830ASP-E
Figure 13. Overvoltage shutdown
Figure 14. I
vs T
LIM case
Vov (V)
50
Ilim (A)
20
47.5
45
17.5
15
Vcc=13V
42.5
40
12.5
10
37.5
35
7.5
5
32.5
30
2.5
0
-50
-25
0
25
50
75
100 125 150
175
-50
-25
0
25
50
75
100 125 150
175
Tc (ºC)
Tc (ºC)
Figure 15. Turn-on voltage slope
Figure 16. Turn-off voltage slope
dVout/dt(off) (V/ms)
500
dVout/dt(on) (V/ms)
600
450
550
Vcc=13V
Rl=6.5Ohm
Vcc=13V
Rl=6.5Ohm
400
500
350
450
400
350
300
250
200
300
250
200
150
100
50
0
-50
-25
0
25
50
75
100 125
150
175
-50
-25
0
25
50
75
100 125
150
175
Tc (ºC)
Tc (ºC)
Figure 17. On-state resistance vs T
Figure 18. On-state resistance vs V
case
CC
Ron (mOhm)
100
Ron (mOhm)
100
90
Tc=150ºC
90
80
70
60
50
40
30
20
Iout=5A
Vcc=8V & 36V
80
70
Iout=5A
60
50
40
30
20
10
0
Tc=25ºC
Tc= -40ºC
-50
-25
0
25
50
75
100 125
150
175
5
10
15
20
25
30
35
40
Tc (ºC)
Vcc (V)
16/27
Doc ID 17605 Rev 2
VND830ASP-E
Application information
3
Application information
Figure 19. Application schematic
+5V
Rprot
INPUT1
V
CC
Dld
OUTPUT1
Rprot
CURRENT SENSE1
INPUT2
μC
Rprot
Rprot
CURRENT SENSE2
GND
OUTPUT2
RGND
RSENSE1
VGND
RSENSE2
DGND
3.1
GND protection network against reverse battery
3.1.1
Solution 1: resistor in the ground line (R
only)
GND
This can be used with any type of load.
The following is an indication on how to dimension the R
resistor.
GND
1.
2.
R
R
≤ 600 mV / I
GND
GND
S(on)max
≥ (-V ) / (-I
)
CC
GND
where -I
is the DC reverse ground pin current and can be found in the absolute
GND
maximum rating section of the device’s datasheet.
Power dissipation in R
(when V < 0: during reverse battery situations) is:
CC
GND
2
P = (-V ) / R
D
CC
GND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
becomes the sum of the
S(on)max
Please note that if the microprocessor ground is not shared by the device ground then the
produces a shift (I * R ) in the input thresholds and the status output
R
GND
S(on)max
GND
values. This shift varies depending on how many devices are ON in the case of several
high-side drivers sharing the same R
.
GND
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize solution 2 (see Section 3.1.2).
Doc ID 17605 Rev 2
17/27
Application information
VND830ASP-E
3.1.2
Solution 2: diode (D
) in the ground line
GND
A resistor (R
inductive load.
= 1 kΩ) should be inserted in parallel to D if the device drives an
GND
GND
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (∼600 mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
Series resistor in INPUT and STATUS lines are also required to prevent that, during battery
voltage transient, the current exceeds the absolute maximum rating.
Safest configuration for unused INPUT and STATUS pin is to leave them unconnected, while
unused SENSE pin has to be connected to ground pin.
3.2
3.3
Load dump protection
D is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
ld
V
max DC rating. The same applies if the device is subject to transients on the V line
CC
CC
that are greater than the ones shown in Table 11.
MCU I/Os protection
If a ground protection network is used and negative transient are present on the V line,
CC
the control pins are pulled negative. ST suggests to insert a resistor (R ) in line to prevent
prot
the microcontroller I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
-V
/I
≤ R
≤ (V
-V -V
) / I
µ
CCpeak latchup
prot
OH C IH GND IHmax
Calculation example:
For V
= -100 V and I
≥ 20 mA; V
≥ 4.5 V
µ
CCpeak
latchup
OH C
5 kΩ ≤ R
≤ 65 kΩ.
prot
Recommended values:
=10 kΩ.
R
prot
18/27
Doc ID 17605 Rev 2
VND830ASP-E
Application information
3.4
PowerSO-10 maximum demagnetization energy
(VCC = 13.5 V)
(1)
Figure 20. Maximum turn- off current versus load inductance
A: Single pulse at Tjstart = 150 °C
B: Repetitive pulse at Tjstart = 100 °C
C: Repetitive pulse at Tjstart = 125 °C
Condition:
VCC = 13.5 V
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
1. Values are generated with RL = 0 Ω
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed
the temperature specified above for curves B and C.
Doc ID 17605 Rev 2
19/27
Package and PCB thermal data
VND830ASP-E
4
Package and PCB thermal data
4.1
PowerSO-10 thermal data
(1)
Figure 21. PowerSO-10 PC board
1. Layout condition of Rth and Zth measurements (PCB FR4 area= 58 mm x 58 mm, PCB thickness=2 mm,
Cu thickness = 35 µm, Copper areas: from minimum pad lay-out to 8 cm2).
Figure 22. R
vs PCB copper area in open box free air condition
thj-amb
RTHj_amb (°C/W)
55
Tj-Tamb=50°C
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
20/27
Doc ID 17605 Rev 2
VND830ASP-E
Package and PCB thermal data
Figure 23. PowerSO-10 thermal impedance junction ambient single pulse
Equation 1: pulse calculation formula
ZTHδ = RTH ⋅ δ + ZTHtp(1 – δ)
δ = tp ⁄ T
where
Figure 24. Thermal fitting model of a double channel HSD in PowerSO-10
Tj_1
C1
R1
C1
R1
C2
R2
C3
R3
C4
R4
C5
R5
C6
R6
Pd1
C2
Tj_2
R2
Pd2
T_amb
Doc ID 17605 Rev 2
21/27
Package and PCB thermal data
VND830ASP-E
Table 14. Thermal parameter
Area/island (cm2)
0.5
6
R1 (°C/ W)
R2 (°C/ W)
R3 (°C/ W)
R4 (°C/ W)
R5 (°C/ W)
R6 (°C/ W)
C1 (W.s/ °C)
C2 (W.s /°C)
C3 (W.s/ °C)
C4 (W.s/ °C)
C5 (W.s/ °C)
C6 (W.s/ °C)
0.15
0.8
0.7
0.8
12
37
22
0.0006
2.10E-03
0.013
0.3
0.75
3
5
22/27
Doc ID 17605 Rev 2
VND830ASP-E
Package and packing information
5
Package and packing information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
5.2
PowerSO-10 mechanical data
Figure 25. PowerSO-10 package dimensions
B
0.10
E
A B
10
H
E
E2
E4
1
SEATING
PLANE
DETAIL "A"
e
B
A
C
0.25
D
=
=
=
=
h
D1
SEATING
PLANE
A
F
A1
L
A1
DETAIL "A"
α
Doc ID 17605 Rev 2
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Package and packing information
VND830ASP-E
Table 15. PowerSO-10 mechanical data
Millimeters
Typ.
Dim.
Min.
3.35
3.4
Max.
3.65
3.6
A
A(1)
A1
B
0
0.10
0.60
0.53
0.55
0.32
9.60
7.60
9.50
7.60
7.50
6.10
6.30
0.40
0.37
0.35
0.23
9.40
7.40
9.30
7.20
7.30
5.90
5.90
B(1)
C
C(1)
D
D1
E
E2
E2(1)
E4
E4(1)
e
1.27
F
1.25
1.20
1.35
1.40
F(1)
H
13.80
13.85
14.40
14.35
H(1)
h
0.50
L
1.20
0.80
0°
1.80
1.10
8°
L(1)
α
α(1)
2°
8°
1. Muar only POA P013P.
24/27
Doc ID 17605 Rev 2
VND830ASP-E
Package and packing information
5.3
PowerSO-10 packing information
Figure 26. PowerSO-10 suggested pad layout and tube shipment (no suffix)
14.6 - 14.9
B
10.8 - 11
6.30
C
A
0.67 - 0.73
0.54 - 0.6
1
2
3
10
9
8
9.5
All dimensions are in mm.
Base Q.ty Bulk Q.ty Tube length (± 0.5)
7
4
5
1.27
6
A
B
C (± 0.1)
0.8
Casablanca
Muar
50
50
1000
1000
532
532
10.4 16.4
4.9 17.2
0.8
Figure 27. Tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
600
600
330
1.5
13
20.2
24.4
60
G (+ 2 / -0)
N (min)
T (max)
30.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
24
4
Tape Hole Spacing
Component Spacing
Hole Diameter
P0 (± 0.1)
P
24
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
1.5
1.5
11.5
6.5
2
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
All dimensions are in mm.
End
Start
Top
No components
500mm min
Components
No components
cover
tape
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
Doc ID 17605 Rev 2
25/27
Revision history
VND830ASP-E
6
Revision history
Table 16. Document revision history
Date
Revision
Changes
19-Jul-2010
19-Sep-2013
1
2
Initial release.
Updated Disclaimer
26/27
Doc ID 17605 Rev 2
VND830ASP-E
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