VND810SP13TR [STMICROELECTRONICS]
DOUBLE CHANNEL HIGH SIDE DRIVER; 双通道高侧驱动器
| 型号： | VND810SP13TR |
| 厂家： | 
ST |
| 描述： | DOUBLE CHANNEL HIGH SIDE DRIVER |
| 文件： | 总18页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
VND810SP
DOUBLE CHANNEL HIGH SIDE DRIVER
TYPE
R
I
V
CC
DS(on)
OUT
VND810SP
160 mΩ (*)
3.5 A (*)
36 V
(*) Per each channel
■ CMOS COMPATIBLE INPUTS
■ OPEN DRAIN STATUS OUTPUTS
10
■ ON STATE OPEN LOAD DETECTION
■ OFF STATE OPEN LOAD DETECTION
■ SHORTED LOAD PROTECTION
1
PowerSO-10™
■ UNDERVOLTAGE AND OVERVOLTAGE
SHUTDOWN
■ PROTECTION AGAINST LOSS OF GROUND
■ VERY LOW STAND-BY CURRENT
ORDER CODES
TUBE
PACKAGE
T&R
PowerSO-10™ VND810SP VND810SP13TR
■ REVERSE BATTERY PROTECTION (**)
DESCRIPTION
combined with thermal shutdown and automatic
restart protects the device against overload. The
device detects open load condition both in on and
off state. Output shorted to VCC is detected in the
off state. Device automatically turns off in case of
ground pin disconnection.
The VND810SP is a monolithic device made by
using
STMicroelectronics
VIPower
M0-3
Technology, intended for driving any kind of load
with one side connected to ground.
Active VCC pin voltage clamp protects the device
against low energy spikes (see ISO7637 transient
compatibility table). Active current limitation
BLOCK DIAGRAM
V
cc
V
cc
OVERVOLTAGE
CLAMP
UNDERVOLTAGE
GND
CLAMP 1
OUTPUT1
INPUT1
STATUS1
DRIVER 1
CLAMP 2
CURRENT LIMITER 1
OPENLOAD ON 1
DRIVER 2
LOGIC
OUTPUT2
OVERTEMP. 1
CURRENT LIMITER 2
OPENLOAD ON 2
INPUT2
OPENLOAD OFF 1
STATUS2
OPENLOAD OFF 2
OVERTEMP. 2
(**) See application schematic at page 8
July 2002
1/18
1
VND810SP
ABSOLUTE MAXIMUM RATING
Symbol
Parameter
Value
Unit
V
V
DC Supply Voltage
41
- 0.3
CC
- V
Reverse DC Supply Voltage
V
CC
GND
OUT
- I
DC Reverse Ground Pin Current
- 200
mA
A
I
DC Output Current
Internally Limited
- 6
- I
Reverse DC Output Current
A
OUT
I
DC Input Current
+/- 10
mA
mA
IN
I
DC Status Current
+/- 10
stat
Electrostatic Discharge (Human Body Model: R=1.5KΩ; C=100pF)
- INPUT
4000
4000
5000
5000
V
V
V
V
V
- STATUS
- OUTPUT
ESD
MAX
- V
CC
Maximum Switching Energy
(L=1.4mH; R =0Ω; V =13.5V; T
E
24
mJ
=150ºC; I =5A)
L
bat
jstart
L
P
Power Dissipation T =25°C
52
W
°C
°C
°C
tot
C
T
Junction Operating Temperature
Case Operating Temperature
Storage Temperature
Internally Limited
- 40 to 150
j
T
c
T
- 55 to 150
stg
CONNECTION DIAGRAM (TOP VIEW)
5
4
3
2
1
OUTPUT 1
OUTPUT 1
N.C.
6
7
GROUND
INPUT 1
STATUS 1
STATUS 2
INPUT 2
8
OUTPUT 2
OUTPUT 2
9
10
11
VCC
CURRENT AND VOLTAGE CONVENTIONS
I
S
I
V
IN1
CC
V
CC
INPUT 1
I
I
STAT1
V
IN1
STATUS 1
INPUT 2
I
OUT1
V
IN2
STAT1
OUTPUT 1
OUTPUT 2
V
OUT1
I
V
I
STAT2
IN2
OUT2
STATUS 2
GND
V
OUT2
V
STAT2
I
GND
2/18
1
VND810SP
THERMAL DATA
Symbol
Parameter
Value
2.4
Unit
°C/W
°C/W
R
Thermal Resistance Junction-case
thj-case
R
Thermal Resistance Junction-ambient
52.4 (*)
thj-amb
2
(*) When mounted on a standard single-sided FR-4 board with 0.5cm of Cu (at least 35µm thick). Horizontal mounting and no artificial air
flow.
ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C< Tj < 150°C, unless otherwise specified)
(Per each channel)
POWER OUTPUTS
Symbol
(**)
Parameter
Test Conditions
Min
5.5
3
Typ
13
4
Max
36
Unit
V
V
Operating Supply Voltage
CC
V
(**) Undervoltage Shut-down
5.5
V
USD
V
(**)
Overvoltage Shut-down
36
V
OV
I
I
=1A; T=25°C
160
320
40
mΩ
mΩ
µA
OUT
OUT
j
R
On State Resistance
ON
=1A; V >8V
CC
12
Off State; V =13V; V =V
=0V
CC
IN
OUT
Off State; V =13V; V =V
Tj=25°C
=0V;
CC
IN
OUT
I (**)
Supply Current
S
12
5
25
7
µA
mA
µA
µA
µA
µA
On State; V =13V; V =5V; I =0A
OUT
CC
IN
I
Off State Output Current
Off State Output Current
Off State Output Current
Off State Output Current
V
V
V
V
=V =0V
OUT
0
50
0
L(off1)
IN
IN
IN
IN
I
=0V; V
=3.5V
-75
L(off2)
OUT
I
=V
=V
=0V; Vcc=13V; T =125°C
5
L(off3)
OUT
OUT
j
I
=0V; Vcc=13V; T =25°C
3
L(off4)
j
(**) Per device
SWITCHING (VCC=13V)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
R =13Ω from V rising edge to
L
IN
t
t
Turn-on Delay Time
Turn-off Delay Time
30
µs
d(on)
d(off)
V
=1.3V
OUT
R =13Ω from V falling edge to
L
IN
30
µs
V
=11.7V
OUT
See
relative
diagram
dV
dt
/
/
R =13Ω from V
=1.3V to
OUT
L
OUT
Turn-on Voltage Slope
Turn-off Voltage Slope
V/µs
V
=10.4V
(on)
OUT
See
relative
diagram
dV
dt
R =13Ω from V
=11.7V to
OUT
L
OUT
V/µs
V
=1.3V
(off)
OUT
LOGIC INPUT
Symbol
Parameter
Input Low Level
Test Conditions
Min
Typ
Max
Unit
V
V
1.25
IL
I
Low Level Input Current
Input High Level
V
V
= 1.25V
= 3.25V
1
µA
V
IL
IN
IN
V
3.25
IH
IH
I
High Level Input Current
Input Hysteresis Voltage
10
8
µA
V
V
0.5
6
hyst
I
I
= 1mA
6.8
V
IN
IN
V
Input Clamp Voltage
ICL
= -1mA
-0.7
V
3/18
1
VND810SP
ELECTRICAL CHARACTERISTICS (continued)
STATUS PIN
Symbol
Parameter
Test Conditions
= 1.6 mA
STAT
Min
Typ
Max
0.5
10
Unit
V
V
Status Low Output Voltage I
Status Leakage Current
STAT
I
Normal Operation; V
= 5V
µA
LSTAT
STAT
Status Pin Input
Capacitance
C
Normal Operation; V
= 5V
100
8
pF
STAT
STAT
I
= 1mA
6
6.8
V
V
STAT
V
Status Clamp Voltage
I
SCL
= - 1mA
-0.7
STAT
PROTECTIONS
Symbol
Parameter
Test Conditions
Min
150
135
7
Typ
Max
Unit
°C
T
Shut-down Temperature
Reset Temperature
Thermal Hysteresis
175
200
TSD
T
°C
R
T
15
5
°C
hyst
Status Delay in Overload
Conditions
Tj>TTSD
t
I
20
µs
sdl
lim
3.5
7.5
7.5
A
A
Current limitation
5.5V<V <36V
CC
Turn-off Output Clamp
Voltage
V
I
=1A; L=6mH
V
-41
V
-48
V
-55
V
demag
OUT
CC
CC
CC
OPENLOAD DETECTION
Symbol
Parameter
Openload ON State
Detection Threshold
Openload ON State
Detection Delay
Test Conditions
Min
Typ
Max
Unit
I
V
=5V
IN
20
40
80
mA
OL
t
I
=0A
OUT
200
µs
DOL(on)
Openload OFF State
Voltage Detection
Threshold
V
V
=0V
IN
1.5
2.5
3.5
V
OL
Openload Detection Delay
at Turn Off
t
1000
µs
DOL(off)
OPEN LOAD STATUS TIMING (with external pull-up)
< I
OVER TEMP STATUS TIMING
T > T
I
V
> V
OL
OUT
OL
OUT
j
TSD
V
INn
V
V
INn
V
STAT n
STAT n
t
t
SDL
SDL
t
t
DOL(off)
DOL(on)
4/18
2
1
VND810SP
Switching time Waveforms
V
OUTn
90%
80%
dV
/dt
OUT (off)
dV
/dt
OUT (on)
10%
t
V
INn
t
d(on)
t
d(off)
t
TRUTH TABLE
CONDITIONS
INPUT
OUTPUT
STATUS
L
H
L
H
H
H
Normal Operation
L
H
H
L
X
X
H
) H
) L
Current Limitation
(T < T
j
TSD
TSD
(T > T
j
L
H
L
L
H
L
Overtemperature
Undervoltage
Overvoltage
L
H
L
L
X
X
L
H
L
L
H
H
L
H
H
H
L
H
Output Voltage > V
OL
L
H
L
H
H
L
Output Current < I
OL
5/18
1
VND810SP
ELECTRICAL TRANSIENT REQUIREMENTS ON VCC PIN
TEST LEVELS
ISO T/R 7637/1
Test Pulse
I
II
III
IV
Delays and
Impedance
1
2
-25 V
+25 V
-25 V
-50 V
+50 V
-50 V
-75 V
+75 V
-100 V
+75 V
-6 V
-100 V
+100 V
-150 V
+100 V
-7 V
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
3a
3b
4
+25 V
-4 V
+50 V
-5 V
5
+26.5 V
+46.5 V
+66.5 V
+86.5 V
ISO T/R 7637/1
Test Pulse
TEST LEVELS RESULTS
I
II
III
C
C
C
C
C
E
IV
C
C
C
C
C
E
1
2
C
C
C
C
C
C
C
C
C
C
C
E
3a
3b
4
5
CLASS
CONTENTS
C
E
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure and cannot be
returned to proper operation without replacing the device.
6/18
1
1
VND810SP
Figure 1: Waveforms
NORMAL OPERATION
INPUT
n
OUTPUT VOLTAGE
n
STATUS
n
UNDERVOLTAGE
V
V
USDhyst
CC
V
USD
INPUT
n
OUTPUT VOLTAGE
n
STATUS
n
undefined
OVERVOLTAGE
V
>V
OV
V
<V
OV
CC
CC
V
CC
INPUT
n
OUTPUT VOLTAGE
n
STATUS
n
OPEN LOAD with external pull-up
INPUT
n
V
>V
OL
OUT
OUTPUT VOLTAGE
n
V
OL
STATUS
n
OPEN LOAD without external pull-up
INPUT
n
OUTPUT VOLTAGE
n
STATUS
n
OVERTEMPERATURE
T
TSD
T
j
T
R
INPUT
n
OUTPUT CURRENT
n
STATUS
n
7/18
1
VND810SP
APPLICATION SCHEMATIC
+5V +5V
+5V
V
CC
R
prot
STATUS1
D
ld
R
R
µC
prot
INPUT1
OUTPUT1
prot
STATUS2
R
prot
INPUT2
OUTPUT2
GND
R
GND
D
V
GND
GND
depending on how many devices are ON in the case of
several high side drivers sharing the same R
If the calculated power dissipation leads to a large resistor
or several devices have to share the same resistor then
the ST suggests to utilize Solution 2 (see below).
GND PROTECTION NETWORK AGAINST
REVERSE BATTERY
.
GND
Solution 1: Resistor in the ground line (R
can be used with any type of load.
only). This
GND
The following is an indication on how to dimension the
Solution 2: A diode (D
) in the ground line.
GND
R
resistor.
GND
1) R
A resistor (R
GND
=1kΩ) should be inserted in parallel to
GND
≤ 600mV / I
.
S(on)max
D
if the device will be driving an inductive load.
GND
2) R
≥ (−V ) / (-I
)
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
the ground network will produce a shift ( 600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
GND
CC
GND
where -I
is the DC reverse ground pin current and can
GND
be found in the absolute maximum rating section of the
device’s datasheet.
Power Dissipation in R
(when V <0: during reverse
CC
GND
battery situations) is:
2
P = (-V ) /R
D
CC
GND
LOAD DUMP PROTECTION
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
D
is necessary (Voltage Transient Suppressor) if the
ld
calculated with formula (1) where I
becomes the
load dump peak voltage exceeds V max DC rating. The
S(on)max
CC
sum of the maximum on-state currents of the different
devices.
same applies if the device will be subject to transients on
the V
line that are greater than the ones shown in the
CC
ISO T/R 7637/1 table.
Please note that if the microprocessor ground is not
common with the device ground then the R
will
GND
produce a shift (I
* R
) in the input thresholds
S(on)max
GND
and the status output values. This shift will vary
8/18
1
1
VND810SP
µC I/Os PROTECTION:
supply the microprocessor.
If a ground protection network is used and negative
The external resistor has to be selected according to the
following requirements:
1) no false open load indication when load is connected:
transient are present on the V line, the control pins will
CC
be pulled negative. ST suggests to insert a resistor (R
)
prot
in line to prevent the µC I/Os pins to latch-up.
in this case we have to avoid V
to be higher than
OUT
The value of these resistors is a compromise between
the leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up limit
of µC I/Os.
V
; this results in the following condition
Olmin
V
=(V /(R +R ))R <V
PU L PU L Olmin.
OUT
2) no misdetection when load is disconnected: in this
case the V has to be higher than V ; this
-V
/I
≤ R
≤ (V
-V -V
) / I
CCpeak latchup
prot
OHµC IH GND
IHmax
OUT
OLmax
Calculation example:
results in the following condition R <(V
V
)/
For V
= - 100V and I
≥ 20mA; V
≥ 4.5V
PU
PU– OLmax
CCpeak
latchup
OHµC
I
.
5kΩ ≤ R
≤ 65kΩ.
L(off2)
prot
Recommended R
value is 10kΩ.
Because I
may significantly increase if V is pulled
out
prot
s(OFF)
high (up to several mA), the pull-up resistor R
should
PU
OPEN LOAD DETECTION IN OFF STATE
Off state open load detection requires an external pull-up
be connected to a supply that is switched OFF when the
module is in standby.
resistor (R ) connected between OUTPUT pin and a
The values of V
, V
and I are available in
L(off2)
PU
OLmin
OLmax
the Electrical Characteristics section.
positive supply voltage (V ) like the +5V line used to
PU
Open Load detection in off state
PU
V batt.
V
VCC
PU
R
DRIVER
+
L(off2)
I
INPUT
LOGIC
OUT
+
-
R
STATUS
OL
V
L
R
GROUND
9/18
1
VND810SP
High Level Input Current
Off State Output Current
IL(off1) (uA)
Iih (uA)
1.6
5
1.44
4.5
Off state
Vin=3.25V
1.28
1.12
0.96
0.8
Vcc=36V
Vin=Vout=0V
4
3.5
3
2.5
2
0.64
0.48
0.32
0.16
0
1.5
1
0.5
0
-50
-25
0
25
50
75
100 125 150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (ºC)
Tc (°C)
Input Clamp Voltage
Status Leakage Current
Vicl (V)
Ilstat (uA)
8
0.05
7.8
Iin=1mA
7.6
0.04
7.4
7.2
7
Vstat=5V
0.03
6.8
6.6
6.4
6.2
6
0.02
0.01
0
-50
-25
0
25
50
75
100 125 150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Status Low Output Voltage
Status Clamp Voltage
Vscl (V)
Vstat (V)
8
0.8
7.8
0.7
Istat=1mA
Istat=1.6mA
7.6
0.6
7.4
7.2
7
0.5
0.4
0.3
0.2
0.1
0
6.8
6.6
6.4
6.2
6
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
10/18
1
VND810SP
On State Resistance Vs Tcase
On State Resistance Vs VCC
Ron (mOhm)
Ron (mOhm)
400
400
350
350
Iout=1A
Iout=1A
Vcc=8V; 13V & 36V
300
300
Tc= 125ºC
Tc= 25ºC
250
250
200
150
100
50
200
150
100
50
Tc= - 40ºC
0
0
-50
-25
0
25
50
75
100 125
150
175
5
10
15
20
25
30
35
40
Tc (ºC)
Vcc (V)
Openload On State Detection Threshold
Input High Level
Iol (mA)
Vih (V)
60
3.6
55
3.4
3.2
3
Vcc=13V
Vin=5V
50
45
40
35
30
25
20
15
10
2.8
2.6
2.4
2.2
2
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Input Low Level
Input Hysteresis Voltage
Vil (V)
Vhyst (V)
1.5
2.6
1.4
1.3
1.2
1.1
1
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.9
0.8
0.7
0.6
0.5
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
11/18
1
VND810SP
Overvoltage Shutdown
Openload Off State Voltage Detection Threshold
Vov (V)
Vol (V)
50
5
48
46
44
42
40
38
36
34
32
30
4.5
Vin=0V
4
3.5
3
2.5
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Turn-on Voltage Slope
Turn-off Voltage Slope
dVout/dt(off) (V/ms)
dVout/dt(on) (V/ms)
500
1000
450
900
Vcc=13V
Rl=13Ohm
Vcc=13V
Rl=13Ohm
400
800
350
700
300
250
200
150
100
50
600
500
400
300
200
100
0
0
-50
-25
0
25
50
75
100 125
150
175
-50
-25
0
25
50
75
100 125 150 175
Tc (ºC)
Tc (ºC)
ILIM Vs Tcase
Ilim (A)
10
9
8
7
6
5
4
3
2
1
0
Vcc=13V
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
12/18
1
VND810SP
Maximum turn off current versus load inductance
ILMAX (A)
10
A
B
C
1
0.01
0.1
1
10
100
L(mH)
A = Single Pulse at TJstart=150ºC
B= Repetitive pulse at TJstart=100ºC
C= Repetitive Pulse at TJstart=125ºC
Conditions:
VCC=13.5V
Values are generated with RL=0Ω
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed
the temperature specified above for curves B and C.
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
13/18
VND810SP
PowerSO-10™ THERMAL DATA
PowerSO-10™ PC Board
Layout condition of R and Z measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
th
th
2
Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8cm ).
Rthj-amb Vs PCB copper area in open box free air condition
RTHj_amb (°C/W)
55
Tj-Tamb=50°C
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
14/18
VND810SP
PowerSO-10 Thermal Impedance Junction Ambient Single Pulse
ZTH (°C/W)
1000
100
10
1
2
0.5 cm
2
6 cm
0.1
0.0001 0.001
0.01
0.1
1
10
100
1000
Time (s)
Thermal fitting model of a double channel HSD
in PowerSO-10
Pulse calculation formula
ZTHδ = RTH δ + ZTHtp(1 – δ)
δ = tp ⁄ T
where
Thermal Parameter
2
Area/island (cm )
R1 (°C/W)
0.5
0.35
1.8
6
Tj_1
C1
R1
C1
R1
C2
R2
C3
R3
C4
R4
C5
R5
C6
R6
R2 (°C/W)
R3( °C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
Pd1
1.1
C2
Tj_2
0.8
12
R2
37
22
Pd2
0.0001
T_amb
7.00E-04
0.008
0.3
0.75
3
5
15/18
VND810SP
PowerSO-10™ MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
MIN.
MAX.
A
A (*)
A1
B
B (*)
C
C (*)
D
D1
E
E2
E2 (*)
E4
E4 (*)
e
F
F (*)
H
3.35
3.4
3.65
3.6
0.132
0.134
0.000
0.016
0.014
0.013
0.009
0.370
0.291
0.366
0.283
0.287
0.232
0.232
0.144
0.142
0.004
0.024
0.021
0.022
0.0126
0.378
0.300
0.374
300
0.00
0.40
0.37
0.35
0.23
9.40
7.40
9.30
7.20
7.30
5.90
5.90
0.10
0.60
0.53
0.55
0.32
9.60
7.60
9.50
7.60
7.50
6.10
6.30
0.295
0.240
0.248
1.27
0.50
0.050
0.002
1.25
1.20
13.80
13.85
1.35
1.40
14.40
14.35
0.049
0.047
0.543
0.545
0.053
0.055
0.567
0.565
H (*)
h
L
L (*)
α
1.20
0.80
0º
1.80
1.10
8º
0.047
0.031
0º
0.070
0.043
8º
α (*)
2º
8º
2º
8º
(*) Muar only POA P013P
B
0.10
E
A B
10
H
E
E2
E4
1
SEATING
PLANE
DETAIL "A"
e
B
A
C
0.25
D
=
=
=
=
h
D1
SEATING
PLANE
A
F
A1
L
A1
DETAIL "A"
α
P095A
16/18
1
VND810SP
PowerSO-10™ SUGGESTED PAD LAYOUT
TUBE SHIPMENT (no suffix)
14.6 - 14.9
CASABLANCA
MUAR
B
10.8- 11
6.30
C
A
C
A
0.67 - 0.73
B
1
2
3
10
9
0.54 - 0.6
All dimensions are in mm.
Base Q.ty Bulk Q.ty Tube length (± 0.5)
8
9.5
7
4
5
1.27
A
B
C (± 0.1)
0.8
6
Casablanca
Muar
50
50
1000
1000
532
532
10.4 16.4
4.9 17.2
0.8
TAPE AND REEL SHIPMENT (suffix “13TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
600
600
330
1.5
13
20.2
24.4
60
G (+ 2 / -0)
N (min)
T (max)
30.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
W
P0 (± 0.1)
P
24
4
Tape Hole Spacing
Component Spacing
Hole Diameter
24
D (± 0.1/-0) 1.5
Hole Diameter
D1 (min)
F (± 0.05)
K (max)
1.5
11.5
6.5
2
Hole Position
Compartment Depth
Hole Spacing
P1 (± 0.1)
All dimensions are in mm.
End
Start
Top
No components
500mm min
Components
No components
cover
tape
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
17/18
1
VND810SP
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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18/18
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