VND810PEPTR-E [STMICROELECTRONICS]
DOUBLE CHANNEL HIGH SIDE DRIVER; 双通道高侧驱动器
| 型号： | VND810PEPTR-E |
| 厂家： | 
ST |
| 描述： | DOUBLE CHANNEL HIGH SIDE DRIVER |
| 文件： | 总15页 (文件大小：534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VND810PEP-E
DOUBLE CHANNEL HIGH SIDE DRIVER
TARGET SPECIFICATION
Table 1. General Features
Figure 1. Package
TYPE
R
I
V
CC
DS(on)
OUT
VND810PEP-E 160 mΩ (*)
3.5 A (*)
36 V
(*) Per each channel
■ CMOS COMPATIBLE INPUTS
■ OPEN DRAIN STATUS OUTPUTS
■ ON STATE OPEN LOAD DETECTION
■ OFF STATE OPEN LOAD DETECTION
■ SHORTED LOAD PROTECTION
■ UNDERVOLTAGE AND OVERVOLTAGE
SHUTDOWN
■ PROTECTION AGAINST LOSS OF GROUND
■ VERY LOW STAND-BY CURRENT
■ REVERSE BATTERY PROTECTION (**)
■ IN COMPLIANCE WITH THE 2002/95/EC
EUROPEAN DIRECTIVE
PowerSSO-12
DESCRIPTION
The VND810PEP-E is a monolithic device designed
in STMicroelectronics VIPower M0-3 Technology,
intended for driving any kind of load with one side
connected to ground.
Active current limitation combined with thermal
shutdown and automatic restart protects the
device against overload. The device detects open
load condition both in on and off state. Output
Active V
pin voltage clamp protects the device
shorted to V is detected in the off state. Device
automatically turns off in case of ground pin
disconnection.
CC
CC
against low energy spikes (see ISO7637 transient
compatibility table).
Table 2. Order Codes
Package
Tube
VND810PEP-E
Tape and Reel
PowerSSO-12
VND810PEPTR-E
Note: (**) See application schematic at page 9
Rev. 4
November 2004
1/15
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
VND810PEP-E
Figure 2. Block Diagram
Vcc
Vcc
CLAMP
OVERVOLTAGE
UNDERVOLTAGE
CLAMP 1
GND
OUTPUT1
OUTPUT2
INPUT1
DRIVER 1
CLAMP 2
STATUS1
CURRENT LIMITER 1
OPENLOAD ON 1
DRIVER 2
LOGIC
OVERTEMP. 1
CURRENT LIMITER 2
OPENLOAD ON 2
INPUT2
OPENLOAD OFF 1
STATUS2
OPENLOAD OFF 2
OVERTEMP. 2
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage
41
- 0.3
- V
Reverse DC Supply Voltage
DC Reverse Ground Pin Current
DC Output Current
V
CC
GND
OUT
- I
- 200
mA
A
I
Internally Limited
- 6
- I
OUT
Reverse DC Output Current
DC Input Current
A
I
IN
+/- 10
mA
mA
I
DC Status Current
+/- 10
stat
Electrostatic Discharge (Human Body Model:
R=1.5KΩ; C=100pF)
- INPUT
4000
4000
5000
5000
V
V
V
V
V
ESD
- STATUS
- OUTPUT
- V
CC
P
Power Dissipation T =25°C
54
W
°C
°C
°C
tot
C
T
Junction Operating Temperature
Case Operating Temperature
Storage Temperature
Internally Limited
- 40 to 150
j
T
c
T
- 55 to 150
stg
2/15
VND810PEP-E
Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins
GND
1
2
3
4
5
6
12
11
10
9
8
7
Vcc
NC
OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT2
Vcc
INPUT1
STATUS1
STATUS2
INPUT2
TAB = Vcc
Connection / Pin Status N.C. Output
Input
Floating
X
X
X
X
X
To Ground
Through 10KΩ resistor
Figure 4. Current and Voltage Conventions
I
S
V
F1
(*)
I
IN1
V
CC
V
CC
INPUT 1
I
OUT1
I
STAT1
V
IN1
OUTPUT 1
STATUS 1
INPUT 2
V
OUT1
I
V
IN2
STAT1
I
OUT2
I
V
IN2
STAT2
OUTPUT 2
V
OUT2
STATUS 2
GND
V
STAT2
I
GND
(*) V = V
- V
during reverse battery condition
Fn
CCn
OUTn
Table 4. Thermal Data
Symbol
Parameter
Value
2.3
Unit
°C/W
°C/W
R
Thermal resistance junction-case
Thermal resistance junction-ambient
(MAX)
(MAX)
thj-case
R
61 (*)
50 (**)
thj-amb
2
Note: (*) When mounted on a standard single-sided FR-4 board with 1cm of Cu (at least 35µm thick) connected to all V pins.
CC
2
Note: (**) When mounted on a standard single-sided FR-4 board with 8cm of Cu (at least 35µm thick) connected to all V
pins.
CC
3/15
VND810PEP-E
ELECTRICAL CHARACTERISTICS (8V<V <36V; -40°C<T <150°C unless otherwise specified)
CC
j
(Per each channel)
Table 5. Power Outputs
Symbol
Parameter
Test Conditions
Min.
5.5
3
Typ.
13
4
Max.
36
Unit
V
V
CC
Operating Supply Voltage
Undervoltage Shut-down
Overvoltage Shut-down
V
USD
5.5
V
V
OV
36
V
I
I
=1A; T =25°C
160
320
mΩ
mΩ
OUT
j
R
On State Resistance
ON
=1A; V >8V
OUT
CC
12
40
µA
Off State; V =13V; V =V
=0V
OUT
CC
IN
Off State; V =13V; V =V
T =25°C
j
=0V;
OUT
CC
IN
I
Supply Current
S
12
5
25
7
µA
mA
On State; V =13V; V =5V; I
=0A
OUT
CC
IN
I
Off State Output Current
Off State Output Current
Off State Output Current
Off State Output Current
V =V =0V
OUT
0
50
0
µA
µA
µA
µA
L(off1)
L(off2)
L(off3)
L(off4)
IN
I
I
I
V =0V; V
=3.5V
-75
IN
OUT
V =V
=0V; V =13V; T =125°C
OUT
5
IN
CC
j
V =V
=0V; V =13V; T =25°C
OUT
3
IN
CC
j
Table 6. Switching (V =13V)
CC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
R =13Ω from V rising edge to
OUT
L
IN
t
Turn-on delay time
30
µs
d(on)
V
=1.3V
R =13Ω from V falling edge to
OUT
L
IN
t
Turn-on delay time
30
µs
d(off)
V
=11.7V
See
relative
diagram
(dV
dt)
/
/
R =13Ω from V
OUT
=1.3V to
OUT
L
OUT
Turn-on voltage slope
V/µs
V
=10.4V
on
See
relative
diagram
(dV
R =13Ω from V
=11.7V to
OUT
OUT
L
Turn-off voltage slope
V/µs
dt)
V
OUT
=1.3V
off
Table 7. V
Symbol
- Output Diode
Parameter
CC
Test Conditions
Min
Min
Typ
Typ
Max
Unit
V
Forward on Voltage
-I
=0.5A; T =150°C
0.6
V
F
OUT
j
Table 8. Status Pin
Symbol
Parameter
Test Conditions
Max
Unit
Status Low Output
Voltage
V
I
I
= 1.6 mA
0.5
V
STAT
STAT
Status Leakage Current Normal Operation; V
= 5V
= 5V
10
100
8
µA
LSTAT
STAT
Status Pin Input
Normal Operation; V
Capacitance
C
pF
STAT
STAT
I
= 1mA
6
6.8
V
V
STAT
V
Status Clamp Voltage
SCL
I
= - 1mA
-0.7
STAT
4/15
VND810PEP-E
ELECTRICAL CHARACTERISTICS (continued)
Table 9. Logic Input
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
V
I
Input Low Level
1.25
IL
Low Level Input Current
Input High Level
V
V
= 1.25V
1
µA
V
IL
IN
IN
V
I
3.25
IH
High Level Input Current
Input Hysteresis Voltage
= 3.25V
10
8
µA
V
IH
V
I(hyst)
0.5
6
I
I
= 1mA
6.8
V
V
IN
IN
V
Input Clamp Voltage
ICL
= -1mA
-0.7
Table 10. Protections (See note 1)
Symbol
Parameter
Test Conditions
Min.
150
135
7
Typ.
Max.
Unit
°C
T
Shut-down Temperature
Reset Temperature
Thermal Hysteresis
175
200
TSD
T
°C
R
T
t
15
5
°C
hyst
Status Delay in Overload
Conditions
T >T
j
TSD
20
µs
SDL
3.5
7.5
7.5
A
A
I
lim
Current limitation
5.5V<V <36V
CC
Turn-off Output Clamp
Voltage
V
I
=1A; L=6mH
V
-41
V
CC
-48
V -55
CC
V
demag
OUT
CC
Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be
used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration
and number of activation cycles.
Table 11. Openload Detection
Symbol
Parameter
Openload ON State
Detection Threshold
Openload ON State
Detection Delay
Test Conditions
Min
Typ
Max
Unit
I
V =5V
20
40
80
mA
OL
IN
t
I
=0A
OUT
200
µs
DOL(on)
Openload OFF State
Voltage Detection
Threshold
V
OL
V =0V
IN
1.5
2.5
3.5
V
Openload Detection Delay
at Turn Off
t
1000
µs
DOL(off)
5/15
VND810PEP-E
Figure 5.
OPEN LOAD STATUS TIMING (with external pull-up)
OVERTEMP STATUS TIMING
T > T
I
< I
OL
OUT
V > V
OUT OL
j
TSD
V
INn
V
V
INn
V
STAT n
STAT n
t
t
SDL
SDL
t
t
DOL(off)
DOL(on)
Figure 6. Switching time Waveforms
V
OUTn
90%
80%
dV
/dt
OUT (off)
dV
/dt
OUT (on)
10%
t
V
INn
t
d(on)
t
d(off)
t
6/15
VND810PEP-E
Table 12. Truth Table
CONDITIONS
INPUT
OUTPUT
STATUS
n
n
n
L
H
L
H
H
H
Normal Operation
Current Limitation
L
H
H
L
X
X
H
) H
) L
(T < T
(T > T
j
j
TSD
TSD
L
H
L
L
H
L
Overtemperature
Undervoltage
Overvoltage
L
H
L
L
X
X
L
H
L
L
H
H
L
H
H
H
L
H
Output Voltage > V
OLn
L
H
L
H
H
L
Output Current < I
OLn
Table 13. Electrical Transient Requirements on V Pin
CC
TEST LEVELS
III
ISO T/R 7637/1
Test Pulse
I
II
IV
Delays and
Impedance
1
2
-25 V
+25 V
-25 V
-50 V
+50 V
-50 V
-75 V
+75 V
-100 V
+75 V
-6 V
-100 V
+100 V
-150 V
+100 V
-7 V
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
3a
3b
4
+25 V
-4 V
+50 V
-5 V
5
+26.5 V
+46.5 V
+66.5 V
+86.5 V
ISO T/R 7637/1
Test Pulse
TEST LEVELS RESULTS
I
II
C
C
C
C
C
E
III
C
C
C
C
C
E
IV
C
C
C
C
C
E
1
2
C
C
C
C
C
C
3a
3b
4
5
CLASS
CONTENTS
C
E
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
7/15
VND810PEP-E
Figure 7. Waveforms
NORMAL OPERATION
INPUT
n
OUTPUT VOLTAGE
n
STATUS
n
UNDERVOLTAGE
V
V
USDhyst
CC
V
USD
INPUT
n
OUTPUT VOLTAGE
n
STATUS
n
undefined
OVERVOLTAGE
V
>V
CC OV
V
<V
CC OV
V
CC
INPUT
n
OUTPUT VOLTAGE
n
STATUS
n
OPEN LOAD with external pull-up
INPUT
n
V
>V
OL
OUT
OUTPUT VOLTAGE
n
V
OL
STATUS
n
OPEN LOAD without external pull-up
INPUT
n
OUTPUT VOLTAGE
n
STATUS
n
OVERTEMPERATURE
T
T
TSD
R
T
j
INPUT
n
OUTPUT CURRENT
n
STATUS
n
8/15
VND810PEP-E
Figure 8. Application Schematic
+5V
+5V
+5V
V
CC
R
prot
STATUS1
D
ld
R
prot
µC
INPUT1
OUTPUT1
R
prot
STATUS2
R
prot
INPUT2
OUTPUT2
GND
R
GND
D
V
GND
GND
the ground network will produce a shift (j600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
Series resistor in INPUT and STATUS lines are also
required to prevent that, during battery voltage transient,
the current exceeds the Absolute Maximum Rating.
GND PROTECTION NETWORK AGAINST
REVERSE BATTERY
Solution 1: Resistor in the ground line (R
can be used with any type of load.
only). This
GND
The following is an indication on how to dimension the
R
resistor.
GND
1) R
2) R
≤ 600mV / (I
).
S(on)max
)
GND
GND
GND
≥ (−V ) / (-I
Safest configuration for unused INPUT and STATUS pin
is to leave them unconnected.
CC
where -I
is the DC reverse ground pin current and can
GND
be found in the absolute maximum rating section of the
LOAD DUMP PROTECTION
device’s datasheet.
D
is necessary (Voltage Transient Suppressor) if the
ld
Power Dissipation in R
battery situations) is:
(when V <0: during reverse
CC
GND
load dump peak voltage exceeds V
max DC rating.
CC
The same applies if the device will be subject to
2
P = (-V ) /R
transients on the V
line that are greater than the ones
D
CC
GND
CC
shown in the ISO T/R 7637/1 table.
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
µC I/Os PROTECTION:
calculated with formula (1) where I
becomes the
S(on)max
If a ground protection network is used and negative
sum of the maximum on-state currents of the different
transients are present on the V line, the control pins will
CC
devices.
be pulled negative. ST suggests to insert a resistor (R
in line to prevent the µC I/Os pins to latch-up.
)
prot
Please note that if the microprocessor ground is not
common with the device ground then the R
will
GND
The value of these resistors is a compromise between the
leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up
limit of µC I/Os.
produce a shift (I
* R
) in the input thresholds
GND
S(on)max
and the status output values. This shift will vary
depending on many devices are ON in the case of several
high side drivers sharing the same R
.
GND
-V
/I
≤ R
≤ (V
-V -V
OHµC IH GND
) / I
CCpeak latchup
prot
IHmax
If the calculated power dissipation leads to a large
resistor or several devices have to share the same
resistor then the ST suggests to utilize Solution 2 (see
below).
Calculation example:
For V
= - 100V and I
≥ 20mA; V
≥ 4.5V
CCpeak
latchup
OHµC
5kΩ ≤ R
≤ 65kΩ.
prot
Solution 2: A diode (D
) in the ground line.
GND
Recommended R
value is 10kΩ.
prot
A resistor (R
GND
=1kΩ) should be inserted in parallel to
GND
D
if the device will be driving an inductive load.
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
9/15
VND810PEP-E
2) no misdetection when load is disconnected: in this
case the V has to be higher than V ; this
OPEN LOAD DETECTION IN OFF STATE
OUT
OLmax
results in the following condition R <(V
V
)/
PU
PU– OLmax
Off state open load detection requires an external pull-up
I
.
L(off2)
resistor (R ) connected between OUTPUT pin and a
PU
Because I
may significantly increase if V
is
s(OFF)
out
positive supply voltage (V ) like the +5V line used to
PU
pulled high (up to several mA), the pull-up resistor R
PU
supply the microprocessor.
The external resistor has to be selected according to the
following requirements:
should be connected to a supply that is switched OFF
when the module is in standby.
The values of V
, V
and I
are available in
L(off2)
OLmin
OLmax
1) no false open load indication when load is connected:
the Electrical Characteristics section.
in this case we have to avoid V
to be higher than
OUT
V
; this results in the following condition
Olmin
V =(V /(R +R ))R <V
OUT PU L PU L Olmin.
Figure 9. Open Load detection in off state
V batt.
VPU
VCC
RPU
DRIVER
IL(off2)
INPUT
+
LOGIC
OUT
+
-
R
STATUS
VOL
RL
GROUND
10/15
VND810PEP-E
PowerSSO-12 Thermal Data
Figure 10. PowerSSO-12 PC Board
Layout condition of R and Z measurements (PCB FR4 area= 78mm x 78mm, PCB thickness=2mm,
th
th
2
Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8cm ).
Figure 11. R
Vs PCB copper area in open box free air condition
thj-amb
RTHj_amb(°C/W)
70
65
60
55
50
45
0
1
2
3
4
5
6
7
8
9
PCB Cu heatsink area (cm^2)
11/15
VND810PEP-E
Figure 12. PowerSSO-12 Thermal Impedance Junction Ambient Single Pulse
ZTH (°C/W)
100
Footprint
2
8 cm
10
1
0.1
0.0001
0.001
0.01
0.1
1
10
100
1000
Time (s)
Figure 13. Thermal fitting model of a double
channel HSD in PowerSSO-12
Pulse calculation formula
ZTHδ = RTH ⋅ δ + ZTHtp(1 – δ)
δ = tp ⁄ T
where
Table 14. Thermal Parameter
2
Area/island (cm )
Footprint
0.1
8
R1/R7 (°C/W)
R2/R3/R8 (°C/W)
R4 (°C/W)
1.5
8
R5 (°C/W)
28
18
22
R6 (°C/W)
30
C1/C7 (W.s/°C)
C2/C8 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
0.0001
0.0007
0.015
0.1
0.15
3
0.017
5
12/15
VND810PEP-E
PACKAGE MECHANICAL
Table 15. PowerSSO-12™ Mechanical Data
millimeters
Typ
Symbol
Min
Max
A
A1
A2
B
1.250
0.000
1.100
0.230
0.190
4.800
3.800
1.620
0.100
1.650
0.410
0.250
5.000
4.000
C
D
E
e
0.800
H
5.800
0.250
0.400
0º
6.200
0.500
1.270
8º
h
L
k
X
1.900
3.600
2.500
4.200
0.100
Y
ddd
Figure 14. PowerSSO-12™ Package Dimensions
13/15
VND810PEP-E
REVISION HISTORY
Table 16. Revision History
Date
Revision
Description of Changes
Oct. 2004
Nov. 2004
Nov. 2004
Nov. 2004
1
2
3
4
- First Issue
- PowerSSO-12 Thermal Charact. insertion
- PC Board copper area correction
- Thermal data correction.
14/15
VND810PEP-E
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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15/15
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