STLC2500C [STMICROELECTRONICS]
BluetoothTM EDR Single Chip; 蓝牙EDR单芯片
| 型号： | STLC2500C |
| 厂家： | 
ST |
| 描述： | BluetoothTM EDR Single Chip |
| 文件： | 总4页 (文件大小：40K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STLC2500C
BluetoothTM EDR Single Chip
DATA BRIEF
Features
■ The lowest power consumption by design and
technology (see Table 1)
WFBGA48 (4.5mm x 4.5 mmx 0.8 mm)
■ On-chip RAM, on-chip ROM
■ World best EDR throughput (see Table 1)
■ World most performing BT-WLAN coexistence
support for several BT/WLAN coexistence
algorithms (i.e. 2/3/4-wire PTA, in a very
flexible and parametrical way to optimize voice
and data quality over Bluetooth and WLAN)
■ Communication interfaces
– Fast UART up to 4Mbps for HCI
– SPI interface up to 6 Mbps for HCI
– PCM interface for voice
■ Superior voice quality
– WirelessLAN coexistence with 2, 3, 4 wires
– 19 programmable GPIOs
– Pitch-Period Error Concealment (PPEC) for
improved speech quality (in the vicinity of
interference)
– Fast master I2C interface
■ Extended range
■ Ciphering support up to 128-bit keys
– Tx output power up to 8 dBm
■ Software support up to HCI stack
■ Pre-calibrated RF
– H4 and H5 HCI transport layer
– Auto calibration (VCO, filters), no RF
calibration required in production
– HCI proprietary commands and single HCI
command for patch/upgrade download
■ Bluetooth™V2.0 + EDR compliant
– Full EDR support and all BT1.2 errata
– All EDR data rates and packet types
■ Internal power management
■ Supports 1.65V to 2.85 Volts IO systems
■ Seven external components: six decoupling
■ Backward compatibility with legacy devices
capacitors and one single antenna interface
through extended V1.2 feature support
■ Ultra low power architecture with 3 different low
power modes: sleep , deep sleep and
complete power down
– Adaptive Frequency Hopping (AFH)
– Faster connections through interlaced scan
– Extended SCO (eSCO) links
Description
■ Point-to-point, point-to-multi-point
(up to 7 slaves) and scatternet capability
The STLC2500C is a single chip ROM-based
Bluetooth solution implemented in 0.13 µm ultra
low power, ultra low leakage CMOS technology
for mobile terminal applications requiring
integration up to HCI level. Patch RAM is
available, enabling multiple patches/upgrades.
The STLC2500C offers multiple interface options.
The radio has been designed specifically for
single chip requirements for minimal consumption
and BOM count.
■ Asynchronous Connection-Less (ACL) logical
transport link
■ Synchronous Connection Oriented (SCO) link
for 2 simultaneous SCO channels at 64Kbps
■ Clock support for all cellular standards: system
clock input and low power clock
■ ARM7TDMI CPU with 32-bit core and AMBA
(AHB-APB) bus configuration
■ Patch RAM capability
January 2006
Rev 1
1/4
For further information contact your local STMicroelectronics sales office.
www.st.com
4
STLC2500C
Applications
■ Mobile terminal platforms
Order codes
Part Number
Package
Packing
Tray
Tape-on-reel
E-STLC2500C
WFBGA48
E-STLC2500CTR WFBGA48
Figure 1. Block diagram
Table 1.
Technical specifications
Parameter
Values
Power consumption
HV3: 10.9mA, 3-EV3: 6.2mA
DH1: 22mA, 3-DH5: 35.4mA
1 µA
Audio communication
Data communication at maximum throughput
Complete power down
Data rate throughput at host interface in EDR mode
2.178 Mbps
2/4
Rev 1
STLC2500C
Revision history
Table 2.
Date
29-Jan-2006
Document revision history
Revision
Changes
1
Initial release.
Rev 1
3/4
STLC2500C
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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© 2006 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
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www.st.com
4/4
Rev 1
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