STLC3055N_技术文档

STLC3055N

WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT

1 FEATURES

■ MONOCHIP SLIC OPTIMISED FOR WLL &

VoIP APPLICATIONS

Figure 1. Package

■ IMPLEMENT ALL KEY FEATURES OF THE

BORSHT FUNCTION

■ SINGLE SUPPLY (5.5 TO 12V)

TQFP44

■

BUILT IN DC/DC CONVERTER CONTROLLER

Table 1. Order Codes

■ SOFT BATTERY REVERSAL WITH

PROGRAMMABLE TRANSITION TIME.

■ ON-HOOK TRANSMISSION.

■ PROGRAMMABLE OFF-HOOK DETECTOR

THRESHOLD

Part Number

Package

TQFP44

STLC3055N

E-STLC3055N ^(*)

■ METERING PULSE GENERATION AND

(*) ECOPACK® (see Section 9)

FILTER

■ INTEGRATED RINGING

2 DESCRIPTION

■ INTEGRATED RING TRIP

■ PARALLEL CONTROL INTERFACE (3.3V

LOGIC LEVEL)

The STLC3055N is a SLIC device specifically de-

signed for WLL (Wireless Local Loop) and ISDN-

Terminal Adaptors and VoIP applications. One of

the distinctive characteristic of this device is the

ability to operate with a single supply voltage (from

+5.5V to +12V) and self generate the negative bat-

tery by means of an on chip DC/DC converter con-

troller that drives an external MOS switch.

■

PROGRAMMABLE CONSTANT CURRENT FEED

■ SURFACE MOUNT PACKAGE

■ INTEGRATED THERMAL PROTECTION

■ DUAL GAIN VALUE OPTION

■ BCD III S, 90V TECHNOLOGY

■ -40 TO +85°C OPERATING RANGE

Figure 2. Block Diagram

PD

D0

D1

D2

DET

GAIN

SETTING

INPUT LOGIC AND DECODER

OUTPUT LOGIC

BGND

Status and functions

TIP

TX

RX

LINE

OUTPUT

STAGE

SUPERVISION

DRIVER

ZAC1

ZAC

RING

AC PROC

RS

ZB

CREV

CSVR

DC PROC

CLK

RSENSE

DC/DC

CONV.

GATE

VF

CKTTX

CTTX1

TTX PROC

Vcc

CVCC

VPOS

REFERENCE

CTTX2

FTTX

Vss

VOLT.

REG.

VBAT

Agnd

Vbat

RTTX CAC ILTF RD IREF RLIM RTH

AGND

Rev. 10

1/25

February 2006

STLC3055N

2 DESCRIPTION (continued)

The battery level is properly adjusted depending on the operating mode. A useful characteristic for these

applications is the integrated ringing generator.

The control interface is a parallel type with open drain output and 3.3V logic levels.

The metering pulses are generated on chip starting from two logic signals (0, 3.3V) one define the meter-

ing pulse frequency and the other the metering pulse duration. An on chip circuit then provides the proper

shaping and filtering. Metering pulse amplitude and shaping (rising and decay time) can be programmed

by external components. A dedicated cancellation circuit avoid possible CODEC input saturation due to

Metering pulse echo.

Constant current feed can be set from 20mA to 40mA. Off-hook detection threshold is programmable from

5mA to 9mA.

The device, developed in BCDIIIS technology (90V process), operates in the extended temperature range

and integrates a thermal protection that sets the device in power down when T_jexceeds 140°C.

Figure 3. Pin Connection

44

43

42

41

40

39

38

3ꢀ

36

35

34

1

2

3

4

5

6

ꢀ

8

9

D0

D1

33

32

31

30

29

28

2ꢀ

26

25

24

23

CSVR

ILTF

D2

RD

PD

RTH

GAIN SET

N.C.

IREF

RLIM

AGND

CVCC

VPOS

RSENSE

GATE

N.C.

DET

CKTTX

CTTX1

CTTX2

10

11

12

13

14

15

16

1ꢀ

18

19

20

21

22

D00TL488-MOD

Table 2. Absolute Maximum Ratings

Symbol

V_pos

Parameter

Value

Unit

V

Positive Supply Voltage

AGND to BGND

-0.4 to +13

-1 to +1

-0.4 to 5.5

150

A/BGND

V_dig

V

Pin D0, D1, D2, DET, CKTTX

Max. junction Temperature

V

T_j

°C

V

(1)

Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device supply

pins).

90

V_btot

ESD

RATING

Human Body Model

1ꢀ50

500

V

Charged Device Model

(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.

RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10)

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STLC3055N

Table 3. Operating Range

Symbol

Parameter

Value

Unit

V

V_pos

A/BGND

V_dig

Positive Supply Voltage

AGND to BGND

5.5 to +12

-100 to +100

-0.25 to 5.25

-40 to +85

-ꢀ4 max.

mV

V

Pin D0, D1, D2, DET, CKTTX, PD

Ambient Operating Temperature Range

Self Generated Battery Voltage

T_op

°C

V

(1)

V_bat

(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.

RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 11)

Table 4. Thermal Data

Symbol

Parameter

Value

Unit

R_{th j-amb}

Thermal Resistance Junction to Ambient

Typ.

60

°C/W

Table 5. Pin Description

N°

1

D0

D1

D2

PD

Function

Control Interface: input bit 0.

Control Interface: input bit 1.

Control interface: input bit 2.

2

3

4

Power Down input. Normally connected to CVCC (or to logic level high).

5

Gain

SET

Control gain interface: 0 Level R_xgain= 0dB T_xgain= -6dB

1 Level R_xgain= +6dB T_xgain= -12dB

6,ꢀ,36,

NC

Not connected.

38,39,40,42

8

DET

Logic interface output of the supervision detector (active low).

9

CKTTX Metering pulse clock input (12 KHz or 16KHz square wave).

CTTX1 Metering burst shaping external capacitor.

10

11

12

CTTX2 Metering burst shaping external capacitor.

RTTX

Metering pulse cancellation buffer output. TTX filter network should be connected to this

point. If not used should be left open.

13

14

FTTX

RX

Metering pulse buffer input this signal is sent to the line and used to perform TTX filtering.

4 wire input port (RX input). A 100kΩ external resistor must be connected to AGND to bias

the input stage. This signal is referred to AGND. If connected to single supply CODEC

output it must be DC decoupled with proper capacitor.

15

16

1ꢀ

18

ZAC1

ZAC

RS

RX buffer output, (the AC impedance is connected from this node to ZAC).

AC impedance synthesis.

Protection resistors image (the image resistor is connected from this node to ZAC).

ZB

Balance Network for 2 to 4 wire conversion (the balance impedance ZB is connected from

this node to AGND. ZA impedance is connected from this node to ZAC1).

19

20

CAC

TX

AC feedback input, AC/DC split capacitor (CAC).

4 wire output port (TX output). The signal is referred to AGND. If connected to single supply

CODEC input it must be DC decoupled with proper capacitor.

21

VF

Feedback input for DC/DC converter controller.

3/25

STLC3055N

Table 5. (continued)

N°

Function

22

CLK

Power Switch Controller Clock (typ. 125KHz). This pin can also be connected to CVCC or

AGND. When the CLK pin is connected to CVCC an auto-oscillation is internally generated

and it is used instead of the external clock. When the CLK pin is connected to AGND, the

GATE output is disabled.

23

24

GATE

Driver for external Power MOS transistor (P-channel).

RSENSE Voltage input for current sensing. RSENSE should be connected close to this pin and

VPOS pin. The PCB layout should minimize the extra resistance introduced by the copper

tracks.

25

26

2ꢀ

28

VPOS

Positive supply

CVCC Internal positive voltage supply filter.

AGND Analog Ground, must be shorted with BGND.

RLIM

IREF

RTH

RD

Constant current feed programming pin (via RLIM). RLIM should be connected close to this

pin and AGND pin to avoid noise injection.

29

30

31

Internal bias current setting pin. RREF should be connected close to this pin and AGND pin

to avoid noise injection.

Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin

and AGND pin to avoid noise injection.

DC feedback and ring trip input. RD should be connected close to this pin and AGND pin to

avoid noise injection.

32

33

34

35

ILTF

Transversal line current image output.

CSVR Battery supply filter capacitor.

BGND Battery Ground, must be shorted with AGND.

VBAT

Regulated battery voltage self generated by the device via DC/DC converter. Must be

shorted to VBAT1.

3ꢀ

41

43

RING

TIP

2 wire port; RING wire (Ib is the current sunk into this pin).

2 wire port; TIP wire (Ia is the current sourced from this pin).

CREV Reverse polarity transition time control. One proper capacitor connected between this pin

and AGND is setting the reverse polarity transition time. This is the same transition time

used to shape the "trapezoidal ringing" during ringing injection.

44

VBAT1 Frame connection. Must be shorted to VBAT.

3 FUNCTIONAL DESCRIPTION

The STLC3055N is a device specifically developed for WLL VoIP and ISDN-TA applications.

It is based on a SLIC core, on purpose optimised for these applications, with the addition of a DC/DC con-

verter controller to fulfil the WLL and ISDN-TA design requirements.

The SLIC performs the standard feeding, signalling and transmission functions.

It can be set in four different operating modes via the D0, D1, D2 pins of the control logic interface (0 to

3.3V logic levels). The loop status is carried out on the DET pin (active low).

The DET pin is an open drain output to allow easy interfacing with both 3.3V and 5V logic levels.

The four possible SLIC’s operating modes are:

■ Power Down

■ High Impedance Feeding (HI-Z)

■ Active

■ Ringing

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STLC3055N

Table 6 shows how to set the different SLIC operating modes.

Table 6. SLIC Operating Modes.

PD

0

D0

0

D1

0

D2

X

Operating Mode

Power Down

1

0

X

H.I. Feeding (HI-Z)

1

0

1

0

Active Normal Polarity

Active Reverse Polarity

Active TTX injection (N.P.)

Active TTX injection (R.P.)

Ring (D2 bit toggles @ fring)

1

0

1

0

1

0

0/1

3.1 DC/DC Converter

The DC/DC converter controller is driving an external power MOS transistor (P-Channel) in order to gen-

erate the negative battery voltage needed for device operation.

The DC/DC converter controller is synchronised with an external CLK (125KHz typ.)or with an internal

clock generated when the pin CLK is connected to CVCC. One sensing resistor in series to Vpos supply

allows to fix the maximum allowed input peak current. This feature is implemented in order to avoid over-

load on Vpos supply in case of line transient (ex. ring trip detection).

The typical value is obtained for a sensing resistor equal to 110mΩ that will guarantee an average current

consumption from Vpos < ꢀ00mA. When in on-hook the self generated battery voltage is set to a pre-

defined value.

This value can be adjusted via one external resistor (RF1) and it is typical -50V. When RING mode is se-

lected this value is increased to -ꢀ0V typ.

Once the line goes in off-hook condition, the DC/DC converter automatically adjust the generated battery

voltage in order to feed the line with a fixed DC current (programmable via RLIM) optimising in this way

the power dissipation.

3.2 OPERATING MODES

3.2.1 Power Down

When this mode is selected the SLIC is switched off and the TIP and RING pins are in high impedance.

Also the line detectors are disabled therefore the off-hook condition cannot be detected.

This mode can be selected in emergency condition when it is necessary to cut any current delivered to the

line.

This mode is also forced by STLC3055N in case of thermal overload (T_j> 140°C).

In this case the device goes back to the previous status as soon as the junction temperature decrease

under the hysteresis threshold.

No AC transmission is possible in this mode.

3.2.2 High Impedance Feeding (HI-Z)

This operating mode is normally selected when the telephone is in on-hook in order to monitor the line

status keeping the power consumption at the minimum.

The output voltage in on-hook condition is equal to the self generated battery voltage (-50V typ).

When off-hook occurs the DET becomes active (low logic level).

5/25

STLC3055N

The off-hook threshold in HI-Z mode is the same value as programmed in ACTIVE mode.

The DC characteristic in HI-Z mode is just equal to the self generated battery with 2x(1600Ω+Rp) in series

(see fig. 4), where Rp is the external protection resistance.

No AC transmission is possible in this mode.

Figure 4. DC Characteristic in HI-Z Mode.

IL

Vbat

2x(R1+Rp)

Slope: 2x(R1+Rp)

(R1=1600ohm)

VL

Vbat (-50V)

3.2.3 Active

3.2.3.1 DC Characteristics & Supervision

When this mode is selected the STLC3055N provides both DC feeding and AC transmission.

The STLC3055N feeds the line with a constant current fixed by RLIM (20mA to 40mA range). The on-hook

voltage is typically 40V allowing on-hook transmission; the self generated Vbat is -50V typ.

If the loop resistance is very high and the line current cannot reach the programmed constant current feed

value, the STLC3055N behaves like a 40V voltage source with a series impedance equal to the protection

resistors 2xRp (typ. 2x50Ω). Fig. 5 shows the typical DC characteristic in ACTIVE mode.

Figure 5. DC Characteristic in ACTIVE Mode

IL

Ilim

(20 to

40mA)

2Rp

VL

10V

Vbat (-50V)

The line status (on/off hook) is monitored by the SLIC’S supervision circuit. The off-hook threshold can

be programmed via the external resistor RTH in the range from 5mA to 9mA.

Independently on the programmed constant current value, the TIP and RING buffers have a current

source capability limited to 80mA typ. Moreover the power available at Vbat is controlled by the DC/DC

converter that limits the peak current drawn from the Vpos supply. The maximum allowed current peak is

set by R_SENSEresistor.

3.2.3.2 AC Characteristics

The SLIC provides the standard SLIC transmission functions:

Once in active mode the SLIC can operate with two different Tx, Rx Gain. Setting properly by the Gain set

6/25

STLC3055N

control bit (see table ꢀ).

Table 7. Gain Set in Active Mode

Gain set

4 to 2 wire Gain

2 to 4 wire Gain

-6dB

Impedance Synthesis Scale Factor

0

1

0dB

x 50

x 25

+6dB

-12dB

■ Input impedance synthesis: can be real or complex and is set by a scaled (x50 or x25) external ZAC

impedance.

■ Transmit and receive: The AC signal present on the 2W port (TIP/RING) is transferred to the TX output

with a -6dB or -12dB gain and from the RX input to the 2W port with a 0dB or +6dB gain.

■ 2 to 4 wire conversion: The balance impedance can be real or complex, the proper cancellation is

obtained by means of two external impedance ZA and ZB

Once in Active mode (D1=1) the SLIC can operate in different states setting properly D0 and D2 control

bits (see also Table 8).

Table 8. SLIC states in ACTIVE mode

D0

0

D1

1

D2

0

Operating Mode

Active Normal Polarity

Active Reverse Polarity

Active TTX injection (N.P.)

Active TTX injection (R.P.)

0

1

0

1

3.2.3.3 Polarity Reversal

The D2 bit controls the line polarity, the transition between the two polarities is performed in a "soft" way.

This means that the TIP and RING wire exchange their polarities following a ramp transition (see fig.6).

The transition time is controlled by an external capacitor CREV. This capacitor is also setting the shape

of the ringing trapezoidal waveform. When the control pins set battery reversal the line polarity is reversed

with a proper transition time set via an external capacitor (CREV).

Figure 6. TIP/RING Typical Transition from Direct to Reverse Polarity

GND

TIP

4V typ.

40V typ

ON-HOOK

dV/dT set

by CREV

RING

3.2.3.4 Metering Pulse Injection (Ttx)

The metering pulses circuit consists of a burst shaping generator that gives a square wave shaped and a

low pass filter to reduce the harmonic distortion of the output signal.

The metering pulse is obtained starting from two logic signals:

■ CKTTX: is a square wave at the TTX frequency (12 or 16KHz) and should be permanently applied to

ꢀ/25

STLC3055N

the CKTTX pin or at least for all the duration of the TTX pulse (including rising and decay phases).

■ D0: enable the TTX generation circuit and define the TTX pulse duration.

These two signals are processed by a dedicated circuitry integrated on chip that generate the metering

pulse as an amplitude modulated shaped squarewave (SQTTX) (see fig.ꢀ).

Both the amplitude and the envelope of the squarewave (SQTTX) can be programmed by means of ex-

ternal components. In particular the amplitude is set by the two resistors RLV and the shaping by the ca-

pacitor CS.

Figure 7. Metering Pulse Generation Circuit.

Low Pass Filter

C1

-

CTTX1

RLV

RTTX

R2

BURST

OP1

FTTX

R1

SQTTX

CS

+

SHAPING

GENERATOR

CFL

C2

RLV

Sinusoidal wave

pulse metering

Required external components vs. filter order.

CTTX2

Order CFL

R1

C1

R2

C2

THD

13%

6%

D0

1

2

3

X

CKTTX

X

3%

Square wave pulse metering

The waveform so generated is then filtered and injected on the line.

The low pass filter can be obtained using the integrated buffer OP1 connected between pin FTTX (OP1

non inverting input) and RTTX (OP1 output) (see fig.ꢀ) and implementing a "Sallen and Key" configuration.

Depending on the external components count it is possible to build an optimised application depending

on the distortion level required. In particular harmonic distortion levels equal to 13%, 6% and 3% can be

obtained respectively with first, second and third order filters (see fig.ꢀ).

The circuit showed in the "Application diagram" is related to the simple first order filter.

Once the shaped and filtered signal is obtained at RTTX buffer output it is injected on the TIP/RING pins

with a +6dB gain or +12dB gain.

It should be noted that this is the nominal condition obtained in presence of ideal TTX echo cancellation

(obtained via proper setting of RTTX and CTTX).

In addition the effective level obtained on the line will depend on the line impedance and the protection re-

sistors value. In the typical application (TTX line impedance =200Ω, RP = 50Ω, and ideal TTX echo cancel-

lation) the metering pulse level on the line will be 1.33 or 2.66 times the level applied to the RTTX pin.

As already mentioned the metering pulse echo cancellation is obtained by means of two external compo-

nents (RTTX and CTTX) that should match the line impedance at the TTX frequency. This simple network

has a double effect:

■ Synthesize a low output impedance at the TIP/RING pins at the TTX frequency.

■ Cut the eventual TTX echo that will be transferred from the line to the TX output.

8/25

STLC3055N

3.2.4 Ringing

When this mode is selected STLC3055N self generate an higher negative battery (-ꢀ0V typ.) in order to

allow a balanced ringing signal of typically 65Vpeak.

In this condition both the DC and AC feedback are disabled and the SLIC line drivers operate as voltage

buffers. The ring waveform is obtained toggling the D2 control bit at the desired ring frequency. This bit in

fact controls the line polarity (0=direct; 1=reverse). As in the ACTIVE mode the line voltage transition is

performed with a ramp transition, obtaining in this way a trapezoidal balanced ring waveform (see fig.8).

The shaping is defined by the CREV external capacitor.

Selecting the proper capacitor value it is possible to get different crest factor values.

The following table shows the crest factor values obtained with a 20Hz and 25Hz ring frequency and with

1REN. These value are valid either with European or USA specification

Figure 8. TIP/RING Typical Ringing Waveform

GND

TIP

2.5V typ.

65V

typ.

dV/dT set

by CREV

RING

2.5V typ.

VBAT

Table 9. :

CREV

CREST FACTOR @20Hz

CREST FACTOR @25Hz

22nF

1.2

1.26

1.32

2ꢀnF

33nF

1.25

1.33

Not significant (*)

(*) Distorsion already less than 10%.

The ring trip detection is performed sensing the variation of the AC line impedance from on hook (relatively

high) to off-hook (low). This particular ring trip method allows to operate without DC offset superimposed

on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given

negative battery. It should be noted that such a method is optimised for operation on short loop applica-

tions and may not operate properly in presence of long loop applications (> 500Ω ). Once ring trip is de-

tected, the DET output is activated (logic level low), at this point the card controller or a simple logic circuit

should stop the D2 toggling in order to effectively disconnect the ring signal and then set the STLC3055N

in the proper operating mode (normally ACTIVE).

3.2.4.1 Ring Level in Presence of More Telephone in Parallel

As already mentioned above the maximum current that can be drawn from the Vpos supply is controlled

and limited via the external RSENSE. This will limit also the power available at the self generated negative

battery.

If for any reason the ringer load will be too low the self generated battery will drop in order to keep the

power consumption to the fixed limit and therefore also the ring voltage level will be reduced.

In the typical application with R_SENSE= 110mΩ the peak current from Vpos is limited to about 900mA,

which correspond to an average current of ꢀ00mA max. In this condition the STLC3055N can drive up to

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STLC3055N

3REN with a ring frequency fr=25Hz (1REN = 1800Ω + 1.0µF, European standard).

In order to drive up to 5REN (1REN= 6930Ω + 8µF, US standard) it is necessary to modify the external

components as follows:

CREV = 15nF

RD = 2.2KΩ

Rsense = 100mΩ

3.3 Layout Recommendation

A properly designed PCB layout is a basic issue to guarantee a correct behaviour and good noise perfor-

mances. Noise sources can be identified in not enough good grounds, not enough low impedance sup-

plies and parasitic coupling between PCB tracks and high impedance pins of the device.

Particular care must be taken on the ground connection and in this case the star configuration allows sure-

ly to avoid possible problems (see Application Diagram Figg. 9 and 10).

The ground of the power supply (VPOS) has to be connected to the center of the star, let’s call this point

Supply GND. This point should show a resistance as low as possible, that means it should be a ground

plane.

In particular to avoid noise problems the layout should prevent any coupling between the DC/DC convert-

er components that are referred to PGND (CVPOS, CD, L) and analog pins that are referred to AGND (ex:

RD, IREF, RTH, RLIM, VF). AGND and BGND must be shorter together. The GND connection of protec-

tion components have to be connected to the Supply GDND.

As a first reccomendation the components CV, L, D1, CVPOS, RSENSE should be kept as close as pos-

sible to each other and isolated from the other components.

Additional improvements can be obtained:

■ decoupling the center of the star from the analog ground of STLC3055N using small chokes.

■ adding a capacitor in the range of 100nF between VPOS and AGND in order to filter the switch

frequency on VPOS.

3.4 External Components List

In order to properly define the external components value the following system parameters have to be de-

fined:

■ The AC input impedance shown by the SLIC at the line terminals "Zs" to which the return loss

measurement is referred. It can be real (typ. 600Ω) or complex.

■ The AC balance impedance, it is the equivalent impedance of the line "Zl" used for evaluation of the

trans-hybrid loss performances (2/4 wire conversion). It is usually a complex impedance.

■ The value of the two protection resistors Rp in series with the line termination. The line impedance at

the TTX frequency "Zlttx".

■ The metering pulse level amplitude measured at line termination "VLOTTX". In case of low order

filtering, VLOTTX represents the amplitude (Vrms) of the fundamental frequency component. (typ 12 or

16KHz).

■

Pulse metering envelope rise and decay time constant "

τ".

■

The slope of the ringing waveform " V_TRT ".

∆

/∆

■ The value of the constant current limit current "Ilim".

■ The value of the off-hook current threshold "I_TH".

■ The value of the ring trip rectified average threshold current "I_RTH".

■ The value of the required self generated negative battery "V_BATR" in ring mode (max value is ꢀ0V).

This value can be obtained from the desired ring peak level + 5V.

■ The value of the maximum current peak sunk from Vpos "IPK".

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STLC3055N

Table 10. External Components

Name

RRX

Function

Rx input bias resistor

Bias setting current

Formula

RREF = 1.3/Ibias

Typ. Value

100kΩ 5%

26kΩ 1%

RREF

Ibias = 50µA

CSVR

RD

Negative Battery Filter

CSVR = 1/(2π ⋅ fp ⋅ 1.8MΩ)

1.5nF 10%

100V

fp = 50Hz

Ring Trip threshold setting

resistor

RD = 100/I_RTH

2KΩ < RD < 5KΩ

4.12kΩ 1%

@ IRTH = 24mA

CAC

AC/DC split capacitance

22µF 20% 15V

@ RD = 4.12kΩ

RP

Line protection resistor

Rp > 30Ω

50Ω 1%

RLIM

Current limiting programming

RLIM = 1300/Ilim

32.5kΩ < RLIM < 65kΩ

52.3kΩ 1%

@ Ilim = 25mA

RTH

Off-hook threshold programming RTH = 290/I_TH

32.4kΩ 1%

@I_TH= 9mA

(ACTIVE mode)

2ꢀkΩ < RTH < 52kΩ

CREV

Reverse polarity transition time

programming

CREV = ((1/3ꢀ50) · ∆T/∆V_TR

)

22nF 10% 10V

@ 12V/ms

RDD

Pull up resistors

100kΩ

100nF 20% 10V

100µF(4)

CVCC

Internally supply filter capacitor

CVpos Positive supply filter capacitor

with low impedance for switch

mode power supply

CV

Battery supply filter capacitor with

low impedance for switch mode

power supply

100µF 20% 100V (5)

CVB

High frequency noise filter

4ꢀ0nF 20% 100V

100nF 10% 15V

CRD (6) High frequency noise filter

Q1

DC/DC converter switch P ch.

MOS transistor

RDS(ON)≤1.2Ω,VDS = -100V

Total gate charge=20nC max.

with VGS=4.5V and VDS=1V

ID>500mA

Possible choiches:

IRF9510 or IRF9520 or

IRF9120 or equivalent

D1

DC/DC converter series diode

V_r> 100V, t_RR≤ 50ns

R_SENSE= 100mV/I_PK

250KΩ<RF1<300KΩ (ꢀ)

SMBYW01-200

or equivalent

RSENSE DC/DC converter peak current

limiting

110mΩ

@I_PK= 900mA

RF1

Negative battery programming

level

300kΩ 1%

@ V_BATR= -ꢀ0V

RF2

L

Negative battery programming leve

l

9.1kΩ 1%

DC/DC converter inductor

DC resistance ≤ 0.1Ω (8)

L=100µH

SUMIDA CDRH125 or equivalent

Table 11. External Components @Gain Set = 0

Name

RS

Function

Formula

RS = 50 ⋅ (2Rp)

Typ. Value

Protection resistance image

Two wire AC impedance

5kΩ @ Rp = 50Ω

ZAC

ZAC = 50 ⋅ (Zs - 2Rp)

ZA = 50 ⋅ Zs

25kΩ 1% @ Zs = 600Ω

30kΩ 1% @ Zs = 600Ω

ZA (1)

SLIC impedance balancing

network

ZB (1)

Line impedance balancing

network

ZB = 50 ⋅ Zl

30kΩ 1% @ Zl = 600Ω

11/25

STLC3055N

Table 11. External Components @Gain Set = 0 (continued)

Name

Function

Formula

Typ. Value

CCOMP AC feedback loop compensation fo = 250kHz

CCOMP = 1/(2π⋅fo⋅100⋅(RP))

120pF 10% 10V @ Rp = 50Ω

CH

Trans-Hybrid Loss frequency

compensation

CH = CCOMP

120pF 10% 10V

RTTX (3) Pulse metering cancellation resistor

RTTX = 50Re (Zlttx+2Rp)

15kΩ @Zlttx = 200Ω real

CTTX (3) Pulse metering cancellation

capacitor

CTTX = 1/{50⋅2π⋅fttx[-lm(Zlttx)]}

100nF 10% 10V (2)

@ Zlttx = 200Ω real

RLV = 63.3·10^3··α·V_LOTTX

α = (|Zlttx + 2Rp|/|Zlttx|)

RLV

Pulse metering level resistor

16.2kΩ @ V_LOTTX= 1ꢀ0mVrms

CS

Pulse metering shaping capacitor CS = τ/(2⋅RLV)

100nF 10% 10V

@ τ = 3.2ms, RLV = 16.2kΩ

CFL

Pulse metering filter capacitor CFL = 2/(2π⋅fttx⋅RLV)

1.5nF 10% 10V

@fttx = 12kHz RLV = 16.2kΩ

Table 12. External Components @Gain Set = 1

Name

RS

Function

Formula

RS = 25 ⋅ (2Rp)

Typ. Value

Protection resistance image

Two wire AC impedance

2.55kΩ @ Rp = 50Ω

12.5kΩ 1% @ Zs = 600Ω

15kΩ 1% @ Zs = 600Ω

ZAC

ZAC = 25 ⋅ (Zs - 2Rp)

ZA = 25 ⋅ Zs

ZA (1)

SLIC impedance balancing

network

ZB (1)

Line impedance balancing

network

ZB = 25 ⋅ Zl

15kΩ 1% @ ZI = 600Ω

CCOMP AC feedback loop compensation fo = 250kHz

CCOMP = 2/(2π⋅fo⋅100⋅(RP))

220pF 10% 10VL @ Rp = 50

220pF 10% 10V

Ω

CH

Trans-Hybrid Loss frequency

compensation

CH = CCOMP

RTTX (3) Pulse metering cancellation

resistor

RTTX = 25Re (Zlttx+2Rp)

ꢀ.5kΩ @Zlttx = 200Ω real

CTTX (3) Pulse metering cancellation

capacitor

CTTX = 1/25⋅2π⋅fttx⋅[-lm(Zlttx)]

100nF 10% 10V (2)

@ Zlttx = 200Ω real

RLV = 31.ꢀ·10^3··α·V_LOTTX

α = (|Zlttx + 2Rp|/|Zlttx|)

RLV

Pulse metering level resistor

16.2kΩ @ V_LOTTX= 340mVrms

CS

Pulse metering shaping capacitor CS = τ/(2⋅RLV)

100nF 10% 10V

@ τ = 3.2ms, RLV = 16.2kΩ

CFL

Pulse metering filter capacitor CFL = 2/(2π⋅fttx⋅RLV)

1.5nF 10% 10V

@fttx = 12kHz RLV = 16.2kΩ

(1) In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|.

(2) In this case CTTX is just operating as a DC decoupling capacitor (fp=100Hz).

(3) Defining ZTTX as the impedance of RTTX in series with CTTX, RTTX and CTTX can also be calculated from the following formula:

ZTTX=50*(Zlttx+2Rp).

(4) CVpos should be defined depending on the power supply current capability and maximum allowable ripple.

(5) For low ripple application use 2x4ꢀµ F in parallel.

(6) Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input).

(ꢀ) RF1 sets the self generated battery voltage in RING and ACTIVE(Il=0) mode as follows:

26ꢀkΩ

-46V

280kΩ

-48V

294kΩ

-49V

300kΩ

-50V

V

BAT(ACTIVE)

-62V

-65V

-68V

-ꢀ0V

BATR(RING)

V

should be defined considering the ring peak level required (Vringpeak=VBATR-6V typ.).

BATR

The above relation is valid provided that the Vpos power supply current capability and the RSENSE programming allow to source all the

current requested by the particular ringer load configuration.

(8) For high efficiency in HI-Z mode coil resistance @125kHz must be < 3Ω

12/25

STLC3055N

Figure 9. Application Diagram.

VPOS

CVPOS

CVCC

RSENSE

RX TX

RRX

RX TX AGND BGND

RS

CVCC

VPOS

RS

RSENSE

GATE

Q1

ZAC

P-ch

CCOMP

D1

ZAC1

VBAT

ZAC

ZA

CVB

RF1

RF2

ZB

L

VF

CV

CH

VDD

ZB

CLK

TIP

CLK

GAIN SET

RDD

RP

TIP

STLC3055N

RING

DET

D0

DET

D0

CONTROL

INTERFACE

CSVR

CREV

D1

D2

CREV

CSVR

PD

TTX CLOCK

CKTTX

RTH

RLIM

IREF

RLV

CTTX1

CS

CTTX2

FTTX

RREF

RLIM

RTH

RTTX

CAC

ILTF

RD

CFL

RTTX

RD

CRD

D00TL489A

AGND

BGND

CTTX

CAC

SYSTEM GND

SUGGESTED GROUND LAY-OUT

PGND

Figure 10. Application Diagram without Metering Pulse Generation.

VPOS

CVCC

CVPOS

RSENSE

RX TX

RRX

RX TX AGND BGND

RS

CVCC

VPOS

RS

RSENSE

GATE

Q1

ZAC

P-ch

CCOMP

D1

ZAC1

VBAT

ZAC

ZA

CVB

RF1

ZB

L

VF

CV

CH

VDD

RDD

ZB

RF2

CLK

TIP

CLK

GAIN SET

RP

TIP

STLC3055N

RING

DET

D0

DET

D0

CONTROL

INTERFACE

CSVR

CREV

D1

D2

CREV

CSVR

PD

CKTTX

CTTX1

CTTX2

FTTX

RTH

RLIM

IREF

RREF

RLIM

RTH

RTTX

CAC

ILTF

RD

CRD

D00TL490/B

AGND

BGND

CAC

SYSTEM GND

SUGGESTED GROUND LAY-OUT

PGND

13/25

STLC3055N

4 ELECTRICAL CHARACTERISTICS

Test conditions: V_pos= 6.0V, AGND = BGND, Normal Polarity, T_amb= 25°C.

External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table.

Note: Testing of all parameter is performed at 25°C. Characterisation as well as design rules used allow

correlation of tested performances at other temperatures. All parameters listed here are met in the oper-

ating range: -40 to +85°C.

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

DC CHARACTERISTICS

V_lohi

Line voltage

Il = 0, HI-Z

(High impedance feeding)

_amb= 0 to 85°C

44

50

V

T

V_lohi

Il = 0, HI-Z

42

48

V

(High impedance feeding)

T

_amb= -40 to 85°C

V_loa

Ilim

Line voltage

Il = 0, ACTIVE

33

31

40

3ꢀ

V

T

_amb= 0 to 85°C

Il = 0, ACTIVE

T

_amb= -40 to 85°C

Lim. current programming

range

ACTIVE mode

20

40

10

mA

%

Ilima

Lim. current accuracy

ACTIVE mode.

-10

Rel. to programmed value

20mA to 40mA

Rfeed HI Feeding resistance

HI-Z (High Impedance feeding)

2.4

50

3.6

kΩ

AC CHARACTERISTICS

L/T

T/L

Long. to transv.

(see Appendix for test circuit)

Rp = 50Ω, 1% tol.,

ACTIVE N. P., R_L= 600Ω (*)

f = 300 to 3400Hz

58

45

53

26

dB

Transv. to long.

(see Appendix for test circuit)

Rp = 50Ω, 1% tol.,

ACTIVE N. P., R_L= 600Ω (*)

f = 300 to 3400Hz

40

48

dB

Transv. to long.

(see Appendix for test circuit)

Rp = 50Ω, 1% tol.,

ACTIVE N. P., R_L= 600Ω (*)

f = 1kHz

2WRL

THL

2W return loss

300 to 3400Hz,

ACTIVE N. P., R_L= 600Ω (*)

22

30

dB

Trans-hybrid loss

300 to 3400Hz,

20Log|VRX/VTX|,

ACTIVE N. P., R_L= 600Ω (*)

Ovl

2W overload level

at line terminals on ref. imped.

ACTIVE N. P., R_L= 600Ω (*)

3.2

dBm

TXoff

G24

TX output offset

ACTIVE N. P., R_L= 600Ω (*)

-250

-6.4

250

-5.6

mV

dB

Transmit gain abs.

0dBm @ 1020Hz,

ACTIVE N. P., R_L= 600Ω (*)

G42

Receive gain abs.

0dBm @ 1020Hz,

ACTIVE N. P., R_L= 600Ω (*)

-0.4

0.4

dB

14/25

STLC3055N

4 ELECTRICAL CHARACTERISTICS

Test conditions: V_pos= 6.0V, AGND = BGND, Normal Polarity, T_amb= 25°C.

External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table.

Note: Testing of all parameter is performed at 25°C. Characterisation as well as design rules used allow

correlation of tested performances at other temperatures. All parameters listed here are met in the oper-

ating range: -40 to +85°C.

Symbol

Parameter

Test Condition

rel. 1020Hz; 0dBm,

Min.

Typ.

Max.

Unit

G24f

TX gain variation vs. freq.

-0.12

0.12

dB

300 to 3400Hz,

ACTIVE N. P., R_L= 600Ω (*)

G24f

V2Wp

V4Wp

RX gain variation vs. freq.

rel. 1020Hz; 0dBm,

300 to 3400Hz,

ACTIVE N. P., R_L= 600Ω (*)

-0.12

0.12

-68

dB

Idle channel noise at line 0dB

gainset

psophometric filtered

ACTIVE N. P., R_L= 600Ω (*)

T_amb= 0 to +85°C

-ꢀ3

-68

-ꢀ5

dBmp

Idle channel noise at line 0dB

gainset

psophometric filtered

ACTIVE N. P., R_L= 600Ω (*)

T_amb= -40 to +85°C

Idle channel noise at line 0dB

gainset

psophometric filtered

-ꢀ0

ACTIVE N. P., R_L= 600Ω (*)

T

_amb= 0 to +85°C

Idle channel noise at line 0dB

gainset

psophometric filtered

ACTIVE N. P., R_L= 600Ω (*)

T

_amb= -40 to +85°C

Thd

Total Harmonic Distortion

Metering pulse level on line

ACTIVE N. P., R_L= 600Ω (*)

-44

dB

VTTX

ACTIVE - TTX; Gain Set = 1

Zl = 200Ω fttx = 12kHz;

260

340

125

mVrms

CLKfreq

CLK operating range

-10%

10%

kHz

(*) R : Line Resistance

L

RING

Vring

Line voltage

RING D2 toggling @ fr = 25Hz

Load = 3REN;

Crest Factor = 1.25

45

44

49

48

Vrms

1REN = 1800Ω + 1.0µF

T

_amb= 0 to +85°C

Vring

Line voltage

RING D2 toggling @ fr = 25Hz

Load = 3REN;

Vrms

Crest Factor = 1.25

1REN = 1800Ω + 1.0µF

T

_amb= -40 to +85°C

DETECTORS

IOFFTHA Off/hook current threshold

ACT. mode, RTH = 32.4kΩ 1%

10.5

mA

kΩ

(Prog. ITH = 9mA)

ROFTHA Off/hook loop resistance

threshold

ACT. mode, RTH = 32.4kΩ 1%

(Prog. ITH = 9mA)

3.4

6

IONTHA On/hook current threshold

ACT. mode, RTH = 32.4kΩ 1%

(Prog. ITH = 9mA)

mA

15/25

STLC3055N

4 ELECTRICAL CHARACTERISTICS

Test conditions: V_pos= 6.0V, AGND = BGND, Normal Polarity, T_amb= 25°C.

External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table.

Note: Testing of all parameter is performed at 25°C. Characterisation as well as design rules used allow

correlation of tested performances at other temperatures. All parameters listed here are met in the oper-

ating range: -40 to +85°C.

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

RONTHA On/hook loop resistance

threshold

ACT. mode, RTH = 32.4kΩ 1%

(Prog. ITH = 9mA)

8

kΩ

IOFFTHI Off/hook current threshold

Hi Z mode, RTH = 32.4kΩ 1%

10.5

mA

Ω

(Prog. ITH = 9mA)

ROFFTHI Off/hook loop resistance

threshold

Hi Z mode, RTH = 32.4kΩ 1%

(Prog. ITH = 9mA)

800

6

IONTHI

On/hook current threshold

Hi Z mode, RTH = 32.4kΩ 1%

(Prog. ITH = 9mA)

mA

kΩ

mA

%

RONTHI On/hook loop resistance

threshold

Hi Z mode, RTH = 32.4kΩ 1%

(Prog. ITH = 9mA)

8

Irt

Ring Trip detector threshold

range

RING

20

-15

50

15

Irta

Ring Trip detector threshold

accuracy

Trtd

Td

Ring trip detection time

Dialling distortion

Loop resistance

RING

TBD

160

ms

Ω

ACTIVE

-1

1

Rlrt ⁽¹⁾

ThAl

500

Tj for th. alarm activation

°C

(1) Rlrt = Maximum loop resistance (incl. telephone) for correct ring trip detection.

DIGITAL INTERFACE

INPUTS: D0, D1, D2, PD, CLK

OUTPUTS: DET

Vih

Vil

Iih

Iil

In put high voltage

Input low voltage

Input high current

Input low current

Output low voltage

2

V

0.8

10

-10

µA

V

10

Vol

Iol = 1mA

0.45

PSRR AND POWER CONSUMPTION

PSERRC Power supply rejection Vpos to Vripple = 100mVrms

26

36

dB

2W port

50 to 4000Hz

Ivpos

Ipk

Vpos supply current @ ii = 0

HI-Z On-Hook

ACTIVE On-Hook,

RING (line open)

13

50

55

25

80

90

mA

Peak current limiting accuracy

RING Off-Hook

RSENSE = 110mΩ

-20%

950

+20% mApk

16/25

STLC3055N

5 APPENDIX A

5.1 STLC3055N Test Circuits

Referring to the application diagram shown in fig. 9 of the STLC3055N datasheet and using as external

components the Typ. Values specified in the "External Components" Tables 10 and 11 (pages 11, 12) find

below the proper configuration for each measurement.

All measurements requiring DC current termination should be performed using "Wandel & Goltermann

DC Loop Holding Circuit GH-1" or equivalent.

Figure 11. 2W Return Loss

2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs)

W&G GH1

Zref

TX

TIP

600ohm

µ

100 F

Vs

STLC3055N

application

circuit

100mA

DC max

1Kohm

E

Zin = 100K

200 to 6kHz

100µF

1Kohm

RX

RING

Figure 12. THL Trans Hybrid Loss

THL = 20Log|Vrx/Vtx|

W&G GH1

TIP

TX

100 F

µ

Vtx

STLC3055N

application

circuit

100mA

DC max

600ohm

Zin = 100K

200 to 6kHz

100µF

RX

RING

Vrx

1ꢀ/25

STLC3055N

Figure 13. G24 Transmit Gain

G24 = 20Log|2Vtx/E|

W&G GH1

TIP

TX

100 F

µ

Vtx

STLC3055N

application

circuit

100mA

DC max

600ohm

E

Zin = 100K

200 to 6kHz

100µF

RX

RING

Figure 14. G42 Receive Gain

G42 = 20Log|VI/Vrx|

W&G GH1

TIP

TX

µ

100 F

STLC3055N

100mA

Vl

DC max

application

circuit

600ohm

Zin = 100K

200 to 6kHz

µ

100 F

RX

RING

Vrx

Figure 15. PSRRC Power supply rejection Vpos to 2W port

PSSRC = 20Log|Vn/Vl|

W&G GH1

TIP

TX

100µF

STLC3055N

application

circuit

100mA

DC max

Vl

600ohm

Zin = 100K

200 to 6kHz

100µF

RX

RING

VPOS

Vn

~

18/25

STLC3055N

Figure 16. L/T Longitudinal to Transversal Conversion

L/T = 20Log|Vcm/Vl|

W&G GH1

300ohm

µ

100 F

TIP

TX

µ

100 F

STLC3055N

application

circuit

100mA

DC max

Vl

Impedance matching

better than 0.1%

Zin = 100K

200 to 6kHz

Vcm

µ

100 F

RX

RING

300ohm

µ

100 F

Figure 17. T/L Transversal to Longitudinal Conversion

T/L = 20Log|Vrx/Vcm|

W&G GH1

µ

100 F

300ohm

TIP

TX

µ

100 F

STLC3055N

100mA

DC max

application

circuit

Impedance matching

better than 0.1%

Zin = 100K

200 to 6kHz

Vcm

600ohm

µ

100 F

RX

RING

Vrx

300ohm

100µF

Figure 18. VTTX Metering Pulse Level on Line

TIP

TX

STLC3055N

Vlttx

application

circuit

200ohm

RX

RING

CKTTX

fttx (12 or 16kHz)

19/25

STLC3055N

Figure 19. V2Wp and W4Wp: Idle Channel Psophometric Noise at Line and TX.

V2Wp = 20Log|Vl/0.774l|; V4Wp = 20Log|Vtx/0.774l|

W&G GH1

TIP

TX

100µF

100mA

Vtx

psophometric

filtered

STLC3055N

application

circuit

DC max

600ohm

Zin = 100K

200 to 6kHz

Vl

psophometric

filtered

100µF

RX

RING

6 APPENDIX B

6.1 STLC3055N Overvoltage Protection

Figure 20. Simplified Configuration for Indoor Overvoltage Protection

STPR120A

BGND

STLC3055N

RP1

RP2

TIP

RING

VBAT

STPR120A

RP1 = 30ohm:

RP2 =Fuse or PTC > 18ohm

Figure 21. Standard Overvoltage Protection Configuration for K20 Compliance

BGND

STLC3055N

RP1

RP2

TIP

LCP1521

RING

VBAT

RP1 = 30ohm:

RP2 =Fuse or PTC > 18ohm

20/25

STLC3055N

7 APPENDIX C

7.1 TYPICAL STATE DIAGRAM FOR STLC3055N OPERATION

Figure 22.

Normally used for

On Hook Transmission

Tj>Tth

PD=0, D0=D1=0

Active

On Hook

Power

Down

Ring Pause

Ring Burst

D0=0, D1=1,

D2=0

Ring Burst

Ringing

D0=1, D1=0,

D2=0/1

PD=1,

D0=D1=0

On Hook Detection for T>Tref

HI-Z

Feeding

Ring Trip

Detection

Active

On Hook Condition

Off Hook

Off Hook Detection

D0=0, D1=1,

D2=0

Off Hook Detection

Note: all state transitions are under the microprocessor control.

21/25

STLC3055N

8 APPENDIX D

8.1 STLC3055Q STLC3055N compatibility.

STLC3055N is pin to pin compatible with the old STLC3055Q but offer a better performance in term of

Power consumption and can be set in a new gain configuration in order to be compatible with the 3.3V

codec.

8.1.1 Typical power consumption comparison

Table 13.

Operative mode

STLC3055Q

52 - 60mA

STLC3055N

13 - 25mA

50 - 80mA

55 - 90mA

HI-Z

Active on hook

Ring (no REN)

93 - 115mA

120 - 140mA

To meet this result some differences, with a minimum impact on the application, has been introduced in

STLC3055N.

8.1.2 Hardware difference:

■

RX input. In STLC3055N it is necessary a 100kΩ external resistor between RX input and

AGND to bias the input stage.

■

Rp. The STLC3055N required a Rp value of 50Ω instead of 41Ω.

TTX filter. To optimize the ttx signal dynamic we have change the values of RLV and CFL;

Table 14.

Component

STLC3055Q

STLC3055N

100kΩ

RRX

Rp

41Ω

2ꢀkΩ

1nF

50Ω

RLV

CFL

16.2kΩ

1.5nF

8.1.3 Parameter differences:

Table 15.

Parameter

Absolute Max. Rating

STLC3055Q

1ꢀV

STLC3055N

13V

Operating Range

15.8V

12V

Typ Metering pulse level (Gs 1)

Typ Metering pulse level (Gs 0)

340mVrms

1ꢀ0mVrms

200mVrms

22/25

STLC3055N

9 PACKAGE INFORMATION

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These

packages have a Lead-free second level interconnect. The category of second Level Interconnect is

marked on the package and on the inner box label, in compliance with JEDEC Standard JESD9ꢀ.

The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Figure 23. TQFP44 (10 x 10) Mechanical Data & Package Dimensions

mm

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN. TYP. MAX. MIN.

TYP. MAX.

0.063

A

A1

A2

B

1.60

0.05

1.35

0.30

0.09

0.15 0.002

0.006

1.40

0.3ꢀ

1.45 0.053 0.055 0.05ꢀ

0.45 0.012 0.015 0.018

C

0.20 0.004

0.008

D

11.80 12.00 12.20 0.464 0.4ꢀ2 0.480

9.80 10.00 10.20 0.386 0.394 0.401

D1

D3

E

8.00

0.315

11.80 12.00 12.20 0.464 0.4ꢀ2 0.480

9.80 10.00 10.20 0.386 0.394 0.401

E1

E3

e

8.00

0.80

0.60

1.00

0.315

0.031

0.ꢀ5 0.018 0.024 0.030

0.039

L

0.45

TQFP44 (10 x 10 x 1.4mm)

L1

k

0˚(min.), 3.5˚(typ.), ꢀ˚(max.)

D

D1

A

A2

A1

33

23

34

22

0.10mm

.004

Seating Plane

12

44

11

1

C

e

K

TQFP4410

00ꢀ6922 D

23/25

STLC3055N

Table 16. Revision History

Date

Revision

Description of Changes

September 2003

October 2004

4

5

First Issue

Update Functional Description and Electrical Characteristics. Aligned

the graphic style to be compliant with the new “Corporate Technical

Pubblications Design Guide”

October 2004

6

ꢀ

Modified the application diagrams and some typo errors.

November 2004

Removed all max. values of the ‘Line Voltage’ parameter on the page

14/24.

Changed the unit from mA to % of the ‘Ilima’ parameter on the page 14/

24.

January 2005

8

Add pin 4 PD in Applications and Block Diagram

Add in Table 2 ‘ESD Rating’

July 2005

9

Changed VTTX value

February 2006

10

Added part number “E-STLC3055N” (ECOPACK).

Added RRX resistance in the figures 9 and 10.

Added Appendix D.

24/25

STLC3055N

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25/25


型号：	STLC3055N
厂家：	ST
描述：	WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT WLL和ISDN- TA用户线接口电路数字传输接口电池电信集成电路电信电路综合业务数字网 CD WLL
文件：	总25页 (文件大小：316K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STLC3055N [STMICROELECTRONICS]

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