STLC3055QTR_技术文档

STLC3055

WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT

MONOCHIP SLIC OPTIMISED FOR WLL &

ISDN-TA APPLICATIONS

IMPLEMENT ALL KEY FEATURES OF THE

BORSHT FUNCTION

SINGLE SUPPLY (5.5 TO 15.8V)

BUILT IN DC/DC CONVERTER CONTROL-

LER.

TQFP44

SOFT BATTERY REVERSAL WITH PRO-

GRAMMABLE TRANSITION TIME.

ORDERING NUMBERS: STLC3055Q

ON-HOOK TRANSMISSION.

PROGRAMMABLE OFF-HOOK DETECTOR

THRESHOLD

STLC3055QTR

METERING PULSE GENERATION AND FIL-

TER

INTEGRATED RINGING

INTEGRATED RING TRIP

PARALLEL CONTROL INTERFACE (3.3V

LOGIC LEVEL)

PROGRAMMABLE CONSTANT CURRENT

FEED

DESCRIPTION

The STLC3055 is a SLIC device specifically de-

signed for WLL (Wireless Local Loop) and ISDN-

Terminal Adaptors. One of the distinctive charac-

teristic of this device is the ability to operate with

a single supply voltage (from +5.5V to +15.8V)

and self generate the negative battery by means

of an on chip DC/DC converter controller that

drives an external MOS switch.

SURFACE MOUNT PACKAGE

INTEGRATED THERMAL PROTECTION

-40 TO +85°C OPERATING RANGE

The battery level is properly adjusted depending

on the operatingmode. A useful characteristic for

BLOCK DIAGRAM

D0

D1

D2

DET

INPUT LOGICAND DECODER

OUTPUT LOGIC

BGND

Status and functions

TIP

TX

RX

LINE

OUTPUT

SUPERVISION

DRIVER

STAGE

ZAC1

ZAC

RING

AC PROC

RS

ZB

CREV

DC PROC

CSVR

CLK

RSENSE

DC/DC

CONV.

GATE

VF

CKTTX

CTTX1

TTX PROC

Vcc

CVCC

VPOS

REFERENCE

CTTX2

FTTX

Vss

VOLT.

REG.

VBAT

Agnd

Vbat

RTTX CAC ILTF RD IREF RLIM RTH

AGND

October 1999

1/22

STLC3055

DESCRIPTION (continued)

these applications is the integrated ringing gener-

ator.

sible CODEC input saturation due to Metering

pulse echo.

The control interface is a parallel type with open

drain output and 3.3V logic levels.

Constant current feed can be set from 20mA to

40mA. Off-hook detection threshold is program-

mable from 5mA to 9mA.

The device, developed in BCD100II technology

(100V process), operates in the extended tem-

perature range and integrates a thermal protec-

tion that sets the device in power down when Tj

exceeds 140°C.

The metering pulses are generated on chip start-

ing from two logic signals (0, 3.3V) one define the

metering pulse frequency and the other the me-

tering pulse duration. An on chip circuit then pro-

vides the proper shaping and filtering. Metering

pulse amplitude and shaping (rising and decay

time) can be programmed by external compo-

nents. A dedicated cancellation circuit avoid pos-

PIN CONNECTION

44

43

42

41

40

39

38

37

36

35

34

1

2

3

4

5

6

7

8

9

D0

D1

33

32

31

30

29

28

27

26

25

24

23

CSVR

ILTF

D2

RD

PD

RTH

RES

IREF

N.C.

RLIM

AGND

CVCC

VPOS

RSENSE

GATE

N.C.

DET

CKTTX

CTTX1

CTTX2

10

11

12

13

14

15

16

17

18

19

20

21

22

D97TL279A

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

V

V_pos

A/BGND

V_dig

Positive Supply Voltage

AGND to BGND

-0.4 to +17

-1 to +1

-0.4 to 5.5

150

V

Pin D0, D1, D2, DET, CKTTX

Max. junction Temperature

V

T_j

°C

V

(1)

V_btot

Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device

supply pins).

100

(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.

RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10)

2/22

STLC3055

OPERATING RANGE

Symbol

Parameter

Value

Unit

V

V_pos

A/BGND

V_dig

Positive Supply Voltage

AGND to BGND

5.5 to +15.8

-100 to +100

-0.25 to 5.25

-40 to +85

-74 max.

V

Pin D0, D1, D2, DET, CKTTX, PD

Ambient Operating Temperature Range

Self Generated Battery Voltage

V

T_op

°C

V

(1)

V_bat

(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.

RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10)

THERMAL DATA

Symbol

Parameter

Value

Unit

R_{th j-amb}

Thermal Resistance Junction to Ambient

Typ.

60

°C/W

PIN DESCRIPTION

N.

25

34

27

16

15

17

18

Name

VPOS

BGND

AGND

ZAC

Function

Positive supply input ranging from 5.5V to 15.8V.

Battery Ground, must be shorted with AGND.

Analog Ground, must be shorted with BGND.

AC impedance synthesis.

ZAC1

RS

RX buffer output, the AC impedance is connected from this node to ZAC.

Protection resistors image (the image resistor is connected from this node to ZAC).

ZB

Balance Network for 2 to 4 wire conversion (the balance impedance ZB is connected from this

node to AGND. ZA impedance is connected from this node to ZAC1).

20

14

TX

4 wire output port (TX output). The signal is referred to AGND. If connected to single supply

CODEC input it must be DC decoupled with proper capacitor.

RX

4 wire input port (RX input); 300K input impedance. This signal is referred to AGND. If

Ω

connected to single supply CODEC output it must be DC decoupled with proper capacitor.

19

32

41

37

28

CAC

ILTF

TIP

AC feedback input, AC/DC split capacitor (CAC).

Transversal line current image output.

2 wire port; TIP wire (Ia is the current sourced from this pin).

2 wire port; RING wire (Ib is the current sunk into this pin).

RING

RLIM

Constant current feed programming pin (via RLIM). RLIM should be connected close to this

pin and PCB layout should avoid noise injection on this pin.

30

29

43

RTH

IREF

CREV

Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin

and PCB layout should avoid noise injection on this pin.

Internal bias current setting pin. RREF should be connected close to this pin and PCB layout

should avoid noise injection on this pin.

Reverse polarity transition time control. One proper capacitor connected between this pin and

AGND is setting the reverse polarity transition time. This is the same transition time used to

shape the ”trapezoidal ringing” during ringing injection.

31

RD

DC feedback and ring trip input. RD should be connected close to this pin and PCB layout

should avoid noise injection on this pin.

3/22

STLC3055

PIN DESCRIPTION (continued)

N.

Name

Function

4

PD

Power Down input. Normally connected to CVCC (or to logic level high). Can be used to set

TIP and Ring terminals in open circuit setting PD=0 and D0=D1=0.

26

35

CVCC

VBAT

Internal positive voltage supply filter.

Regulated battery voltage self generated by the device via DC/DC converter. Must be shorted

to VBAT1.

23

21

22

GATE

VF

Driver for external Power MOS transistor.

Feedback input for DC/DC converter controller.

CLK

Power Switch Controller Clock (typ. 125KHz). From version marked STLC3055 A5, this pin

can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an

internal auto-oscillation is internally generated and it is used instead of the external clock.

When the CLK pin is connected to AGND, the GATE output is disabled.

24

RSENSE

Voltage input for current sensing. RSENSE should be connected close to this pin and VPOS

pin. The PCB layout should minimize the extra resistance introduced by the copper tracks.

1

2

D0

D1

Control Interface: input bit 0.

Control Interface: input bit 1.

3

D2

Control interface: input bit 2.

8

DET

CSVR

RTTX

Logic interface output of the supervision detector (active low).

Battery supply filter capacitor.

33

12

Metering pulse cancellation buffer output. TTX filter network should be connected to this point.

If not used should be left open.

13

10

11

9

FTTX

CTTX1

CTTX2

CKTTX

VBAT1

RES

Metering pulse buffer input this signal is sent to the line and used to perform TTX filtering.

Metering burst shaping external capacitor.

Metering pulse clock input (12 KHz or 16KHz square wave).

Frame connection. Must be shorted to VBAT.

Reserved, must be connected to AGND.

44

5

6, 7,36,

38,39,

40,42

NC

Not connected.

High ImpedanceFeeding (HI-Z)

Active

Ringing

FUNCTIONAL DESCRIPTION

The STLC3055 is a device specifically developed

for WLL and ISDN-TA applications.

Table 1 shows how to set the different SLIC oper-

ating modes.

It is based on a SLIC core, on purpose optimised

for these applications, with the addition of a

DC/DC converter controller to fulfil the WLL and

ISDN-TA design requirements.

Table 1. SLIC operating modes.

The SLIC performs the standard feeding, signal-

ling and transmissionfunctions.

It can be set in three different operating modes

via the D0, D1, D2 pins of the control logic inter-

face (0 to 3.3V logic levels). The loop status is

carried out on the DET pin (active low).

PD D0 D1 D2

Operating Mode

Power Down

0

1

0

1

0

1

0

X

0

1

0

1

H.I. Feeding (HI-Z)

Active Normal Polarity

Active Reverse Polarity

Active TTX injection (N.P.)

Active TTX injection (R.P.)

The DET pin is an open drain output to allow easy

interfacing with both 3.3V and 5V logic levels.

The four possible SLIC’s operating modes are:

0/1 Ring (D2 bit toggles @ fring)

Power Down

4/22

STLC3055

The DC/DC converter controller is driving an ex-

ternal power MOS transistor (P-Channel) in order

to generate the negative battery voltage needed

for device operation.

This operating mode is normally selected when

the telephone is in on-hookin order to monitor the

line status keeping the power consumption at the

minimum.

The DC/DC converter controller is synchronised

with an externalCLK (125KHZtyp.).

The output voltage in on-hook condition is equal

to the self generated battery voltage (-50V typ).

From version marked STLC3055 A5, it can be

synchronised to an internal clock generated when

the pin CLK is connected to CVCC. One sensing

resistor in series to Vpos supply allows to fix the

maximum allowed input peak current. This feature

is implemented in order to avoid overload on

Vpos supply in case of line transient (ex. ring trip

detection).

When off-hook occurs the DET becomes active

(low logic level).

The off-hook threshold in HI-Z mode is the same

value as programmed in ACTIVE mode.

The DC characteristic in HI-Z mode is just equal

to the self generated battery with 2x(1500W+Rp)

in series (see fig.1), where Rp is the external pro-

tection resistance.

The typical value is obtained for a sensing resis-

tor equal to 110mΩ that will guarantee an aver-

age current consumptionfrom Vpos < 700mA.

Figure 1. DC Characteristicin HI-Z Mode.

When in on-hook the self generated battery volt-

age is set to a predefinedvalue.

IL

This value can be adjusted via one externalresis-

tor (RF1) and it is typical -50V. When RING mode

is selectedthis value is increasedto -70V typ.

Vbat

2x(R1+Rp)

Slope: 2x(R1+Rp)

Once the line goes in off-hook condition, the

DC/DC converter automatically adjust the gener-

ated battery voltage in order to feed the line with

a fixed DC current (programmable via RLIM) opti-

mising in this way the power dissipation.

(R1=1500ohm)

VL

Vbat (-50V)

OPERATING MODES

Power Down

DC CHARACTERISTIC & SUPERVISION

AC CHARACTERISTICS

When this mode is selected the SLIC is switched

off and the TIP and RING pins are in high imped-

ance. Also the line detectors are disabled there-

fore the off-hookcondition cannot be detected.

This mode can be selected in emergency condi-

tion when it is necessary to cut any current deliv-

ered to the line.

The AC impedance shown at the 2W port

(TIP/RING) is the same as the DC one. The

TIP/RING AC impedance will be 2x(1500 + Rp)

Ω

or high impedance.

This mode is also forced by STLC3055 in case of

Active

thermal overload(Tj > 140°C).

DC CHARACTERISTICS & SUPERVISION

When this mode is selected the STLC3055 pro-

vides both DC feedingand AC transmission.

In this case the device goes back to the previous

status as soon as the junction temperature de-

crease under the hysteresis threshold.

The STLC3055 feeds the line with a constant cur-

rent fixed by RLIM (20mA to 40mA range). The

on-hook voltage is typically 40V allowing on-hook

transmission; the self generatedVbat is -50V typ.

AC CHARACTERISTICS

The 2W port is set in high impedance, the TX

output buffer is a low impedance output, no AC

transmissionis possible.

If the loop resistance is very high and the line

current cannot reach the programmed constant

current feed value, the STLC3055 behaves like a

40V voltage source with a series impedance

equal to the protection resistors 2xRp (typ.

High Impedance Feeding (HI-Z)

DC CHARACTERISTIC & SUPERVISION

2x41 ) plus the internal resistance. Fig. 2 shows

Ω

the typical DC characteristicin ACTIVE mode.

5/22

STLC3055

Figure 2. DC characteristicin ACTIVE mode

POLARITY REVERSAL

The D2 bit controls the line polarity, the transition

between the two polarities is performed in a ”soft”

way. This means that the TIP and RING wire ex-

change their polarities following a ramp transition

(see fig.3). The transition time is controlled by an

external capacitor CREV. This capacitor is also

setting the shape of the ringing trapezoidal wave-

form.

IL

Ilim

(20 to

40mA)

2Rp

When the control pins set battery reversal the line

polarity is reversed with a proper transition time

set via an external capacitor(CREV).

VL

10V

Figure 3. TIP/RING typical transition from

Direct to Reverse Polarity

Vbat (-50V)

The line status (on/off hook) is monitored by the

SLIC’s supervision circuit. The off-hook threshold

can be programmed via the external resistor R_TH

in the range from 5mA to 9mA.

GND

TIP

4V typ.

Independently on the programmed constant cur-

rent value, the TIP and RING buffers have a cur-

rent source capability limited to 70mA typ.

40V typ

ON-HOOK

Moreover the power available at Vbat is control-

led by the DC/DC converter that limits the peak

current drawn from the Vpos supply. The maxi-

mum allowed current peak is set by the R_SENSE

resistor and it is typically 900mApk.

dV/dT set

by CREV

RING

AC CHARACTERISTICS

The SLIC provides the standard SLIC transmis-

sion functions:

METERING PULSE INJECTION (TTX)

Input impedance synthesis: can be real or

complex and is set by a scaled (x50) external

ZAC impedance.

Transmit and receive: The AC signal present

on the 2W port (TIP/RING) is transferredto the

TX output with a -6dB gain and from the RX in-

put to the 2W port with a 0dB gain.

2 to 4 wire conversion: The balance imped-

ance can be real or complex, the proper can-

cellation is obtained by means of two external

impedanceZA and ZB.

The metering pulses circuit consist of a burst

shaping generator that gives a square wave

shaped and a low pass filter to reduce the har-

monic distortionof the output signal.

The metering pulse is obtained starting from two

logic signals:

CKTTX: is a square wave at the TTX fre-

quency (12 or 16KHz) and should be perma-

nently applied to the CKTTX pin or at least for

all the duration of the TTX pulse (including ris-

ing and decay phases).

D0: enable the TTX generation circuit and de-

fine the TTX pulse duration.

Once in Active mode (D1=1) the SLIC can oper-

ate in different states setting properly D0 and D2

control bits (see also Table 2).

Table 2. SLIC states in ACTIVE mode

This two signals are then processed by a dedi-

cated circuitry integrated on chip that generate

the metering pulse as an amplitude modulated

shaped squarewave (SQTTX) (see fig.4).

D0

0

D1

1

D2

0

Operating Mode

Active Normal Polarity

Both the amplitude and the envelope of the

squarewave (SQTTX) can be programmed by

means of external components. In particular the

amplitude is set by the two resistors RLV and the

0

1

Active Reverse Polarity

Active TTX injection (N.P.)

Active TTX injection (R.P.)

1

0

1

6/22

STLC3055

Figure 4. Metering pulse generation circuit.

Low Pass Filter

C1

-

OP1

+

CTTX1

RLV

RTTX

BURST

R2

FTTX

R1

SQTTX

CS

SHAPING

GENERATOR

CFL

C2

RLV

Sinusoidal wave

pulse metering

Required external components vs. filter order.

CTTX2

Order CFL R1

C!

R2

C2 THD

D0

1

2

3

X

13%

X

6%

3%

CKTTX

X

Square wave pulse metering

shaping by the capacitor CS.

The waveform so generated is then filtered and

injected on the line.

As already mentioned the metering pulse echo

cancellation is obtained by means of two external

components (RTTX and CTTX) that should match

the line impedance at the TTX frequency. This

simple network has a double effect:

The low pass filter can be obtained using the inte-

grated buffer OP1 connected between pin FTTX

(OP1 non inverting input) and RTTX (OP1 output)

(see fig.4) and implementing a ”Sallen and Key”

configuration.

Synthesise a low output impedance at the

TIP/RINGpins at the TTX frequency.

Cut the eventual TTX echo that will be trans-

ferred from the line to the TX output.

Dependingon the external components count it is

possible to build an optimised application de-

pending on the distortion level required. In par-

ticular harmonic distortion levels equal to 13%,

6% and 3% can be obtained respectively with

first, second and third order filters (see fig.4).

The circuit showed in the ”Application diagram” is

related to the simple first order filter.

Once the shaped and filtered signal is obtained at

RTTX buffer output it is injected on the TIP/RING

pins with a +6dB gain.

It should be noted that this is the nominal condi-

tion obtained in presence of ideal TTX echo can-

cellation (obtained via proper setting of RTTX and

CTTX). In addition the effective level obtained on

the line will depend on the line impedance, the

protection resistor value and the series switch

(SW1 or SW2) on resistance.

In the typical application (TTX line impedance

=200Ω , RP = 41Ω, SW1,2 on resistance = 9Ω

and ideal TTX echo cancellation) the metering

pulse level on the line will be 1.33 times the level

applied to the RTTX pin.

Ringing

When this mode is selected STLC3055 self gen-

erate an higher negative battery (-70V typ.) in or-

der to allow a balanced ringing signal of typically

65Vpeak.

In this condition both the DC and AC feedback

loop are disabled and the SLIC line drivers oper-

ate as voltagebuffers.

The ring waveform is obtained toggling the D2

control bit at the desired ring frequency.This bit in

fact controls the line polarity (0=direct; 1=re-

verse). As in the ACTIVE mode the line voltage

transition is performed with a ramp transition, ob-

taining in this way a trapezoidal balanced ring

waveform (see fig.5).

The shaping is defined by the CREV external

capacitor.

Selecting the proper capacitor value it is possible

to get differentcrest factor values.

The following table shows the crest factor values

7/22

STLC3055

Figure 5. TIP/RING typical ringing waveform

If for any reason the ringer load will be too high

the self generated battery will drop in order to

keep the power consumption to the fixed limit and

therefore also the ring voltage level will be re-

duced.

GND

2.5V typ.

TIP

In the typical application with R_SENSE= 110mΩ

the peak current from Vpos is limited to about

900mA, which correspond to an average current

of 700mA max. In this condition the STLC3055

can drive up to 3REN with a ring frequency

fr=25Hz (1REN = 1800Ω + 1.0µF, European

standard).

65V

typ.

dV/dT set

by CREV

In order to drive up to 5REN (1REN= 6930Ω +

8 F, US standard) it is necessary to modify the

µ

RING

2.5V typ.

VBAT

externalcomponentsas follows:

CREV = 15nF

RD = 2.2KΩ

obtained with a 20Hz and 25Hz ring frequency

and with 1REN. This value are valid either with

European or USA specification:

Power On Requirements

CREST

FACTOR

@20Hz

CREST

FACTOR

@25Hz

In order to avoid damage to the device when

Vpos is first applied it is recommended to keep all

the logic inputs to a low logic level (0V) until Vpos

is >5.5V.

CREV

22nF

27nF

33nF

1.2

1.26

1.32

1.25

1.33

In case this power up sequence cannot be guar-

anteed it’s recommended to connect a shottkydi-

ode (BAT46 or equivalent) between VBAT and

BGND see figure below.

Not significant (*)

(*) Distorsion already less than 10%.

Figure 6. Shottky diode connection

The ring trip detection is performed sensing the

variation of the AC line impedance from on hook

(relatively high) to off-hook (low). This particular

ring trip method allows to operate without DC off-

set superimposed on the ring signal and therefore

obtaining the maximum possible ring level on the

load starting from a given negative battery.

It should be noted that such a method is opti-

mised for operation on shortloop applications and

may not operateproperly in presenceof long loop

applications (> 500Ω ).

BGND

STLC3055

BAT46

VBAT

Once ring trip is detected,the DET output is acti-

vated (logic level low), at this point the card con-

troller or a simple logic circuit should stop the D2

toggling in order to effectively disconnect the ring

signal and then set the STLC3055 in the proper

operatingmode (normally ACTIVE).

RING LEVEL IN PRESENCE OF MORE TELE-

PHONE IN PARALLEL

As already mentioned above the maximum cur-

rent that can be drawn from the Vpos supply is

controlledand limited via the external RSENSE.

This will limit also the power available at the self

generatednegative battery.

8/22

STLC3055

Layout Recommendation

The AC input impedance shown by the SLIC at

the line terminals ”Zs” to which the return loss

measurement is referred. It can be real (typ.

600Ω) or complex.

The AC balance impedance, it is the equiva-

lent impedance of the line ”Zl” used for evalu-

ation of the trans-hybrid loss performances

(2/4 wire conversion). It is usually a complex

impedance.

The value of the two protection resistors Rp in

series with the line termination.

The line impedance at the TTX frequency

”Zlttx”.

A properly designed PCB layout is a basic issue

to guarantee a correct behaviour and good noise

performances.

Particular care must be taken on the ground con-

nection and in this case the star configuration al-

lows surely to avoid possible problems (see Appli-

cation Diagram Fig. 7).

The ground of the power supply (VPOS) has to

be connected to the center of the star, let’s call

this point PGND. This point should show a resis-

tance as low as possible, that means it should be

a ground plane.

Noise sources can be identified in not enough

good grounds, not enough low impedance sup-

plies and parasitic coupling between PCB tracks

and high impedance pins of the device.

In particular to avoid noise problems the layout

should prevent any coupling between the DC/DC

converter components and analog pins that are

referred to AGND (ex: RD, IREF, RTH, RLIM,

VF). As a first reccomendation the components

CV, L, D1, CVPOS, RSENSE should be kept as

close as possible to each other and isolated from

the other components.

The metering pulse level amplitude measured

at line termination ”V_LOTTX”. In case of low or-

der filtering, V_LOTTXrepresents the amplitude

(Vrms) of the fundamental frequency compo-

nent. (typ 12 or 16KHz).

Pulse metering envelope rise and decay time

constant ” ”.

τ

The slope of the ringing waveform” V / _T”.

∆

TR

The value of the constant current limit current

”Ilim”.

The value of the off-hook current threshold

”I_TH”.

The value of the ring trip rectified average

threshold current ”I_RTH”.

The value of the required self generated nega-

Additionalimprovements can be obtained:

decoupling the center of the star from the ana-

log ground of STLC3055 using small chokes.

adding a capacitor in the range of 100nF be-

tween VPOS and AGND in order to filter the

switch frequency on VPOS.

tive battery ”V_BATR

”

in ring mode (max value

is 70V). This value can be obtained from the

desired ring peak level + 5V.

External Components List

The value of the maximum current peak sunk

from Vpos ”IPK”.

In order to properly define the external compo-

nents value the following system parameters

have to be defined:

9/22

STLC3055

EXTERNAL COMPONENTS

Name

Function

Formula

RREF = 1.3/Ibias

Typ. Value

RREF

Bias setting current

26k 1%

Ω

Ibias = 50µA

CSVR

RD

Negative Battery Filter

CSVR = 1/(2π fp 1.8MΩ)

fp = 50Hz

1.5nF 10%

100VL

Ring Trip threshold setting

resistor

RD = 100/I_RTH

4.12k 1%

Ω

2K < RD < 5K

@ IRTH = 24mA

Ω

CAC

AC/DC split capacitance

22 F 20% 15VL

µ

@ RD = 4.12kΩ

RP

RS

Line protection resistor

Rp > 30Ω

41Ω 1%

Protection and series switches

resistance image

RS = 100 (Rp + 9Ω)

5kΩ @ Rp = 41Ω

ZAC

ZA (1)

ZB (1)

CCOMP

CH

Two wire AC impedance

ZAC = 50 (Zs - 2Rp - 18 )

25k 1%

@ Zs = 600

Ω

SLIC impedance balancing

network

ZA = 50 Zs

ZB = 50 Zl

30kΩ 1%

@ Zs = 600Ω

Line impedance balancing

network

30k 1%

Ω

@ Zl = 600

Ω

AC feedback loop compensation CCOMP = 1/(2 fo 100 (RP+9 ))

120pF 10% 10VL

@ Rp = 41

π

Ω

fo = 250kHz

Ω

Trans-Hybrid Loss frequency

compensation

CH = CCOMP

120pF 10% 10VL

RLIM

Current limiting programming

RLIM = 1300/Ilim

32.5k < RLIM < 65k

52.3k 1%

@ Ilim = 25mA

Ω

RTH

Off-hook threshold programming RTH = 260/I_TH

28.7k 1%

Ω

(ACTIVE mode)

27kΩ < RTH < 52kΩ

@I_TH= 9mA

CREV

RTTX (3)

CTTX (3)

RLV

Reverse polarity transition time

programming

CREV = (1/3750) ∆T/∆V_TR

)

22nF 10% 10V

@ 12V/ms

Pulse metering cancellation

resistor

RTTX = 50Re[(Zlttx+2Rp+18 )]

15k

Ω

@Zlttx = 200 real

Ω

Pulse metering cancellation

capacitor

CTTX = 1/{50 2 fttx[-lm(Zlttx)]}

100nF 10% 10V (2)

@ Zlttx = 200Ω real

π

Pulse metering level resistor

RLV = 63.3 10³α V_LOTTX

27kΩ 1%

@ V_LOTTX= 275mVrms

= (|Zlttx + 2Rp + 18 |/|Zlttx|)

α

Ω

CS

Pulse metering shaping

capacitor

CS = /(2 RLV)

100nF 10% 10V

= 6ms, RLV = 27.1k

τ

@

τ

Ω

CFL

Pulse metering filter capacitor

CFL = 2/(2 fttx RLV)

1nF 10% 10V

@fttx = 12kHz

π

RLV = 27k

Ω

RDD

CVCC

CVpos

Pull up resistors

100k

Ω

Internally supply filter capacitor

100nF 20% 10V

100 F(4)

Positive supply filter capacitor

with low impedance for switch

mode power supply

µ

CV

Battery supply filter capacitor

with low impedance for switch

mode power supply

100µF 20% 100V (5)

CVB

High frequency noise filter

470nF 20% 100VL

10/22

STLC3055

EXTERNAL COMPONENTS (continued)

Name

CRD (6)

Q1

Function

Formula

Typ. Value

100nF 10% 15VL

Possible choiches:

IRF9510 or IRF9520 or

IRF9120 or equivalent

High frequency noise filter

DC/DC converter switch P ch.

MOS transistor

RDS(ON)≤1.2Ω,VDS = -100V

Total gate charge=20nC max.

with VGS=4.5V and VDS=1V

ID>500mA

D1

RSENSE

L (8)

DC/DC converter series diode

Vr > 100V, t_RR50ns

SMBYW01-200

or equivalent

≤

DC/DC converter peak current

limiting

RSENSE = 100mV/I_PK

110mΩ

@I_PK= 900mA

DC/DC converter inductor

DC Resistance 0.1 (9)

L=125 H RFP1304PV

≤

Ω

µ

(Manuf.: All Inductive)

or SUMIDA CDRH125

or equivalent

CF1

RF1

RF2

DC/DC converter feedback loop

stability

220pF to 470pF (10)

Negative battery programming

level

250K <RF1<300K (7)

300kW 1%

@ V_BATR= -70V

Ω

Negative battery programming

level

9.1kΩ 1%

(1) In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|.

(2) In this case CTTX is justoperating as a DC decoupling capacitor (fp=100Hz).

(3) Defining ZTTX as the impedance of RTTX in series with CTTX, RTTX and CTTX can also be calculated from the following formula:

ZTTX=50*(Zlttx+2Rp+18 ).

Ω

(4) CVpos should be defined depending on the power supply current capability and maximum allowable ripple.

(5) For low ripple application use 2x47 F in parallel.

µ

(6) Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input).

(7) RF1 sets the self generated battery voltage in RING and ACTIVE(Il=0) mode as follows:

267k

280k

294kW

-49V

300k

Ω

V_BAT(ACTIVE)

V_BATR(RING)

-46V

-62V

-48V

-65V

-50V

-70V

-68V

VBATR should be defined considering the ring peak level required (Vringpeak=VBATR-6V typ.).

The above relation is valid provided that the Vpos power supply current capability and the RSENSE programming allow to source all the

current requested by the particular ringer load configuration.

(8) Core: MICROMETALS T50-26C IRON POWDER, AL-VALUE 61nH/N2

Current rating: 2A (50/60Hz)

Operating Temperature -25° to +60° Centigrades

Inductance: 14 H +/-15% at 1KHz, 1mA

µ

DC resistance of winding: MAX.100 mOhm

Code: RFY1303

Wire: UEW2, 0,60 mm

Turns: 50

Inductance (f=1KHz): >125 H

µ

(9) For high efficiency in HI-Z mode coil resistance @125kHz must be <3ohm

(10) Function of this capacitor is to introduce a zero at the resonance frequency for loop stability. In case some parasitic resistance are already

present in the loop (Coil, CVBAT, PCB layout), the presence of this capacitor can degrade the device noise performances; in this case CF1

should be removed being the loop stability already guaranteed by the parasitic resistance.

11/22

STLC3055

Figure 6. Application Diagram.

VPOS

CVPOS

CVCC

RSENSE

RX TX

RS

AGND BGND

CVCC

VPOS

RS

RSENSE

GATE

ZAC

Q1

L

CCOMP

D1

ZAC1

VBAT

ZAC

ZA

CVB

CF1

RF1

RF2

ZB

VF

CV

CH

ZB

VDD

CLK

TIP

CLK

RDD

RP

TIP

RING

DET

D0

STLC3055

CONTROL

INTERFACE

D0

CSVR

CREV

D1

D2

D1

D2

CREV

CSVR

TTX CLOCK

RLV

CKTTX

CTTX1

RTH

RLIM

IREF

CS

RLV

CTTX2

FTTX

RREF

RLIM

RTH

RTTX

CAC

ILTF

RD

CFL

RTTX

RD

CRD

D96TL275D

AGND

BGND

CTTX

CAC

SUPPLY GND

SUGGESTED GROUND LAY-OUT

PGND

Figure 7. Application Diagram without Metering Pulse Generation.

VPOS

CVPOS

CVCC

RSENSE

RX TX

RS

AGND BGND

CVCC

VPOS

RS

RSENSE

GATE

ZAC

Q1

L

CCOMP

D1

ZAC1

VBAT

ZAC

ZA

CVB

CF1

RF1

ZB

VF

CV

CH

VDD

RDD

ZB

RF2

CLK

TIP

CLK

RP

TIP

RING

STLC3055

RING

DET

D0

DET

D0

CONTROL

INTERFACE

CSVR

CREV

D1

D2

CREV

CSVR

TTX CLOCK

CKTTX

CTTX1

CTTX2

FTTX

RTH

RLIM

IREF

RREF

RLIM

RTH

RTTX

CAC

ILTF

RD

CRD

D98TL380A

AGND

BGND

CAC

SUPPLY GND

SUGGESTED GROUND LAY-OUT

PGND

12/22

STLC3055

ELECTRICAL CHARACTERISTICS

Test conditions: V_pos= 6.0V,AGND = BGND, Normal Polarity, T_amb= 25°C.

Externalcomponentsas listed in the ”Typical Values” column of EXTERNAL COMPONENTS Table.

Note: Testing of all parameter is performed at 25°C. Characterisation as well as design rules used allow

correlation of tested performances at other temperatures. All parameters listed here are met in the oper-

ating range: -40 to +85°C.

DC CHARACTERISTICS

Symbol

Parameter

Line voltage

Test Condition

Il = 0, HI-Z

(High impedance feeding)

Min.

Typ.

Max.

Unit

V_lohi

44

50

V

T

_amb= 0 to 85°C

V_lohi

Line voltage

Il = 0, HI-Z

(High impedance feeding)

42

48

V

T

_amb= -40 to 85°C

V_loa

Line voltage

Il = 0, ACTIVE

33

31

40

37

V

T

_amb= 0 to 85°C

Il = 0, ACTIVE

T

_amb= -40 to 85°C

Ilim

Lim. current programming range ACTIVE mode

20

40

10

mA

Ilima

Lim. current accuracy

ACTIVE mode.

-10

Rel. to programmed value

20mA to 40mA

Rfeed HI

Zrx

Feeding resistance

HI-Z (High Impedance feeding)

2.4

3.6

k

Ω

RX port input impedance

280

AC CHARACTERISTICS

L/T

T/L

Long. to transv.

(see Appendix for test circuit)

Rp = 41 , 1% tol.,

48

40

48

50

45

53

26

dB

Ω

ACTIVE N. P., R = 600 (*)

Ω

L

f = 300 to 3400Hz

Transv. to long.

(see Appendix for test circuit)

Rp = 41Ω, 1% tol.,

ACTIVE N. P., R = 600 (*)

Ω

L

f = 300 to 3400Hz

Transv. to long.

(see Appendix for test circuit)

Rp = 41 , 1% tol.,

Ω

ACTIVE N. P., R_L= 600Ω (*)

f = 1kHz

2WRL

THL

2W return loss

300 to 3400Hz,

22

30

dB

ACTIVE N. P., R = 600 (*)

Ω

L

Trans-hybrid loss

300 to 3400Hz,

20Log|VRX/VTX|,

ACTIVE N. P., R = 600 (*)

Ω

L

Ovl

2W overload level

at line terminals on ref. imped.

10

dBm

ACTIVE N. P., R = 600 (*)

Ω

L

TXoff

G24

TX output offset

ACTIVE N. P., R = 600 (*)

-150

-6.4

150

-5.6

mV

dB

Ω

L

Transmit gain abs.

0dBm @ 1020Hz,

ACTIVE N. P., R_L= 600Ω (*)

G42

Receive gain abs.

0dBm @ 1020Hz,

-0.4

0.4

dB

ACTIVE N. P., R = 600 (*)

Ω

L

G24f

TX gain variation vs. freq.

rel. 1020Hz; 0dBm,

300 to 3400Hz,

-0.12

0.12

ACTIVE N. P., R_L= 600Ω (*)

13/22

STLC3055

ELECTRICAL CHARACTERISTICS (continued)

Symbol

Parameter

Test Condition

rel. 1020Hz; 0dBm,

Min.

Typ.

Max.

Unit

G42f

RX gain variation vs. freq.

-0.12

0.12

dB

300 to 3400Hz,

ACTIVE N. P., R = 600 (*)

Ω

L

V2Wp

V4Wp

Idle channel noise at line

psophometric filtered

ACTIVE N. P., R_L= 600Ω (*)

-73

-68

-75

-68

-70

dBmp

T

_amb= 0 to +85°C

psophometric filtered

ACTIVE N. P., R = 600 (*)

Ω

L

T

_amb= -40 to +85°C

psophometric filtered

ACTIVE N. P., R = 600 (*)

Ω

L

T

_amb= 0 to +85°C

psophometric filtered

ACTIVE N. P., R_L= 600Ω (*)

T

_amb= -40 to +85°C

Thd

Total Harmonic Distortion

Metering pulse level on line

ACTIVE N. P., R = 600 (*)

-46

dB

Ω

L

VTTX

ACTIVE - TTX

200

250

125

mVrms

Zl = 200 fttx = 12kHz

Ω

CLKfreq

CLK operating range

-10%

10%

kHz

(*) R_L: Line Resistance

RING

Vring

Line voltage

RING D2 toggling @ fr = 25Hz

Load = 3REN;

Crest Factor = 1.25

45

44

49

48

Vrms

1REN = 1800 + 1.0 F

Ω

µ

T

_amb= 0 to +85°C

Vring

Line voltage

RING D2 toggling @ fr = 25Hz

Load = 3REN;

Crest Factor = 1.25

1REN = 1800Ω + 1.0µF

T

_amb= -40 to +85°C

DETECTORS

IOFFTHA

Off/hook current threshold

ACT. mode, RTH = 28.7k 1%

10.5

mA

Ω

(Prog. ITH = 9mA)

ROFTHA

IONTHA

RONTHA

IOFFTHI

ROFFTHI

IONTHI

Off/hook loop resistance

threshold

ACT. mode, RTH = 28.7k 1%

(Prog. ITH = 9mA)

3.4

6

k

Ω

On/hook current threshold

ACT. mode, RTH = 28.7kΩ 1%

(Prog. ITH = 9mA)

mA

On/hook loop resistance

threshold

ACT. mode, RTH = 28.7k 1%

8

k

Ω

(Prog. ITH = 9mA)

Off/hook current threshold

Hi Z mode, RTH = 28.7k 1%

10.5

mA

Ω

(Prog. ITH = 9mA)

Off/hook loop resistance

threshold

Hi Z mode, RTH = 28.7kΩ 1%

(Prog. ITH = 9mA)

800

6

On/hook current threshold

Hi Z mode, RTH = 28.7k 1%

mA

Ω

(Prog. ITH = 9mA)

RONTHI

On/hook loop resistance

threshold

Hi Z mode, RTH = 28.7k 1%

(Prog. ITH = 9mA)

8

k

Ω

14/22

STLC3055

ELECTRICAL CHARACTERISTICS (continued)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Irt

Ring Trip detector threshold

range

RING

20

50

mA

Irta

Ring Trip detector threshold

accuracy

-15

-1

15

%

Trtd

Td

Ring trip detection time

Dialling distortion

RING

TBD

160

ms

Ω

ACTIVE

1

Rlrt (1)

ThAl

Loop resistance

500

Tj for th. alarm activation

°C

(1) Rlrt = Maximum loop resistance (incl. telephone) for correct ring trip detection.

DIGITAL INTERFACE

INPUTS: D0, D1, D2, PD, CLK

OUTPUTS: DET

Vih

Vil

Iih

Iil

In put high voltage

Input low voltage

Input high current

Input low current

Output low voltage

2

V

0.8

10

-10

A

µ

10

Vol

Iol = 1mA

0.45

V

PSRR AND POWER CONSUMPTION

PSERRC

Power supply rejection Vpos to

2W port

Vripple = 100mVrms

50 to 4000Hz

26

36

dB

Ivpos

Vpos supply current @ ii = 0

HI-Z On-Hook

ACTIVE On-Hook,

RING (line open)

52

93

120

60

115

140

mA

Ipk

Peak current limiting accuracy

RING Off-Hook

RSENSE = 110m

-20%

950

+20%

mApk

Ω

15/22

STLC3055

APPENDIX A

STLC3055 Test Circuits

Referring to the application diagram shown in fig. 7 of the STLC3055 datasheet and using as external

components the Typ. Values specified in the ”External Components” Table (page 13) find below the

proper configurationfor each measurement.

All measurements requiring DC current termination should be performed using ”Wandel & Goltermann

DC Loop Holding Circuit GH-1” or equivalent.

Figure A1. 2W Return Loss

2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs)

W&G GH1

Zref

TX

TIP

600ohm

100µF

Vs

STLC3055

application

circuit

100mA

DC max

1Kohm

E

Zin = 100K

200 to 6kHz

100µF

1Kohm

RX

RING

Figure A2. THL Trans Hybrid Loss

THL = 20Log|Vrx/Vtx|

W&G GH1

TIP

TX

100µF

Vtx

STLC3055

application

circuit

100mA

DC max

600ohm

Zin = 100K

200 to 6kHz

100µF

RX

RING

Vrx

16/22

STLC3055

Figure A3. G24 Transmit Gain

G24 = 20Log|2Vtx/E|

W&G GH1

TIP

TX

100µF

Vtx

STLC3055

application

circuit

100mA

DC max

600ohm

E

Zin = 100K

200 to 6kHz

100 F

µ

RX

RING

Figure A4. G42 Receive Gain

G42 = 20Log|VI/Vrx|

W&G GH1

TIP

TX

100µF

STLC3055

application

circuit

100mA

Vl

DC max

600ohm

Zin = 100K

200 to 6kHz

100µF

RX

RING

Vrx

Figure A5. PSRRC Power supply rejection Vpos to 2W port

PSSRC = 20Log|Vn/Vl|

W&G GH1

TIP

TX

100 F

µ

STLC3055

application

circuit

100mA

Vl

DC max

600ohm

Zin = 100K

200 to 6kHz

100µF

RX

RING

VPOS

Vn

~

17/22

STLC3055

Figure A6. L/T Longitudinal to Transversal Conversion

L/T = 20Log|Vcm/Vl|

W&G GH1

300ohm

100µF

TIP

TX

µ

100 F

STLC3055

application

circuit

100mA

DC max

Vl

Impedance matching

better than 0.1%

Zin = 100K

200 to 6kHz

Vcm

100µF

RX

RING

300ohm

100µF

Figure A7. T/L Transversal to Longitudinal Conversion

T/L = 20Log|Vrx/Vcm|

W&G GH1

100µF

300ohm

TIP

TX

100µF

STLC3055

application

circuit

100mA

DC max

Impedancematching

better than 0.1%

Zin = 100K

200 to 6kHz

Vcm

600ohm

100µF

RX

RING

Vrx

300ohm

µ

100 F

Figure A8. VTTX Metering Pulse level on line

TIP

TX

STLC3055

application

circuit

Vlttx

200ohm

RX

RING

CKTTX

fttx (12 or 16kHz)

18/22

STLC3055

Figure A9. V2Wp and W4Wp: Idle channel psophometric noise at line and TX.

V2Wp = 20Log|Vl/0.774l|;V4Wp = 20Log|Vtx/0.774l|

W&G GH1

TIP

TX

100µF

Vtx

psophometric

filtered

STLC3055

application

circuit

100mA

DC max

600ohm

Zin = 100K

200 to 6kHz

Vl

psophometric

filtered

100 F

µ

RX

RING

APPENDIX B

STLC3055 Overvoltage Protection

Figure B1. Simplified configuration for indoor overvoltage protection

BGND

STLC3055

RP1

RP2

TIP

RING

VBAT

RP2: Fuse orPTC

Figure B2. Standard overvoltage protection configuration for K20 compliance

BGND

STLC3055

RP1

RP2

TIP

LCP1511

RING

VBAT

RP2: Fuse or PTC

19/22

STLC3055

APPENDIX C

TYPICAL STATE DIAGRAM FOR STLC3055 OPERATION

Figure C1.

Normally used for

On Hook

Transmission

Tj>Tth

PD=0, D0=D1=0

Active

On Hook

Power

Down

Ring Pause

D0=0, D1=1,

D2=0

Ring Burst

D0=1, D1=0, D2=0/1

Ringing

PD=1, D0=D1=0

On Hook Detection for T>Tref

HI-Z

Feeding

Ring Trip

Detection

Active

On Hook Condition

Off Hook

D0=0, D1=1,

D2=0

Off Hook Detection

Note: all state transitionsare under the microprocessor control.

20/22

STLC3055

21/22

STLC3055

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is

granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are

subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products

are not authorized for use as critical components in life support devices or systems without express writtenapproval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -

Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

http://www.st.com

22/22


型号：	STLC3055QTR
厂家：	ST
描述：	WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT WLL和ISDN- TA用户线接口电路综合业务数字网 WLL
文件：	总22页 (文件大小：155K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STLC3055QTR [STMICROELECTRONICS]

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