STLC3055N_09 [STMICROELECTRONICS]
WLL and ISDN-TA subscriber line interface circuit; WLL和ISDN -TA的用户线接口电路
| 型号： | STLC3055N_09 |
| 厂家： | 
ST |
| 描述： | WLL and ISDN-TA subscriber line interface circuit |
| 文件： | 总34页 (文件大小：325K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STLC3055N
WLL and ISDN-TA subscriber line interface circuit
Features
■ Monochip subscriber line interface circuit
(SLIC) optimised for WLL and VoIP
applications
■ Implement all key features of the BORSHT
LQFP44
function
■ Single supply (5.5 V to 12 V)
generate the negative battery by means of an
on chip DC/DC converter controller that drives an
external MOS switch.
■ Built in DC/DC converter controller
■ Soft battery reversal with programmable
transition time.
The battery level is properly adjusted depending
on the operating mode. A useful characteristic for
these applications is the integrated ringing
generator.
■ On-hook transmission.
■ Programmable off-hook detector threshold
■ Metering pulse generation and filter
■ Integrated ringing
The control interface is a parallel type with open
drain output and 3.3 V logic levels.
■ Integrated ring trip
The metering pulses are generated on chip
starting from two logic signals (0 and 3.3 V) one
define the metering pulse frequency and the other
the metering pulse duration. An on chip circuit
then provides the proper shaping and filtering.
Metering pulse amplitude and shaping (rising and
decay time) can be programmed by external
components. A dedicated cancellation circuit
avoid possible codec input saturation due to
metering pulse echo.
■ Parallel control interface (3.3 V logic level)
■ Programmable constant current feed
■ Surface mount package
■ Integrated thermal protection
■ Dual gain value option
■ BCD III S, 90 V technology
■ -40 to +85 °C operating range
Constant current feed can be set from 20 mA to
40 mA. Off-hook detection threshold is
programmable from 5 mA to 9 mA.
Description
The STLC3055N is a SLIC device specifically
designed for wireless local loop (WLL) and ISDN-
terminal adaptors (ISDN-TA) and VoIP
applications. One of the distinctive characteristic
of this device is the ability to operate with a single
supply voltage (from 5.5 V to 12 V) and self
The device, developed in BCD III S technology
(90 V process), operates in the extended
temperature range and integrates a thermal
protection that sets the device in power down
when Tj exceeds 140 °C.
Table 1.
Device summary
Order code
Package
Packing
E-STLC3055N (1)
LQFP44
Tray
1. ECOPACK® (see Section 10)
February 2009
Rev 11
1/34
www.st.com
1
Contents
STLC3055N
Contents
1
2
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
3.2
3.3
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
4.2
DC/DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.1
4.2.2
4.2.3
4.2.4
Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
High impedance feeding (HI-Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ringing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1
5.2
5.3
Layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
External components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7
8
9
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Typical state diagram for STLC3055N operation . . . . . . . . . . . . . . . . . 30
STLC3055Q vs STLC3055N compatibility. . . . . . . . . . . . . . . . . . . . . . . 31
9.1
9.2
9.3
Typical power consumption comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Hardware differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Parameter differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10
11
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2/34
STLC3055N
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SLIC operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Gain set in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SLIC states in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CREST factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
External components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
External components @gain set = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
External components @gain set = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power consumption differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Hardware differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Parameter differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3/34
List of figures
STLC3055N
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC characteristic in HI-Z mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC characteristic in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
TIP/RING typical transition from direct to reverse polarity . . . . . . . . . . . . . . . . . . . . . . . . . 12
Metering pulse generation circuit.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TIP/RING typical ringing waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application diagram with metering pulse generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Application diagram without metering pulse generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. 2W return loss 2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs) . . . . . . . . . . . . . . . . 26
Figure 11. THL trans hybrid loss THL = 20Log|Vrx/Vtx|. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12. G24 transmit gain G24 = 20Log|2Vtx/E| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. G42 receive gain G42 = 20Log|VI/Vrx| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. PSRRC power supply rejection Vpos to 2W port PSSRC = 20Log|Vn/Vl| . . . . . . . . . . . . . 27
Figure 15. L/T longitudinal to transversal conversion L/T = 20Log|Vcm/Vl|. . . . . . . . . . . . . . . . . . . . . 27
Figure 16. T/L transversal to longitudinal conversion T/L = 20Log|Vrx/Vcm|. . . . . . . . . . . . . . . . . . . . 28
Figure 17. VTTX metering pulse level on line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18. V2Wp and W4Wp: idle channel psophometric noise at line and TX.
V2Wp = 20Log|Vl/0.774l|; V4Wp = 20Log|Vtx/0.774l| . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19. Simplified configuration for indoor overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 20. Standard overvoltage protection configuration for K20 compliance . . . . . . . . . . . . . . . . . . 29
Figure 21. State diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 22. LQFP44 (10 x 10 x 1.4 mm) mechanical data and package dimensions . . . . . . . . . . . . . . 32
4/34
STLC3055N
Block diagram
1
Block diagram
Figure 1.
Block diagram
PD
D0
D1
D2
DET
GAIN
SETTING
INPUT LOGIC AND DECODER
OUTPUT LOGIC
BGND
TIP
Status and functions
TX
RX
LINE
OUTPUT
STAGE
SUPERVISION
DRIVER
ZAC1
ZAC
RING
AC PROC
RS
ZB
CREV
CSVR
DC PROC
CLK
RSENSE
GATE
VF
DC/DC
CONV.
CKTTX
CTTX1
CTTX2
FTTX
Vcc
TTX PROC
CVCC
VPOS
REFERENCE
Vss
VOLT.
REG.
VBAT
Agnd
Vbat
RTTX CAC ILTF RD IREF RLIM RTH
AGND
5/34
Pin description
STLC3055N
2
Pin description
Figure 2.
Pin connection (top view)
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
D0
D1
33
32
31
30
29
28
27
26
25
24
23
CSVR
ILTF
D2
RD
PD
RTH
GAIN SET
N.C.
IREF
RLIM
AGND
CVCC
VPOS
RSENSE
GATE
N.C.
DET
CKTTX
CTTX1
CTTX2
10
11
12
13
14
15
16
17
18
19
20
21
22
D00TL488-MOD
Table 2.
N°
Pin description
Pin
Function
1
2
3
4
D0
D1
D2
PD
Control Interface: input bit 0.
Control Interface: input bit 1.
Control interface: input bit 2.
Power down input. Normally connected to CVCC (or to logic level high).
Control gain interface: 0 Level Rxgain = 0dB Txgain = -6dB
1 Level Rxgain = +6dB Txgain = -12dB
5
Gain SET
6,7,36,
38,39,40,42
NC
Not connected.
Logic interface output of the supervision detector (active low).
8
9
DET
CKTTX Metering pulse clock input (12 KHz or 16KHz square wave).
10
11
CTTX1
CTTX2
Metering burst shaping external capacitor.
Metering burst shaping external capacitor.
Metering pulse cancellation buffer output. TTX filter network should be connected to
this point. If not used should be left open.
12
13
RTTX
FTTX
Metering pulse buffer input this signal is sent to the line and used to perform TTX
filtering.
4 wire input port (RX input). A 100 kΩ external resistor must be connected to AGND to
bias the input stage. This signal is referred to AGND. If connected to single supply
CODEC output it must be DC decoupled with proper capacitor.
14
RX
15
16
ZAC1
ZAC
RX buffer output, (the AC impedance is connected from this node to ZAC).
AC impedance synthesis.
6/34
STLC3055N
Pin description
Table 2.
N°
Pin description (continued)
Pin
Function
17
18
19
20
21
RS
ZB
Protection resistors image (the image resistor is connected from this node to ZAC).
Balance network for 2 to 4 wire conversion (the balance impedance ZB is connected
from this node to AGND. ZA impedance is connected from this node to ZAC1).
CAC
TX
AC feedback input, AC/DC split capacitor (CAC).
4 wire output port (TX output). The signal is referred to AGND. If connected to single
supply CODEC input it must be DC decoupled with proper capacitor.
VF
Feedback input for DC/DC converter controller.
Power switch controller clock (typ. 125 kHz). This pin can also be connected to CVCC
or AGND. When the CLK pin is connected to CVCC an auto-oscillation is internally
generated and it is used instead of the external clock. When the CLK pin is connected
to AGND, the GATE output is disabled.
22
CLK
23
24
GATE
Driver for external Power MOS transistor (P-channel).
Voltage input for current sensing. RSENSE should be connected close to this pin and
RSENSE VPOS pin. The PCB layout should minimize the extra resistance introduced by the
copper tracks.
25
26
27
VPOS
CVCC
AGND
Positive supply
Internal positive voltage supply filter.
Analog ground, must be shorted with BGND.
Constant current feed programming pin (via RLIM). RLIM should be connected close to
this pin and AGND pin to avoid noise injection.
28
29
30
31
RLIM
IREF
RTH
RD
Internal bias current setting pin. RREF should be connected close to this pin and
AGND pin to avoid noise injection.
Off-hook threshold programming pin (via RTH). RTH should be connected close to this
pin and AGND pin to avoid noise injection.
DC feedback and ring trip input. RD should be connected close to this pin and AGND
pin to avoid noise injection.
32
33
34
ILTF
Transversal line current image output.
Battery supply filter capacitor.
CSVR
BGND
Battery ground, must be shorted with AGND.
Regulated battery voltage self generated by the device via DC/DC converter. Must be
shorted to VBAT1.
35
VBAT
37
41
RING
TIP
2 wire port; RING wire (Ib is the current sunk into this pin).
2 wire port; TIP wire (Ia is the current sourced from this pin).
Reverse polarity transition time control. One proper capacitor connected between this
pin and AGND is setting the reverse polarity transition time. This is the same transition
time used to shape the "trapezoidal ringing" during ringing injection.
43
44
CREV
VBAT1
Frame connection. Must be shorted to VBAT.
7/34
Electrical specification
STLC3055N
3
Electrical specification
3.1
Absolute maximum rating
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
Vpos
Positive supply voltage
-0.4 to +13
-1 to +1
-0.4 to 5.5
150
V
V
A/BGND AGND to BGND
Vdig
Tj
Pin D0, D1, D2, DET, CKTTX
V
Max. junction temperature
°C
Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device
supply pins).
(1)
Vbtot
90
V
Human body model
1750
500
V
V
ESD
RATING
Charged device model
1. Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.
RF1 and RF2 shall be selected in order to fulfil the a.m limits (see Table 10: External components on
page 17).
3.2
Operating range
Table 4.
Symbol
Operating range
Parameter
Value
Unit
Vpos
Positive supply voltage
5.5 to +12
-100 to +100
-0.25 to 5.25
-40 to +85
-74 max.
V
mV
V
A/BGND AGND to BGND
Vdig
Top
Pin D0, D1, D2, DET, CKTTX, PD
Ambient operating temperature range
Self generated battery voltage
°C
V
(1)
Vbat
1. Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.
RF1 and RF2 shall be selected in order to fulfill the a.m limits (see Table 10: External components on
page 17).
3.3
Thermal data
Table 5.
Symbol
Thermal data
Parameter
Value
Unit
Rth j-amb Thermal resistance junction to ambient
Typ.
60
°C/W
8/34
STLC3055N
Functional description
4
Functional description
The STLC3055N is a device specifically developed for WLL VoIP and ISDN-TA applications.
It is based on a SLIC core, on purpose optimised for these applications, with the addition of
a DC/DC converter controller to fulfil the WLL and ISDN-TA design requirements.
The SLIC performs the standard feeding, signalling and transmission functions.
It can be set in four different operating modes via the D0, D1, D2 pins of the control logic
interface (0 to 3.3 V logic levels). The loop status is carried out on the DET pin (active low).
The DET pin is an open drain output to allow easy interfacing with both 3.3 V and 5 V logic
levels.
The four possible SLIC’s operating modes are:
●
●
●
●
Power down
High impedance feeding (HI-Z)
Active
Ringing
Table 6 shows how to set the different SLIC operating modes.
Table 6.
PD
SLIC operating modes.
D0
D1
D2
Operating mode
0
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
1
1
0
X
X
Power down
H.I. feeding (HI-Z)
Active normal polarity
Active reverse polarity
0
1
0
Active TTX injection (N.P.)
Active TTX injection (R.P.)
Ring (D2 bit toggles @ fring)
1
0/1
4.1
DC/DC converter
The DC/DC converter controller is driving an external power MOS transistor (P-channel) in
order to generate the negative battery voltage needed for device operation.
The DC/DC converter controller is synchronised with an external CLK (125 kHz typ.) or with
an internal clock generated when the pin CLK is connected to CVCC. One sensing resistor
in series to Vpos supply allows to fix the maximum allowed input peak current. This feature
is implemented in order to avoid overload on Vpos supply in case of line transient (ex. ring
trip detection).
The typical value is obtained for a sensing resistor equal to 110 mΩ that will guarantee an
average current consumption from Vpos < 700 mA. When in on-hook the self generated
battery voltage is set to a predefined value.
This value can be adjusted via one external resistor (RF1) and it is typical -50 V. When
RING mode is selected this value is increased to -70 V typ.
9/34
Functional description
STLC3055N
Once the line goes in off-hook condition, the DC/DC converter automatically adjust the
generated battery voltage in order to feed the line with a fixed DC current (programmable via
RLIM) optimising in this way the power dissipation.
4.2
Operating modes
4.2.1
Power down
When this mode is selected the SLIC is switched off and the TIP and RING pins are in high
impedance. Also the line detectors are disabled therefore the off-hook condition cannot be
detected.
This mode can be selected in emergency condition when it is necessary to cut any current
delivered to the line.
This mode is also forced by STLC3055N in case of thermal overload (Tj > 140 °C).
In this case the device goes back to the previous status as soon as the junction temperature
decrease under the hysteresis threshold.
No AC transmission is possible in this mode.
4.2.2
High impedance feeding (HI-Z)
This operating mode is normally selected when the telephone is in on-hook in order to
monitor the line status keeping the power consumption at the minimum.
The output voltage in on-hook condition is equal to the self generated battery voltage (-50 V
typ).
When off-hook occurs the DET becomes active (low logic level).
The off-hook threshold in HI-Z mode is the same value as programmed in ACTIVE mode.
The DC characteristic in HI-Z mode is just equal to the self generated battery with
2x(1600 Ω+Rp) in series (see Figure 3), where Rp is the external protection resistance.
No AC transmission is possible in this mode.
Figure 3.
DC characteristic in HI-Z mode.
IL
Vbat
2x(R1+Rp)
Slope: 2x(R1+Rp)
(R1=1600ohm)
VL
Vbat (-50V)
4.2.3
Active
DC characteristics and supervision
When this mode is selected the STLC3055N provides both DC feeding and AC
transmission.
10/34
STLC3055N
Functional description
The STLC3055N feeds the line with a constant current fixed by RLIM (20 mA to 40 mA
range). The on-hook voltage is typically 40 V allowing on-hook transmission; the self
generated Vbat is -50 V typ.
If the loop resistance is very high and the line current cannot reach the programmed
constant current feed value, the STLC3055N behaves like a 40 V voltage source with a
series impedance equal to the protection resistors 2xRp (typ. 2 x 50 Ω). Figure 4 shows the
typical DC characteristic in Active mode.
Figure 4.
DC characteristic in active mode
IL
Ilim
(20 to
40mA)
2Rp
VL
Vbat (-50V)
10V
The line status (on/off-hook) is monitored by the SLIC’s supervision circuit. The off-hook
threshold can be programmed via the external resistor RTH in the range from 5 mA to 9 mA.
Independently on the programmed constant current value, the TIP and RING buffers have a
current source capability limited to 80 mA typ. Moreover the power available at Vbat is
controlled by the DC/DC converter that limits the peak current drawn from the Vpos supply.
The maximum allowed current peak is set by RSENSE resistor.
AC characteristics
The SLIC provides the standard SLIC transmission functions:
Once in active mode the SLIC can operate with two different Tx, Rx Gain. Setting properly
by the gain set control bit (see Table 7).
Table 7.
Gain set
Gain set in active mode
4 to 2 wire gain
2 to 4 wire gain
Impedance synthesis scale factor
0
1
0 dB
-6 dB
x 50
x 25
+6 dB
-12 dB
●
●
Input impedance synthesis: can be real or complex and is set by a scaled (x 50 or
x 25) external ZAC impedance.
Transmit and receive: The AC signal present on the 2W port (TIP and RING pins) is
transferred to the TX output with a -6 dB or -12 dB gain and from the RX input to the
2W port with a 0 dB or +6 dB gain.
●
2 to 4 wire conversion: The balance impedance can be real or complex, the proper
cancellation is obtained by means of two external impedance ZA and ZB
Once in Active mode (D1=1) the SLIC can operate in different states setting properly D0 and
D2 control bits (see also Table 8).
11/34
Functional description
STLC3055N
Table 8.
D0
SLIC states in active mode
D1
D2
Operating Mode
0
0
1
1
1
1
1
1
0
1
0
1
Active normal polarity
Active reverse polarity
Active TTX injection (normal polarity)
Active TTX injection (reverse polarity)
Polarity reversal
The D2 bit controls the line polarity, the transition between the two polarities is performed in
a "soft" way. This means that the TIP and RING wire exchange their polarities following a
ramp transition (see Figure 5). The transition time is controlled by an external capacitor
CREV. This capacitor is also setting the shape of the ringing trapezoidal waveform. When
the control pins set battery reversal the line polarity is reversed with a proper transition time
set via an external capacitor (CREV).
Figure 5.
TIP/RING typical transition from direct to reverse polarity
GND
TIP
4V typ.
40V typ
ON-HOOK
dV/dT set
by CREV
RING
Metering pulse injection (Ttx)
The metering pulses circuit consists of a burst shaping generator that gives a square wave
shaped and a low pass filter to reduce the harmonic distortion of the output signal.
The metering pulse is obtained starting from two logic signals:
●
CKTTX: is a square wave at the TTX frequency (12 or 16 kHz) and should be
permanently applied to the CKTTX pin or at least for all the duration of the TTX pulse
(including rising and decay phases).
●
D0: enable the TTX generation circuit and define the TTX pulse duration.
These two signals are processed by a dedicated circuitry integrated on chip that generate
the metering pulse as an amplitude modulated shaped squarewave (SQTTX)
(see Figure 6).
Both the amplitude and the envelope of the squarewave (SQTTX) can be programmed by
means of external components. In particular the amplitude is set by the two resistors RLV
and the shaping by the capacitor CS.
12/34
STLC3055N
Functional description
Figure 6.
Metering pulse generation circuit.
Low Pass Filter
C1
-
CTTX1
RLV
RTTX
BURST
R2
FTTX
OP1
R1
SQTTX
CS
+
SHAPING
GENERATOR
CFL
C2
RLV
Sinusoidal wave
pulse metering
Required external components vs. filter order.
CTTX2
Order
CFL
R1
C1
R2
C2
THD
D0
1
2
3
X
13%
6%
CKTTX
X
X
X
X
X
X
X
X
X
3%
Square wave pulse metering
The waveform so generated is then filtered and injected on the line.
The low pass filter can be obtained using the integrated buffer OP1 connected between pin
FTTX (OP1 non inverting input) and RTTX (OP1 output) (see Figure 6) and implementing a
"Sallen and Key" configuration. Depending on the external components count it is possible
to build an optimised application depending on the distortion level required. In particular
harmonic distortion levels equal to 13 %, 6 % and 3 % can be obtained respectively with
first, second and third order filters (see Figure 6).
The circuit showed in Figure 8: Application diagram with metering pulse generation. on
page 20 is related to the simple first order filter.
Once the shaped and filtered signal is obtained at RTTX buffer output it is injected on the
TIP/RING pins with a +6 dB gain or +12 dB gain.
It should be noted that this is the nominal condition obtained in presence of ideal TTX echo
cancellation (obtained via proper setting of RTTX and CTTX).
In addition, the effective level obtained on the line will depend on the line impedance and the
protection resistors value. In the typical application (TTX line impedance =200 Ω, RP = 50 Ω,
and ideal TTX echo cancellation) the metering pulse level on the line will be 1.33 or 2.66
times the level applied to the RTTX pin.
As already mentioned the metering pulse echo cancellation is obtained by means of two
external components (RTTX and CTTX) that should match the line impedance at the TTX
frequency. This simple network has a double effect:
●
Synthesize a low output impedance at the TIP/RING pins at the TTX frequency.
Cut the eventual TTX echo that will be transferred from the line to the TX output.
●
4.2.4
Ringing
When this mode is selected STLC3055N self generate an higher negative battery (-70 V
typ.) in order to allow a balanced ringing signal of typically 65 Vpeak.
In this condition both the DC and AC feedback are disabled and the SLIC line drivers
operate as voltage buffers. The ring waveform is obtained toggling the D2 control bit at the
13/34
Functional description
STLC3055N
desired ring frequency. This bit in fact controls the line polarity (0=direct; 1=reverse). As in
the Active mode the line voltage transition is performed with a ramp transition, obtaining in
this way a trapezoidal balanced ring waveform (see Figure 7). The shaping is defined by the
CREV external capacitor.
Selecting the proper capacitor value it is possible to get different CREST factor values.
The following table shows the CREST factor values obtained with a 20 Hz and 25 Hz ring
frequency and with 1REN. These value are valid either with European or USA specification.
Figure 7.
TIP/RING typical ringing waveform
GND
TIP
2.5V typ.
65V
typ.
dV/dT set
by CREV
RING
2.5V typ.
VBAT
Table 9.
CREST factor
CREV
CREST factor @20 Hz
CREST factor @25 Hz
22nF
27nF
33nF
1.2
1.26
1.32
1.25
1.33
(1)
Not significant
1. Distortion already less than 10%.
The ring trip detection is performed sensing the variation of the AC line impedance from on-
hook (relatively high) to off-hook (low). This particular ring trip method allows to operate
without DC offset superimposed on the ring signal and therefore obtaining the maximum
possible ring level on the load starting from a given negative battery. It should be noted that
such a method is optimised for operation on short loop applications and may not operate
properly in presence of long loop applications (> 500 Ω). Once ring trip is detected, the DET
output is activated (logic level low), at this point the card controller or a simple logic circuit
should stop the D2 toggling in order to effectively disconnect the ring signal and then set the
STLC3055N in the proper operating mode (normally Active).
Ring level in presence of more telephone in parallel
As already mentioned above the maximum current that can be drawn from the Vpos supply
is controlled and limited via the external R
the self generated negative battery.
. This will limit also the power available at
SENSE
If for any reason the ringer load will be too low the self generated battery will drop in order to
keep the power consumption to the fixed limit and therefore also the ring voltage level will be
reduced.
In the typical application with RSENSE = 110 mΩ the peak current from Vpos is limited to
about 900 mA, which correspond to an average current of 700 mA max. In this condition the
STLC3055N can drive up to 3REN with a ring frequency fr=25 Hz (1REN = 1800 Ω + 1.0 µF,
European standard).
14/34
STLC3055N
Functional description
In order to drive up to 5REN (1REN= 6930 Ω + 8 µF, US standard) it is necessary to modify
the external components as follows:
CREV = 15 nF
RD = 2.2 kΩ
Rsense = 100 mΩ .
15/34
Application information
STLC3055N
5
Application information
5.1
Layout recommendation
A properly designed PCB layout is a basic issue to guarantee a correct behavior and good
noise performances. Noise sources can be identified in not enough good grounds, not
enough low impedance supplies and parasitic coupling between PCB tracks and high
impedance pins of the device.
Particular care must be taken on the ground connection and in this case the star
configuration allows surely to avoid possible problems (see Figure 8 on page 20 and
Figure 9 on page 21).
The ground of the power supply (VPOS) has to be connected to the center of the star, let’s
call this point Supply GND. This point should show a resistance as low as possible, that
means it should be a ground plane.
In particular to avoid noise problems the layout should prevent any coupling between the
DC/DC converter components that are referred to PGND (CVPOS, CD, L) and analog pins
that are referred to AGND (ex: RD, IREF, RTH, RLIM, VF). AGND and BGND must be
shorter together. The GND connection of protection components have to be connected to
the Supply GDND.
As a first recommendation the components CV, L, D1, CVPOS, RSENSE should be kept as
close as possible to each other and isolated from the other components.
Additional improvements can be obtained:
●
●
decoupling the center of the star from the analog ground of STLC3055N using small
chokes.
adding a capacitor in the range of 100 nF between VPOS and AGND in order to filter
the switch frequency on VPOS.
16/34
STLC3055N
Application information
5.2
External components list
In order to properly define the external components value the following system parameters
have to be defined:
●
The AC input impedance shown by the SLIC at the line terminals "Zs" to which the
return loss measurement is referred. It can be real (typ. 600 Ω) or complex.
●
The AC balance impedance, it is the equivalent impedance of the line "Zl" used for
evaluation of the trans-hybrid loss performances (2/4 wire conversion). It is usually a
complex impedance.
●
●
The value of the two protection resistors Rp in series with the line termination. The line
impedance at the TTX frequency "Zlttx".
The metering pulse level amplitude measured at line termination "VLOTTX". In case of
low order filtering, VLOTTX represents the amplitude (Vrms) of the fundamental
frequency component. (typ 12 or 16 kHz).
●
●
●
●
●
●
Pulse metering envelope rise and decay time constant "τ".
The slope of the ringing waveform "ΔVTR/ΔT ".
The value of the constant current limit current "Ilim".
The value of the off-hook current threshold "ITH".
The value of the ring trip rectified average threshold current "IRTH".
The value of the required self generated negative battery "VBATR" in ring mode (max
value is 70 V). This value can be obtained from the desired ring peak level +5 V.
●
The value of the maximum current peak sunk from Vpos "IPK".
Table 10. External components
Name
Function
Formula
Typ. value
RRX
Rx input bias resistor
100 kΩ 5%
RREF = 1.3/Ibias
RREF Bias setting current
CSVR Negative battery filter
26 kΩ 1%
Ibias = 50 μA
CSVR = 1/(2π ⋅ fp ⋅ 1.8 MΩ)
fp = 50 Hz
1.5 nF 10%
100 V
RD = 100/IRTH
4.12 kΩ 1%
@ IRTH = 24 mA
Ring Trip threshold setting
resistor
RD
2 kΩ < RD < 5 kΩ
22 μF 20% 15 V
@ RD = 4.12 kΩ
CAC
RP
AC/DC split capacitance
Line protection resistor
Rp > 30 Ω
50 Ω 1%
RLIM = 1300/Ilim
52.3 kΩ 1%
@ Ilim = 25 mA
RLIM
Current limiting programming
32.5kΩ < RLIM < 65kΩ
Off-hook threshold programming RTH = 290/ITH
32.4 kΩ 1%
@ITH = 9 mA
RTH
(ACTIVE mode)
27 kΩ < RTH < 52 kΩ
22 nF 10% 10 V
@ 12 V/ms
Reverse polarity transition time
programming
CREV
RDD
CREV = ((1/3750) · ΔT/ΔVTR
)
Pull up resistors
100 kΩ
CVCC Internally supply filter capacitor
100 nF 20% 10 V
17/34
Application information
STLC3055N
Table 10. External components (continued)
Name
Function
Formula
Typ. value
Positive supply filter capacitor
CVpos with low impedance for switch
mode power supply
(1)
100 μF
Battery supply filter capacitor
with low impedance for switch
mode power supply
(2)
CV
100 μF 20% 100 V
CVB
High frequency noise filter
High frequency noise filter
470 nF 20% 100 V
100 nF 10% 15 V
(3)
CRD
RDS(ON) ≤ 1.2 Ω,VDS = -100 V
Total gate charge = 20 nC max.
with VGS = 4.5 V and VDS = 1 V
ID > 500 mA
Possible choiches:
IRF9510 or IRF9520 or
IRF9120 or equivalent
DC/DC converter switch P-
channel MOS transistor
Q1
SMBYW01-200
or equivalent
D1
DC/DC converter series diode
Vr > 100 V, tRR ≤ 50 ns
110 mΩ
@IPK = 900 mA
DC/DC converter peak current
limiting
RSENSE
RSENSE = 100 mV/IPK
300 kΩ 1%
@ VBATR = -70 V
Negative battery programming
level
(4)
RF1
RF2
L
250 kΩ < RF1 < 300 kΩ
Negative battery programming
9.1 kΩ 1 %
leve
l
L=100 μH
SUMIDA CDRH125 or equivalent
(5)
DC/DC converter inductor
DC resistance ≤ 0.1 Ω
1. CVpos should be defined depending on the power supply current capability and maximum allowable ripple.
2. For low ripple application use 2 x 47 μF in parallel.
3. Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input).
4
RF1 sets the self generated battery voltage in Ring and Active (Il=0) mode as follows:
267 kΩ
280 kΩ
294 kΩ
300 kΩ
VBAT(ACTIVE)
VBATR(RING)
-46 V
-62 V
-48 V
-65 V
-49 V
-68 V
-50 V
-70 V
V
BATR should be defined considering the ring peak level required (Vringpeak=VBATR-6 V typ.). The above relation is valid
provided that the Vpos power supply current capability and the RSENSE programming allow to source all the current
requested by the particular ringer load configuration.
5
For high efficiency in HI-Z mode coil resistance @125 kHz must be < 3 Ω
Table 11. External components @gain set = 0
Name
Function
Formula
RS = 50 ⋅ (2Rp)
Typ. value
RS
Protection resistance image
Two wire AC impedance
5 kΩ @ Rp = 50 Ω
ZAC
ZAC = 50 ⋅ (Zs - 2Rp)
ZA = 50 ⋅ Zs
25 kΩ 1% @ Zs = 600 Ω
SLIC impedance balancing
network
(1)
ZA
30 kΩ 1% @ Zs = 600 Ω
18/34
STLC3055N
Application information
Table 11. External components @gain set = 0 (continued)
Name
Function
Formula
Typ. value
Line impedance balancing
network
(1)
ZB
ZB = 50 ⋅ Zl
30 kΩ 1% @ Zl = 600 Ω
fo = 250 kHz
CCOMP AC feedback loop compensation
120 pF 10% 10 V @ Rp = 50 Ω
120 pF 10% 10 V
CCOMP = 1/(2π⋅fo⋅100⋅(RP))
Trans-Hybrid Loss frequency
CH
CH = CCOMP
compensation
Pulse metering cancellation
resistor
(2)
(2)
RTTX
CTTX
RTTX = 50Re (Zlttx+2Rp)
15 kΩ @Zlttx = 200 Ω real
(3)
100nF 10% 10V
Pulse metering cancellation
capacitor
CTTX = 1/{50⋅2π⋅fttx[-
lm(Zlttx)]}
@ Zlttx = 200Ω real
RLV = 63.3·103··α·VLOTTX
α = (|Zlttx + 2Rp|/|Zlttx|)
RLV
CS
Pulse metering level resistor
16.2 kΩ @ VLOTTX = 170mVrms
100 nF 10% 10V
Pulse metering shaping
capacitor
CS = τ/(2⋅RLV)
@ τ = 3.2 ms, RLV = 16.2 kΩ
1.5 nF 10% 10 V
CFL
Pulse metering filter capacitor
CFL = 2/(2π⋅fttx⋅RLV)
@fttx = 12 kHz RLV = 16.2 kΩ
1. In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|.
2. Defining ZTTX as the impedance of RTTX in series with CTTX, RTTX and CTTX can also be calculated from the following
formula:
ZTTX=50*(Zlttx+2Rp).
3. In this case CTTX is just operating as a DC decoupling capacitor (fp=100 Hz).
Table 12. External components @gain set = 1
Name
Function
Formula
RS = 25 ⋅ (2Rp)
Typ. value
RS
Protection resistance image
Two wire AC impedance
2.55 kΩ @ Rp = 50 Ω
ZAC
ZAC = 25 ⋅ (Zs - 2Rp)
ZA = 25 ⋅ Zs
12.5 kΩ 1% @ Zs = 600 Ω
SLIC impedance balancing
network
(1)
ZA
15 kΩ 1% @ Zs = 600 Ω
15 kΩ 1% @ ZI = 600 Ω
220 pF 10% 10VL @ Rp = 50 Ω
220 pF 10% 10 V
Line impedance balancing
network
(1)
ZB
ZB = 25 ⋅ Zl
fo = 250kHz
CCOMP AC feedback loop compensation
CCOMP = 2/(2π⋅fo⋅100⋅(RP))
Trans-Hybrid Loss frequency
compensation
CH
CH = CCOMP
Pulse metering cancellation
resistor
(2)
(2)
RTTX
CTTX
RTTX = 25Re (Zlttx+2Rp)
7.5 kΩ @Zlttx = 200 Ω real
(3)
100 nF 10% 10 V
Pulse metering cancellation
capacitor
CTTX = 1/25⋅2π⋅fttx⋅[-lm(Zlttx)]
@ Zlttx = 200 Ω real
RLV = 31.7·103··α·VLOTTX
α = (|Zlttx + 2Rp|/|Zlttx|)
RLV
Pulse metering level resistor
16.2 kΩ @ VLOTTX = 340 mVrms
19/34
Application information
STLC3055N
Table 12. External components @gain set = 1 (continued)
Name
Function
Formula
Typ. value
100 nF 10% 10V
Pulse metering shaping
capacitor
CS
CS = τ/(2⋅RLV)
@ τ = 3.2 ms, RLV = 16.2 kΩ
1.5nF 10% 10 V
CFL
Pulse metering filter capacitor
CFL = 2/(2π⋅fttx⋅RLV)
@fttx = 12 kHz RLV = 16.2 kΩ
1. In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|.
2. Defining ZTTX as the impedance of RTTX in series with CTTX, RTTX and CTTX can also be calculated from the following
formula:
ZTTX=50*(Zlttx+2Rp).
3. In this case CTTX is just operating as a DC decoupling capacitor (fp=100 Hz).
5.3
Application diagram
Figure 8.
Application diagram with metering pulse generation.
VPOS
CVCC
CVPOS
RSENSE
RX TX
RRX
RX TX AGND BGND
RS
CVCC
VPOS
RS
RSENSE
GATE
Q1
ZAC
P-ch
CCOMP
D1
ZAC1
VBAT
ZAC
ZA
CVB
RF1
RF2
ZB
L
VF
CV
CH
VDD
ZB
CLK
TIP
CLK
GAIN SET
RDD
RP
RP
TIP
STLC3055N
RING
RING
DET
D0
DET
D0
CONTROL
INTERFACE
CSVR
CREV
D1
D1
D2
D2
CREV
CSVR
PD
PD
TTX CLOCK
CKTTX
RTH
RLIM
IREF
RLV
RLV
CTTX1
CS
CTTX2
FTTX
RREF
RLIM
RTH
RTTX
CAC
ILTF
RD
CFL
RTTX
RD
CRD
D00TL489A
AGND
BGND
CTTX
CAC
SYSTEM GND
SUGGESTED GROUND LAY-OUT
PGND
20/34
STLC3055N
Figure 9.
Application information
Application diagram without metering pulse generation
VPOS
CVCC
CVPOS
RSENSE
RX TX
RRX
RX TX AGND BGND
RS
CVCC
VPOS
RS
RSENSE
GATE
Q1
ZAC
P-ch
D1
CCOMP
ZAC1
VBAT
ZAC
ZA
CVB
RF1
ZB
L
VF
CV
CH
VDD
RDD
ZB
RF2
CLK
TIP
CLK
GAIN SET
RP
RP
TIP
STLC3055N
RING
RING
DET
D0
DET
D0
CONTROL
INTERFACE
CSVR
CREV
D1
D1
D2
D2
CREV
CSVR
PD
PD
CKTTX
CTTX1
CTTX2
FTTX
RTH
RLIM
IREF
RREF
RLIM
RTH
RTTX
CAC
ILTF
RD
RD
CRD
D00TL490/B
AGND
BGND
CAC
SYSTEM GND
SUGGESTED GROUND LAY-OUT
PGND
21/34
Electrical characteristics
STLC3055N
6
Electrical characteristics
Table 13. Electrical characteristics
Test conditions: Vpos = 6.0V, AGND = BGND, normal polarity, Tamb = 25 °C.
External components as listed in the "typical values" column of external components table.
Note: Testing of all parameter is performed at 25 °C. Characterisation as well as design
rules used allow correlation of tested performances at other temperatures. All parameters
listed here are met in the operating range: -40 to +85 °C.
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
DC characteristics
Il = 0, HI-Z
Vlohi
Line voltage
(High impedance feeding)
Tamb = 0 to 85 °C
44
42
50
48
V
V
Il = 0, HI-Z
Vlohi
Line voltage
(High impedance feeding)
Tamb = -40 to 85 °C
Il = 0, ACTIVE
Vloa
Vloa
Ilim
Line voltage
Line voltage
33
31
20
40
37
V
V
Tamb = 0 to 85 °C
Il = 0, ACTIVE
Tamb = -40 to 85 °C
Lim. current programming
range
ACTIVE mode
40
mA
ACTIVE mode.
Ilima
Lim. current accuracy
Rel. to programmed value
20 mA to 40 mA
-10
2.4
10
%
Rfeed HI Feeding resistance
HI-Z (High Impedance feeding)
3.6
kΩ
AC characteristics
Rp = 50 Ω, 1% tol.,
ACTIVE N. P., RL = 600 Ω
f = 300 to 3400 Hz
Long. to transv.
L/T
(1)
50
40
58
45
dB
dB
(see Section 6.1: Test circuits.)
Rp = 50 Ω, 1% tol.,
ACTIVE N. P., RL = 600 Ω
f = 300 to 3400 Hz
Transv. to long.
(1)
T/L
(see Section 6.1: Test circuits.)
Rp = 50 Ω, 1% tol.,
ACTIVE N. P., RL = 600 Ω
f = 1 kHz
Transv. to long.
(1)
T/L
2WRL
THL
48
22
30
53
26
dB
dB
dB
(see Section 6.1: Test circuits.)
300 to 3400 Hz,
2W return loss
(1)
ACTIVE N. P., RL = 600 Ω
300 to 3400 Hz,
Trans-hybrid loss
20Log|VRX/VTX|,
(1)
ACTIVE N. P., RL = 600 Ω
22/34
STLC3055N
Electrical characteristics
Table 13. Electrical characteristics (continued)
Test conditions: Vpos = 6.0V, AGND = BGND, normal polarity, Tamb = 25 °C.
External components as listed in the "typical values" column of external components table.
Note: Testing of all parameter is performed at 25 °C. Characterisation as well as design
rules used allow correlation of tested performances at other temperatures. All parameters
listed here are met in the operating range: -40 to +85 °C.
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
at line terminals on ref. imped.
Ovl
TXoff
G24
2W overload level
3.2
-250
-6.4
dBm
mV
dB
(1)
ACTIVE N. P., RL = 600 Ω
(1)
TX output offset
ACTIVE N. P., RL = 600 Ω
250
-5.6
0 dBm @ 1020 Hz,
Transmit gain abs.
(1)
ACTIVE N. P., RL = 600 Ω
0 dBm @ 1020 Hz,
G42
Receive gain abs.
-0.4
0.4
dB
dB
(1)
ACTIVE N. P., RL = 600 Ω
rel. 1020Hz; 0 dBm,
300 to 3400 Hz,
G24f
TX gain variation vs. freq.
-0.12
0.12
(1)
ACTIVE N. P., RL = 600 Ω
rel. 1020 Hz; 0 dBm,
300 to 3400 Hz,
G24f
V2Wp
V2Wp
V4Wp
V4Wp
RX gain variation vs. freq.
-0.12
0.12
-68
dB
(1)
ACTIVE N. P., RL = 600 Ω
psophometric filtered
Idle channel noise at line 0dB
gainset
(1)
ACTIVE N. P., RL = 600 Ω
Tamb = 0 to +85 °C
-73
-68
-75
-75
dBmp
dBmp
dBmp
dBmp
psophometric filtered
Idle channel noise at line 0dB
gainset
(1)
ACTIVE N. P., RL = 600 Ω
Tamb = -40 to +85 °C
psophometric filtered
Idle channel noise at line 0dB
gainset
(1)
ACTIVE N. P., RL = 600 Ω
Tamb = 0 to +85 °C
-70
psophometric filtered
Idle channel noise at line 0dB
gainset
(1)
ACTIVE N. P., RL = 600 Ω
Tamb = -40 to +85 °C
(1)
Thd
Total Harmonic Distortion
Metering pulse level on line
ACTIVE N. P., RL = 600 Ω
-44
dB
mVrms
kHz
ACTIVE - TTX; Gain Set = 1
VTTX
260
340
125
Zl = 200 Ω fttx = 12 kHz;
CLKfreq CLK operating range
Ring
-10%
10%
RING D2 toggling @ fr = 25 Hz
Load = 3REN;
Vring
Line voltage
Crest Factor = 1.25
45
49
Vrms
1REN = 1800 Ω + 1.0 μF
Tamb = 0 to +85°C
23/34
Electrical characteristics
STLC3055N
Table 13. Electrical characteristics (continued)
Test conditions: Vpos = 6.0V, AGND = BGND, normal polarity, Tamb = 25 °C.
External components as listed in the "typical values" column of external components table.
Note: Testing of all parameter is performed at 25 °C. Characterisation as well as design
rules used allow correlation of tested performances at other temperatures. All parameters
listed here are met in the operating range: -40 to +85 °C.
Symbol
Vring
Parameter
Test condition
Min.
Typ.
Max.
Unit
RING D2 toggling @ fr = 25Hz
Load = 3REN;
Line voltage
Crest Factor = 1.25
44
48
Vrms
1REN = 1800Ω + 1.0μF
Tamb = -40 to +85°C
Detectors
ACT. mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
IOFFTHA Off/hook current threshold
10.5
mA
kΩ
mA
kΩ
mA
Ω
Off/hook loop resistance
ACT. mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
ROFTHA
threshold
3.4
6
ACT. mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
IONTHA On/hook current threshold
On/hook loop resistance
ACT. mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
RONTHA
threshold
8
Hi Z mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
IOFFTHI Off/hook current threshold
10.5
Off/hook loop resistance
Hi Z mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
ROFFTHI
threshold
800
6
Hi Z mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
IONTHI On/hook current threshold
mA
On/hook loop resistance
Hi Z mode, RTH = 32.4kΩ 1%
(Prog. ITH = 9mA)
RONTHI
threshold
8
kΩ
mA
%
Ring Trip detector threshold
range
Irt
Ring mode
Ring mode
20
-15
50
15
Ring Trip detector threshold
accuracy
Irta
Trtd
Td
Ring trip detection time
Dialling distortion
Ring mode
60
ms
ms
Ω
Active mode
-1
1
(2)
Rlrt
ThAl
Loop resistance
500
Tj for th. alarm activation
160
°C
24/34
STLC3055N
Electrical characteristics
Table 13. Electrical characteristics (continued)
Test conditions: Vpos = 6.0V, AGND = BGND, normal polarity, Tamb = 25 °C.
External components as listed in the "typical values" column of external components table.
Note: Testing of all parameter is performed at 25 °C. Characterisation as well as design
rules used allow correlation of tested performances at other temperatures. All parameters
listed here are met in the operating range: -40 to +85 °C.
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Digital interface
INPUTS: D0, D1, D2, PD, CLK
OUTPUTS: DET
Vih
Vil
Iih
Iil
In put high voltage
Input low voltage
Input high current
Input low current
Output low voltage
2
V
V
0.8
10
-10
-10
μA
μA
V
10
Vol
Iol = 1mA
0.45
PSRR and power consumption
Vripple = 100mVrms
50 to 4000Hz
Power supply rejection Vpos to
2W port
PSERRC
Ivpos
26
36
dB
HI-Z On-Hook
13
50
55
25
80
90
mA
mA
mA
Vpos supply current @ ii = 0
ACTIVE On-Hook,
RING (line open)
RING Off-Hook
Ipk
Peak current limiting accuracy
-20%
950
+20% mApk
RSENSE = 110mΩ
1. RL: Line Resistance
2. Rlrt = Maximum loop resistance (incl. telephone) for correct ring trip detection.
25/34
Electrical characteristics
STLC3055N
6.1
Test circuits
Referring to the application diagram shown in Figure 8 on page 20 and using as external
components the typical values specified in the Table 10 on page 17 and Table 11 on
page 18, find below the proper configuration for each measurement.
All measurements requiring DC current termination should be performed using "Wandel &
Goltermann DC Loop Holding Circuit GH-1" or equivalent.
Figure 10. 2W return loss 2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs)
W&G GH1
Zref
TX
TIP
600ohm
100μF
Vs
STLC3055N
application
circuit
100mA
DC max
1Kohm
E
Zin = 100K
200 to 6kHz
100μF
1Kohm
RX
RING
Figure 11. THL trans hybrid loss THL = 20Log|Vrx/Vtx|
W&G GH1
TIP
TX
100μF
Vtx
Vrx
Vtx
STLC3055N
application
circuit
100mA
DC max
600ohm
Zin = 100K
200 to 6kHz
100μF
RX
RING
Figure 12. G24 transmit gain G24 = 20Log|2Vtx/E|
W&G GH1
TIP
TX
100μF
STLC3055N
application
circuit
100mA
DC max
600ohm
E
Zin = 100K
200 to 6kHz
100μF
RX
RING
26/34
STLC3055N
Electrical characteristics
Figure 13. G42 receive gain G42 = 20Log|VI/Vrx|
W&G GH1
TIP
TX
100μF
STLC3055N
100mA
Vl
DC max
application
circuit
600ohm
Zin = 100K
200 to 6kHz
100μF
RX
RING
Vrx
Figure 14. PSRRC power supply rejection Vpos to 2W port PSSRC = 20Log|Vn/Vl|
W&G GH1
TIP
TX
100μF
STLC3055N
application
circuit
100mA
DC max
Vl
600ohm
Zin = 100K
200 to 6kHz
100μF
RX
RING
VPOS
Vn
~
Figure 15. L/T longitudinal to transversal conversion L/T = 20Log|Vcm/Vl|
W&G GH1
300ohm
100μF
TIP
TX
100μF
STLC3055N
application
circuit
100mA
DC max
Vl
Impedance matching
better than 0.1%
Zin = 100K
200 to 6kHz
Vcm
100μF
RX
RING
300ohm
100μF
27/34
Electrical characteristics
STLC3055N
Figure 16. T/L transversal to longitudinal conversion T/L = 20Log|Vrx/Vcm|
W&G GH1
100μF
300ohm
TIP
TX
100μF
STLC3055N
100mA
DC max
application
circuit
Impedance matching
better than 0.1%
Zin = 100K
200 to 6kHz
Vcm
600ohm
100μF
RX
RING
Vrx
300ohm
100μF
Figure 17. VTTX metering pulse level on line
TIP
TX
STLC3055N
Vlttx
application
circuit
200ohm
RX
RING
CKTTX
fttx (12 or 16kHz)
Figure 18. V2Wp and W4Wp: idle channel psophometric noise at line and TX.
V2Wp = 20Log|Vl/0.774l|; V4Wp = 20Log|Vtx/0.774l|
W&G GH1
TIP
TX
100μF
Vtx
psophometric
filtered
STLC3055N
application
circuit
100mA
DC max
600ohm
Zin = 100K
200 to 6kHz
Vl
psophometric
filtered
100μF
RX
RING
28/34
STLC3055N
Overvoltage protection
7
Overvoltage protection
Figure 19. Simplified configuration for indoor overvoltage protection
STPR120A
BGND
STLC3055N
RP1
RP1
RP2
RP2
TIP
TIP
RING
RING
VBAT
STPR120A
RP1 = 30ohm:
RP2 =Fuse or PTC > 18ohm
Figure 20. Standard overvoltage protection configuration for K20 compliance
BGND
STLC3055N
RP1
RP1
RP2
RP2
TIP
TIP
LCP1521
RING
RING
VBAT
RP1 = 30ohm:
RP2 =Fuse or PTC > 18ohm
29/34
Typical state diagram for STLC3055N operation
STLC3055N
8
Typical state diagram for STLC3055N operation
Figure 21. State diagram
Normally used for
On Hook Transmission
Tj>Tth
PD=0, D0=D1=0
Active
On Hook
Power
Down
Ring Pause
D0=0, D1=1,
D2=0
Ring Burst
Ring Burst
Ringing
D0=1, D1=0,
D2=0/1
PD=1,
D0=D1=0
On Hook Detection for T>Tref
HI-Z
Feeding
Ring Trip
Detection
Active
On Hook Condition
Off Hook
Off Hook Detection
D0=0, D1=1,
D2=0
Off Hook Detection
Note: all state transitions are under the microprocessor control.
30/34
STLC3055N
STLC3055Q vs STLC3055N compatibility.
9
STLC3055Q vs STLC3055N compatibility.
STLC3055N is pin to pin compatible with the old STLC3055Q but offer a better performance
in term of power consumption and can be set in a new gain configuration in order to be
compatible with the 3.3 V codec.
9.1
Typical power consumption comparison
Table 14. Power consumption differences
Operative mode
STLC3055Q
STLC3055N
HI-Z
52 - 60 mA
93 - 115 mA
120 - 140 mA
13 - 25 mA
50 - 80 mA
55 - 90 mA
Active on hook
Ring (no REN)
To meet this result some differences, with a minimum impact on the application, has been
introduced in STLC3055N.
9.2
Hardware differences
●
RX input. In STLC3055N it is necessary a 100 kΩ external resistor between RX input
and AGND to bias the input stage.
●
●
Rp. The STLC3055N required a Rp value of 50 Ω instead of 41 Ω.
TTX filter. To optimize the ttx signal dynamic, the values of RLV and CFL have been
changed;
Table 15. Hardware differences
Component
STLC3055Q
STLC3055N
RRX
Rp
100 kΩ
50 Ω
41 Ω
27 kΩ
1 nF
RLV
CFL
16.2 kΩ
1.5 nF
9.3
Parameter differences
Table 16. Parameter differences
Parameter
STLC3055Q
STLC3055N
Absolute max. rating
17 V
13 V
12 V
Operating range
15.8 V
Typ. metering pulse level (Gs 1)
Typ. metering pulse level (Gs 0)
340 mVrms
200 mV
170 mV
rms
rms
31/34
Package information
STLC3055N
10
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 22. LQFP44 (10 x 10 x 1.4 mm) mechanical data and package dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN.
TYP. MAX. MIN.
1.60
TYP. MAX.
0.063
A
A1
A2
B
0.05
1.35
0.30
0.09
0.15 0.002
0.006
1.40
0.37
1.45 0.053 0.055 0.057
0.45 0.012 0.015 0.018
C
0.20 0.004
0.008
D
11.80 12.00 12.20 0.464 0.472 0.480
9.80 10.00 10.20 0.386 0.394 0.401
D1
D3
E
8.00
0.315
11.80 12.00 12.20 0.464 0.472 0.480
9.80 10.00 10.20 0.386 0.394 0.401
E1
E3
e
8.00
0.80
0.60
1.00
0.315
0.031
0.75 0.018 0.024 0.030
0.039
L
0.45
L1
k
LQFP44 (10 x 10 x 1.4mm)
0˚(min.), 3.5˚(typ.), 7˚(max.)
0.10
ccc
0.0039
0076922 E
32/34
STLC3055N
Revision history
11
Revision history
Table 17. Document revision history
Date
Revision
Changes
11-Sep-2003
4
First Issue
Update Functional Description and Electrical Characteristics.
Aligned the graphic style to be compliant with the new “Corporate
Technical Publications Design Guide”
01-Oct-2004
15-Oct-2004
5
6
Modified the application diagrams and some typo errors.
Removed all max. values of the ‘Line Voltage’ parameter on the page
14/24.
05-Nov-2004
7
Changed the unit from mA to % of the ‘Ilima’ parameter on the page
14/24.
Add pin 4 PD in Applications and Block Diagram
Add in Table 2 ‘ESD Rating’
15-Jan-2005
01-Jul-2005
8
9
Changed VTTX value
Added part number “E-STLC3055N” (ECOPACK).
Added RRX resistance in the figures 9 and 10.
Added Appendix D.
21-Feb-2006
12-Feb-2009
10
11
Document reformatted.
Updated Section 10: Package information on page 32.
33/34
STLC3055N
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