STLC3040 [STMICROELECTRONICS]
A/MU-LAW, PCM CODEC, PQCC44, PLASTIC, LCC-44;
| 型号： | STLC3040 |
| 厂家： | 
ST |
| 描述： | A/MU-LAW, PCM CODEC, PQCC44, PLASTIC, LCC-44 PC 电信 信息通信管理 电信集成电路 |
| 文件： | 总13页 (文件大小：893K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCF4536B
PROGRAMMABLE TIMER
0
■
■
■
■
■
24 FLIP-FLOP STAGES - COUNTS FROM 2
TO 2
LAST 16 STAGES SELECTABLE BY BCD
SELECT CODE
GROUP SELECT INDICATES ONE OR
MORE PRIORITY INPUTS
24
DIP
QUIESCENT CURRENT SPECIFIED UP TO
20V
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
ORDER CODES
■
■
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
PACKAGE
TUBE
T & R
DIP
HCF4536BEY
I = 100nA (MAX) AT V = 18V T = 25°C
I
DD
A
■
■
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
can be driven by an external clock or an RC
oscillator that can be constructed using on-chip
components. Input IN1 serves as either the
external clock input or the input to the on-chip RC
oscillator. OUT1 and OUT2 are connection
terminals for the external RC components. In
addition, an on-chip monostable circuit is provided
to allow a variable pulse width output. Various
timing functions can be achieved using
combinations of these capabilities. A logic "1" on
the 8-BYPASS input enables a bypass of the first
8 stages and makes stage 9 the first counter stage
of the last 16 stages. Selection of 1 of 16 outputs
is accomplished by the decoder and the BCD
inputs A, B, C, and D. MONO IN is the timing input
DESCRIPTION
HCF4536B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP package.
HCF4536B is a programmable timer consisting of
24 ripple-binary counter stages. The salient
feature of this device is its flexibility. The device
can count from 1 to 2 or the first 8 stages can be
bypassed to allow an output, selectable by a 4-bit
code, from any one of the remaining 16 stages. It
24
PIN CONNECTION
October 2002
1/13
HCF4536B
for the on-chip monostable oscillator. Grounding
of the MONO IN terminal through a resistor of 10
KΩ or higher, disables the one shot circuit and
connects the decoder directly to the DECODE
one-shot circuit and controls its pulse width. A fast
test mode is enabled by a logic "1" on 8-BYPASS,
SET, and RESET. This mode divides the 24-stage
counter into three 8-stage sections to facilitate a
fast test sequence.
OUT terminal. A resistor to V and a capacitor to
DD
ground from the MONO IN terminal enables the
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
9, 10, 11, 12
A, B, C, D Binary Select Input
1
2
SET
Set input
RESET
Reset Input
Monostable OscillatorTim-
ing Input
15
6
MONO IN
8BYPASS
IN1
8Bypass input( bypass
the first 8 stages)
External Clock Input or
RC oscillator Input
3
4, 5
13
OUT1, OUT2 Outputs
DECODE
Decode Out Terminal
OUT
CLOCK
INHIBIT
7
Clock Inhibit Input
OSC.
INHIBIT
14
Oscillator Inhibit Input
V
8
Negative Supply Voltage
Positive Supply Voltage
SS
V
16
DD
FUNCTIONAL DIAGRAM
2/13
HCF4536B
TRUTH TABLE
In1
Set
Reset
Clock Inh
Osc. Inh
Out1
Out2
Decode Out
L
L
L
L
L
L
L
L
No Change
Advance to Next State
X
X
X
L
H
L
L
L
L
H
L
L
L
L
L
L
X
L
L
H
H
H
L
H
L
No Change
No Change
L
L
H
H
L
L
L
Advance to Next State
X : Don’t Care
DECODE OUT SELECTION TABLE
NUMBER OF STAGES IN DIVIDER CHAIN
D
C
B
A
8-BYPASS = 0
8-BYPASS = 1
L
L
L
L
L
L
L
H
L
9
1
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
L
L
H
H
L
3
L
L
H
L
4
L
H
H
H
H
L
5
L
L
H
L
6
L
H
H
L
7
L
H
L
8
H
H
H
H
H
H
H
H
9
L
L
H
L
10
11
12
13
14
15
16
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
BLOCK DIAGRAM
3/13
HCF4536B
LOGIC DIAGRAM
4/13
HCF4536B
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage
DC Input Voltage
DC Input Current
-0.5 to +22
V
V
DD
V
-0.5 to V + 0.5
I
DD
I
± 10
200
mA
mW
mW
°C
I
P
Power Dissipation per Package
Power Dissipation per Output Transistor
Operating Temperature
D
100
T
-55 to +125
op
T
Storage Temperature
-65 to +150
°C
stg
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V pin voltage.
SS
5/13
HCF4536B
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
Supply Voltage
3 to 20
0 to V
V
V
DD
V
Input Voltage
I
DD
T
Operating Temperature
-55 to 125
°C
op
DC SPECIFICATIONS
Test Condition
Value
T
= 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
V
|I |
V
DD
I
O
O
(V)
(V)
(µA) (V)
Min. Typ. Max. Min. Max. Min. Max.
I
Quiescent Current
0/5
0/10
0/15
0/20
0/5
5
0.04
0.04
0.04
5
150
300
150
300
L
10
15
20
10
20
µA
600
600
0.08 100
3000
3000
V
High Level Output
Voltage
<1
<1
<1
<1
<1
<1
<1
<1
5
4.95
9.95
4.95
9.95
4.95
9.95
OH
0/10
0/15
5/0
10
V
V
V
V
15 14.95
14.95
14.95
V
Low Level Output
Voltage
5
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
OL
10/0
15/0
10
15
V
High Level Input
Voltage
0.5/4.5
1/9
5
3.5
7
3.5
7
3.5
7
IH
10
15
5
1.5/13.5 <1
11
11
11
V
Low Level Input
Voltage
4.5/0.5
9/1
<1
<1
1.5
3
1.5
3
1.5
3
IL
10
15
5
13.5/1.5 <1
4
4
4
I
Output Drive
Current
0/5
0/5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
<1
<1
<1
<1
<1
<1
<1
-1.36 -3.2
-1.1
-0.36
-0.9
-2.4
0.36
0.9
-1.1
-0.36
-0.9
-2.4
0.36
0.9
OH
5
-0.44
-1.1
-3.0
0.44
1.1
-1
-2.6
-6.8
1
mA
mA
0/10
0/15
0/5
10
15
5
I
Output Sink
Current
OL
0/10
0/15
10
15
2.6
6.8
3.0
2.4
2.4
I
Input Leakage
Current
I
-5
0/18
Any Input
18
±0.1
±1
±1
µA
±10
C
Input Capacitance
Any Input
5
7.5
pF
I
The Noise Margin for both "1" and "0" level is: 1V min. with V =5V, 2V min. with V =10V, 2.5V min. with V =15V
DD
DD
DD
6/13
HCF4536B
DYNAMIC ELECTRICAL CHARACTERISTICS (T
= 25°C, C = 50pF, R = 200KΩ, t = t = 20 ns)
amb
L
L
r
f
Test Condition
Value (*)
Unit
Symbol
t
Parameter
V
(V)
Min. Typ. Max.
DD
t
Propagation Delay Time
(Clock to Q1, 8-Bypass
High)
5
1
0.5
0.35
2.5
0.8
0.6
4
2
1
PLH PHL
10
15
5
µs
µs
µs
ns
0.7
5
Propagation Delay Time
(Clock to Q1, 8-Bypass
Low)
10
15
5
0.6
1.2
8
Propagation Delay Time
(Clock to Q16)
10
15
5
1.5
1
3
2
Propagation Delay Time
(Qn to Qn+1)
150
75
300
150
100
600
250
160
6
10
15
5
50
t
t
Propagation Delay Time
Reset to Qn
Transition Time
Pulse Width Clock
Set
300
125
80
PLH
10
15
5
ns
3
PHL
10
15
5
1
2
µs
ns
0.75
100
50
1.5
200
100
80
400
150
100
400
200
120
6
t
t
THL TLH
10
15
5
40
t
200
75
W
10
15
5
ns
50
200
100
60
10
15
5
ns
Reset
3
10
15
5
1
2
µs
µs
µs
µs
MHz
0.75
2.5
1
1.5
5
Recovery Time Set
Reset
10
15
5
2
0.6
3.5
1.5
1
1.6
7
10
15
5
3
2
t t
Clock Input Rise or Fall
Time
r, f
10
15
5
Unlimited
f
Maximum Clock Input
Frequency
0.5
1.5
2.5
1
3
5
CL
10
15
(*) Typical temperature coefficient for all V value is 0.3 %/°C.
DD
7/13
HCF4536B
TYPICAL APPLICATIONS
Time Internal Configuration Using External Clock;
Set and Clock Inhibit Functions
Time Internal Configuration Using On-Chip RC
oscillator and Reset Input to Initiate Time Interval
Time Internal Configuration Using Ext. Ck; Reset
and Output Monostable to Achieve a Pulse Out
Use of HCF4098B and HCF4536B to get Decode
Pulse 8 Clock Pulses after Reset Pulses
TIMING DIAGRAM
8/13
HCF4536B
FUNCTIONAL TEST SEQUENCE
Outputs
Inputs
COMMENTS
Decade Out
In 1
Set
Reset
8-Bypass
Q1 Thru
Q24
All 24 steps are in reset mode
H
H
L
L
H
H
H
H
H
H
H
H
L
L
L
Counter is in three 8-stage section in parallel
mode
First "H" to "L" Transition of Clock
H
L
255 "H" to "L" transitions are clocked in the
counter
H
H
H
H
H
H
L
H
H
The 255 "H" to "L" Transition
Counter converted back to 24 stages in series
mode.
L
L
L
L
Set and Reset must be connected together
and simultaneously go from "H" to "L"
In switches to a "H"
H
L
L
L
L
L
L
L
H
L
1
Counter Ripples from an all "H" state to an all
"L" state
FUNCTIONAL TEST SEQUENCE
Test function has been included for the reduction
of test time required to exercise all 24 counter
stages.This test function divides the counter into
three 8-stage section and 255 counts are loaded in
each of the 8-stage sections in parallel. All
flip-flops are now at a "H". The counter is now
returned to the normal 24-steps in series
configuration. One more pulse is entered into In1
which will cause the counter to ripple from an all
"H" state to an all "L" state.
TEST CIRCUIT
C
R
R
= 50pF or equivalent (includes jig and probe capacitance)
L
L
T
= 200KΩ
= Z
of pulse generator (typically 50Ω)
OUT
9/13
HCF4536B
WAVEFORM : PROPAGATION DELAY TIMES, PULSE WIDTH CLOCK
10/13
HCF4536B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
0.51
0.77
MAX.
MIN.
0.020
0.030
MAX.
a1
B
b
1.65
0.065
0.5
0.020
0.010
b1
D
E
e
0.25
20
0.787
8.5
2.54
17.78
0.335
0.100
0.700
e3
F
7.1
5.1
0.280
0.201
I
L
3.3
0.130
Z
1.27
0.050
P001C
11/13
HCF4536B
SO-16 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.007
0.064
0.018
0.010
A
a1
a2
b
0.1
0.003
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45˚ (typ.)
9.8
5.8
10
0.385
0.228
0.393
0.244
E
6.2
e
1.27
8.89
0.050
0.350
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.024
G
L
1.27
0.62
M
S
˚ (max.)
8
PO13H
12/13
HCF4536B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2002 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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13/13
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