STLC3040-TR [STMICROELECTRONICS]

STLC3040-TR;
STLC3040-TR
型号: STLC3040-TR
厂家: ST    ST
描述:

STLC3040-TR

PC 电信 信息通信管理 电信集成电路
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STLC3040  
®
SUBSCRIBER LINE INTERFACE CODEC FILTER, COFISLIC  
Single chip CODEC and FILTER including all  
LOW-VOLTAGE SLIC functions.  
Advanced 12V BJT, 5V CMOS 0.8um technol-  
ogy.  
Low external component count.  
Over-sampling A/D and D/A conversion.  
No functional trimming or adjustments re-  
PLCC44  
quired.  
ORDERING NUMBERS: STLC3040  
STLC3040-TR  
Serves a wide range of specifications; i.e. ITU-  
T, LSSGR.  
A-law, and µ-law PCM and Linear voice cod-  
ing, sw selectable  
Figure 1: Pin Connection (Top view)  
GCI compatible interface.  
Programmable Digital-Filters for impedance-  
matching, hybrid-balance, frequency-response  
and gain.  
6
5 4 3 2 1 44 43 42 41 40  
Programmable Feeding-Resistance (2 x 50Ω  
to 2 x 400) and current-limiting (0-69.3mA).  
Programmable voltage-drop according to  
transmission needs.  
12kHz/16kHz Teletax Generation with Pro-  
grammable Level 0-10 Vrms in 40mV steps in-  
cluding shaping and filtering.  
Integrated Ring-Generator with Zero-Crossing.  
Programmable frequency from 16.6Hz to  
60Hz, programmable level up to 85Vrms, Inte-  
grated auto ring-trip.  
IO1  
IO2  
C1  
7
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
O1  
8
I1  
9
SIR2  
MR  
IDH  
C2  
10  
11  
12  
13  
14  
15  
16  
17  
VL1  
VL2  
SIR0  
CAP  
IL  
V
CC  
V
EE  
IDM  
IDL  
RAC  
SIR1  
STR2  
EXT  
Signalling functions ON/OFF - Hook, Gnd-key  
with filter and Programmable persistence  
check.  
18 19 20 21 22 23 24 25 26 27 28  
D94TL161D  
Advanced test capabilities:  
On-board line tests and circuit tests.  
Signalling tests for meterpulse TTX and Ring-  
ing.  
On chip Line-card identification.  
Tone generator for circuit test.  
3 Loop-back paths.  
DESCRIPTION  
The subscriber line codec-filter, STLC3040, is  
fabricated in BiCMOS (12V bipolar / 5V CMOS)  
technology. It uses Digital-Signal-Process-  
ing(DSP) to implement central-office telephone in-  
terface features: DC-feed, Supervision, PCM-  
Codec-Filter, Ring, Teletax metering (TTX) and  
Test functions. The STLC3040 is fully program-  
mable and needs few external resistors and ca-  
pacitors.  
Three operating conditions:  
Power Down, Active, Ringing. Off-hook pro-  
grammable threshold-level in each of these  
conditions.  
Interface to High-Voltage SLIC to select  
modes, provide hard or soft Polarity-Reversal  
and sense HV (L3000N, L3000S, STLC3170)  
High Thermal condition.  
On-hook transmission capability.  
Selectable 2/4MHz backplane clock.  
Standard PLCC 44 package.  
The STLC3040 interfaces the subscriber’s line via  
the High-Voltage (HV) (L3000N, L3000S,  
STLC3170) device and the central-office back-  
1/49  
January 1999  
STLC3040  
is possible in all operating modes as described in  
section 4.  
Ring-signal with zero-crossing start/stop injection  
is generated on chip with programmable fre-  
quency and amplitude. In addition, when Ring-  
trip is detected, the Ring-signal is automatically  
disconnected at the next zero-crossing.  
Power consumption is kept low by providing a  
"Power-Down" mode where the HV-SLIC is  
switched off (Power Denial). A set of internal re-  
sistors connected to the line allows Off-hook de-  
tection in this mode. Overall power dissipation is  
around 50mW (max.) in Power Down mode.  
Several testing features are included in the  
STLC3040, both for self-test and to test line leak-  
age, capacitance ..etc, thus saving on test equip-  
ment and relays. Measured DC quantities are dig-  
itized and sent via the B1 voice channel to the  
backplane. With proper software selection each  
signal can be modulated by a 1KHz carrier before  
being sent to B1 voice channel. Programmable  
linear code, software selectable, boosts the calcu-  
lation resolution.  
DESCRIPTION (continued)  
plane via a GCI compatible interface (see fig.2).  
The GCI handles all STLC3040 control and voice  
channel.  
The STLC3040 processes the transversal line-  
current sensed by the ST HV (L3000N, L3000S,  
STLC3170) Line Driver Circuit and generates  
voltage-drive to the line via the HV (L3000N,  
L3000S, STLC3170), thus synthetizing the imped-  
ances required by various world administrations .  
Line impedances as well as the two-to-four wire  
conversion synthesis are software programmable.  
Also Transmit (Tx) and Receive(Rx) AC fre-  
quency–response, determined by DSP-filters,  
guarantee voice-band flat-response. Tx and Rx  
Gains are programmable as well. Digitized voice  
can be encoded on A-law or u-law.  
The DC characteristic is obtained by selecting  
limit-current value, DC-feed resistance (2 X 50  
steps) and Drop-voltage. It also permits On-hook  
transmission and TTX pulse injection with filtering  
and shaping. TTX metering pulse generation (12  
or 16kHz) has programmable amplitude up to 10  
Vrms.  
Sigma-Delta converters (ASD: Analog, DSD: Digi-  
tal) make the conversion independent of technol-  
ogy parameters (fig. 3).  
Off-hook detection with programmable thresholds  
Figure 2: Functional Diagram.  
LV  
HV  
STLC3040  
L3000N  
FSC  
DIGITAL  
SIGNAL  
PROCESSOR  
RP1  
RP2  
DCL  
GCI  
VOUT  
VIN  
TIP  
ITIP  
INT.  
DU  
A=20  
DD  
RING  
IRING  
A=-20  
Iline  
IT  
IT  
CURRENT  
SENSORS  
ANALOG  
FRONT  
END  
IL  
IL  
REF  
C2  
PDO  
C2  
C1  
HV  
CONTROL  
C1  
VBIM  
CDVB  
ACDC  
CAC  
CAP  
RAC  
RDC  
REF  
VCC  
D95TL204B  
STLC3040 PIN DESCRIPTION (This list is grouped according to Function)  
N.  
Symbol  
Type (*)  
Description  
POWER SUPPLY  
1
2
27  
33  
34  
DGND  
VDD  
AGND  
VEE  
PS  
PS  
PS  
PS  
PS  
Digital Ground  
+5V Digital Supply Voltage  
Analog Ground  
-5V Analog Supply Voltage  
+5V Analog Supply Voltage  
VCC  
2/49  
STLC3040  
STLC3040 PIN DESCRIPTION (continued)  
N.  
GCI  
40  
Symbol  
Type (*)  
Description  
SEL24  
DI  
Select Clock Frequency for GCI Interface 2MHz/4MHz not affecting the data rate  
(2Mbit/s)  
If SEL24 = 0, Clock Frequency = 2048KHz  
If SEL24 = 1, Clock Frequency = 4096KHz  
43,42, TS0,TS1,  
DI  
GCI Select Time Slot Identifier Pins  
41  
3
4
5
TS2  
FSC  
DCL  
DD  
DI  
DI  
DI  
Frame Sync 8kHz GCI Interface  
Master Data Clock GCI Interface  
Data Down link GCI Interface  
6
DU  
OD  
Data Up link GCI Interface (Open Drain Driver)  
INTERFACE TO HV SLIC  
9
C1  
AI/O  
State Control Signal 1. Combination of C1 and C2 defines HV (L3000N, L3000S,  
STLC3170) operating mode. Current sense for thermal indication.  
10  
28  
C2  
AO  
State Control Signal 2. Combination of C1 and C2 defines HV (L3000N, L3000S,  
STLC3170) operating mode.  
Power down output. Proper bias current is provided to HV (L3000N, L3000S, STLC3170) by this  
pin. When the current is 0 the HV (L3000N, L3000S, STLC3170) goes in Power Denial (high  
impedance). Proper combinations of PDO with C1, C2 set additional operating modes for  
STLC3170 High Voltage Interface.  
PDO  
AO  
11,12 VL1, VL2  
AI  
Comparator Input. These are inputs of the comparator that senses the line voltage in  
Power Denial allowing Off/Hook detection in this mode.  
15  
19  
25  
26  
IL  
IT  
VBIM  
VOUT  
AI  
AI  
AI  
Longitudinal Line-Current input IL = (ITIP - IRING)/100.  
Transversal Line-Current input IT=(ITIP + IRING)/100.  
Battery image monitor.  
Output feeding the line voltage (DC, AC, RING, TTX) through H.V. HV (L3000N,  
L3000S, STLC3170).  
AO  
I/O  
7, 8  
39  
IO1, IO2  
O1  
DI/O  
DO  
DI  
Programmable GCI controlled I/O.  
Digital output written via GCI.  
Digital input read via GCI.  
38  
I1  
MISCELLANEOUS FUNCTION  
29  
36  
EXT  
MR  
DI  
DI  
External Ring Sync. Input.  
Master Reset Input. Active High. The STLC3040 is forced in Loop-open and internal  
registers are preset to default values.  
31,32 IDL, IDM  
AI  
DI  
AI/O  
AI/O  
AI/O  
AI  
Identification Code Signals, M+L ternary digits  
H most significant bit, L least significant bit.  
Capacitor must be connected to this pin. Its value defines the Soft Battery Reversal slope.  
AC-Synthesis Reference Resistor.  
AC/DC Line Split. Scaled line-current output, DC feedback input.  
Splitter Capacitor. Scaled AC line-current input.  
35  
IDH  
CAP  
RAC  
ACDC  
CAC  
RDC  
REF  
14  
16  
20  
21  
22  
23  
AI  
AI/O  
DC-Synthesis Reference Resistor.  
Reference Voltage Output. A resistor on this pin sets the internal reference current.  
UNUSED  
18,24 STR0,STR1 DI/O  
30,44 STR2,STR3  
Reserved for testing, must be shorted to DGND.  
13,17 SIR0, SIR1  
37 SIR2  
DI/O  
DI/O  
Must be left open.  
Can be left open  
(*) Type Description  
Type Description  
Type Description  
AI  
AO  
Analog Input  
Analog Output  
DI  
PS  
Digital Input  
Chip Power/Ground  
DO  
OD  
Digital Output  
Open Drain Output  
AI/O Analog Input/Output  
DI/O Digital Input/Output  
3/49  
STLC3040  
different conditions are present and depend on  
loop resistance.  
4 FUNCTIONAL DESCRIPTION  
The STLC3040 is implemented by a combination  
of analog and digital circuits, merging the best  
available analog and digital processing perform-  
ances of the BiCMOS technology. In particular  
two main blocks of the STLC3040 can be identi-  
fied: an analog front end interfacing the HV  
(L3000N, L3000S, STLC3170) and a programma-  
ble DSP. (See fig. 3)  
a) Resistive Feed Region: the SLIC kit operates  
as a voltage source with a series resistance  
50 ), where n can be  
equal to (2Rp+n  
2
programmed from 1 to 8 via CR8 register. Vari-  
ous values of voltage drops are possible as  
shown in Fig. 4.  
b) Constant current region: when IL reaches the  
programmed limiting current value (from 0 to  
69.3mA; 1.1mA step via CR6 register), the Kit  
operates as a proper constant current source.  
(see Fig. 4).  
4.1 - Signal processing.  
The line-current signal received in pin IT from the  
HV (L3000N, L3000S, STLC3170) is mirrored out  
of pin ACDC. On its way, its value is sensed to  
determine Off-Hook signalling. While in active  
conversation this istantaneous sensing is used for  
fast Hook signalling such as numbering. Then  
line-current AC and DC parts are splitted by RDC  
and CAC. The signal is processed to realize AC  
and DC impedance synthesis. Indeed IT pin car-  
ries the AC current due to voice signals present at  
line terminals and the DC current related to the  
specific V-I operating point.  
During Stand-By mode signal is created by the  
DC current after AC part has been removed. This  
filtered Hook produces robust signalling in Stand-  
by mode or pause-period during reduced-power  
Ring mode.  
Concerning AC Processing the AC current-signal  
is converted to voltage on the reference resistor  
RAC (1620 ).  
Line impedance (real or complex) synthesis is  
carried out thanks to programmable filters. All the  
filters are integrated in the digital side of COFIS-  
LIC except the so called KA filter that is in the  
Analog Front End.  
KD and Z (in digital side) filters allow to match the  
line impedance if properly programmed. Further-  
more KA ensures stability to impedance synthesis  
loop.  
In the Receive direction (Rx), the Analog Front  
End (AFE) receives a 1-bit modulated composite  
signal, which represents part of the voltage to be  
forced into the line. It performs DAC and filtering  
As far as the DC characteristic is concerned, two  
Figure 3: Block Diagram.  
DIGITAL SIGNAL PROCESSOR  
ANALOG FRONT END  
Post  
Filter  
A/u  
exp.  
GR  
R
+
DSD  
LB1  
LB3  
Rx  
FSC  
DCL  
DU  
TTX  
RING  
TEST  
Echo  
Canc.  
B
+
VOUT  
GCI  
INT.  
Z
DD  
Tx  
KA  
LB1  
LB2  
LB3  
+
A/u  
Comp.  
GX  
X
+
KD  
DEC  
ASD  
ANTIALIAS  
FILTER  
TTX  
Canc.  
Ilim  
DC Char  
Curr. buff.  
RDC  
ACDC  
CAC  
CAC  
RAC  
IT  
RAC  
RDC  
D95TL205D  
4/49  
STLC3040  
Figure 4.  
I
L
VDROP = 9.6V + VdTTX .40 (see par 4.3.2.1)  
ILIM: 0-70mA 1.1mA step  
I
LIM  
V
DROP  
R
FEED  
= 2 * R + n * 100Ω  
P
V
BAT  
V
L
V
OL  
I
L
100mA  
(typ)  
RING MODE  
R
FEED  
= 2R  
P
V
L
V
-22V  
BAT  
I
L
I
LIM  
STAND-BY MODE  
LIM: 0-70mA 1.1mA step  
I
R
FEED  
= 2 * R + n * 100Ω  
P
V
L
V
BAT  
-5.85V  
D95TL208D  
functions. This voltage is then combined with the  
AC and DC analog impedance signals, plus a  
TTX pulse, in a summing buffer that feeds the Vin  
pin of the HV (L3000N, L3000S, STLC3170).  
The architecture of the digital section is based on  
Digital Signal Processor which synthetises 7 digi-  
tal filters (B, Z, X, R, KD, GX, GR). KA uses the  
some register value as KD. In Table 1 you can  
find the number of coefficients and their bit width  
for each filter.  
deep registers. These internal filters can be en-  
abled setting the most significant 5 bits of CR4  
register and CR11 (1). PCM encoding and ITU-T  
high/lowpass-filtering are done by dedicated state  
machines. Setting the bit 0 of CR4 register A-law  
µ−  
or law can be selected.  
In order to match the complex line impedance,  
both amplitude and phase can be programmed  
using Filter Z.  
The two to four wires echo cancellation is imple-  
mented thanks to programmable echo canceler  
(B Filter) with Gain and Group-delay equalizer.  
Table 1:  
Two programmable FIR filters X and R, can be  
set in order to guarantee the best overall line fre-  
quency response in the frequency domain, ac-  
cording to the local specifications. In this way the  
signal distorsion can be reduced with 14-bits  
resolution.  
Gain Setting, both in transmission and in receive,  
is done by two FIR filters (GX for transmission,  
GR for Receive).  
A coefficient optimization software let the users  
calculate GX and GR filters coefficients.  
In transmission the maximum achievable gain  
without distortion is 3dB.  
NUMBER OF  
COEFFICIENTS  
COEFFICIENT  
WIDTH  
FILTER  
B
R
8
4
4
1
1
1
3
14 BITS  
14 BITS  
X
14 BITS  
GR  
GX  
KA, KD  
Z
8 BITS  
8 BITS  
8, 14 BITS (*)  
14 BITS  
(*) KA is a subset of KD = most significant bits, (5-12) but sign bit,  
of KD register.  
Filter coefficients can be programmed by 14 bits  
5/49  
STLC3040  
In receive the maximum programmable gain is  
0dB.  
Table 3:  
PDO = 50 A  
µ
Gain step resolution in both sides (Rx and Tx) de-  
pends on the value of the gains. See table below  
to gain/step accuracy.  
pin 9 (C1)  
(*)Vmv  
(*)Vhv  
(*)Vlv  
(*)Vhv  
ST-BY  
TIP OPEN RING OPEN  
pin 10  
(C2)  
Table 2.  
(*)Vmv CONV.NP  
(*)Vlv CONV.RP  
BB.NP  
BB.RP  
RING NP  
RING RP  
Tx & Rx Gain  
Step accuracy  
0.070dB  
0.14dB  
Xmax - 6dB (1/128)  
Xmax - 12dB (1/64)  
Xmax - 18dB (1/32)  
Xmax - 24dB (1/16)  
Xmax - 30dB (1/8)  
Xmax - 36dB (1/4)  
Xmax - 42dB (1/2)  
µ
PDO = 0 A  
pin 9 (C1)  
(*)Vmv  
0.27dB  
(*)Vhv  
(*)Vlv  
0.56dB  
(*)Vhv Ext. Indication Ext. Indication  
Ext.  
Indication  
1.16dB  
2.5dB  
(*)Vmv Ext. Indication  
(*)Vlv Ext. Indication  
Ext.  
Indication  
Ext.  
Indication  
pin  
10  
(C2)  
6.0dB  
Tx: Xmax = 3dB; Rx: Xmax = 0dB  
Ext.  
Indication  
Loop Open  
(HV Internal  
Resistors  
The Voice Signal Processing is shown in Block  
diagram in Fig.3.  
In the RX direction, after being decoded, the voice  
sample passes through a set of interpolator and  
correction filters. The signal is finally oversampled  
to a high-rate of 256kHz before being summed to  
the feed-back impedance synthesis signal.  
disconnect)  
(*) Vhv, Vmv, Vlv see digital interface electrical characteristics.  
Through PDO pin (pin 28) the STLC3040 forces  
the HV (L3000N, L3000S, STLC3170) in Power  
Denial if the current at this pin is 0. When the  
µ
STLC3040 sinks 50 A the HV (L3000N, L3000S,  
STLC3170) will be turned on. In Power Denial,  
TIP and RING wires are disconnected from the  
HV (L3000N, L3000S, STLC3170) driver (Power  
Analog circuits performs Off-Hook sense and al-  
lows On-Hook Signaling.  
The longitudinal line current provided by the HV  
(L3000N, L3000S, STLC3170) is sensed at pin IL;  
Ground Key signalling is activated when the ab-  
solute longitudinal current on IL pin exceeds  
threshold. A low pass filter and programmable  
persistance filter (register CR3) elaborates the  
detection.  
µ
Denial). Table 3 related to PDO = 0 A is valid  
only for STLC3170.  
VL1, VL2 pins sense, the Off-Hook when HV  
(L3000N, L3000S, STLC3170) is in power denial,  
allowing very low power consumption in On-Hook  
condition.  
Other important features, which usually require  
external circuitry, like Test Tones, Ringing, Meter-  
ing Impulse Injection are programmable via soft-  
ware. Ring signals can be programmed both in  
Amplitude and Frequency via CR9 register.  
The Metering Pulse Injection Level can be set by  
the CR10 register. Ring-Trip detection is per-  
formed by a dedicated internal circuitry.  
The Vbim pin receives from the HV (L3000N,  
L3000S, STLC3170) an information on the actual  
battery voltage (Vbim = Vbat/40), this voltage is  
then compared with the line voltage and one bit is  
set in the upstream data flow if Vline < (VOL/2).  
This allows the system to be tailored for different  
line requirements.  
Line and circuit-test functions are discussed in  
detail in the appendix.  
The HV (L3000N, L3000S, STLC3170) is driven  
by the STLC3040 through two ternary pins C1  
and C2 (pin 9 & 10 of STLC3040) that define the  
operating state of the HV (L3000N, L3000S,  
STLC3170) (Table 3).  
C1 and C2 are set according to the content of the  
bytes received by STLC3040 at DD pin (pin 5) of  
the GCI Interface. C1 pin is internally tied to a  
current-sensing circuit. It senses an extra current  
that the HV (L3000N, L3000S, STLC3170) issues  
when in thermal overload conditions.  
4.3 Slic Kit Operating Modes  
STLC3040/HV (L3000N, L3000S, STLC3170) kit  
can work in three main modes:  
- POWER DOWN  
- ACTIVE  
- RING  
Each mode is selected by Command-Indicate  
(C/I) and Monitor GCI channels. Line State  
changes are signalled through either upstream  
C/I or SR register. During the switching between  
any two modes the indication is frozen for  
10msec in addition to the programmed persis-  
6/49  
STLC3040  
tance.  
RING pins; theHV shows on TIP pin the RT im-  
pedance and on RING pin the RR impedance if it  
integrates the 2 external resistors RT and RR  
(STLC3170). This mode is used to get a low  
power consumption obtaining supervision only via  
the STLC3040 and a resistive sensing network.  
The total power consumption of the SLIC Kit in  
this mode is under to 50mW (being almost 0 the  
consumption from battery).  
All operating modes with related C/I command  
bits and CR register bits are shown in table 13  
pag 45.  
4.3.1 POWER DOWN  
In this condition SLIC Kit reduces strongly its  
power consumption allowing Off-Hook detection.  
Only the internal circuitry dedicated to the Off-  
Hook detection is switched on.  
C/I and CR1 register configuration (programmed  
by Monitor) defining Power Down Submodes are  
here below shown:  
4.3.1.2 - Loop Open  
This mode can be selected only if the High Volt-  
age integrates the two external resistors (RR, RT  
see fig. 5) of the feeding and sensing circuitry.  
This is implemented on the STLC3170 high volt-  
age device.  
Table 4: Power Down Submodes  
SLIC KIT MODE  
C/I C/I C/I CR1 CR1 CR1  
(7)  
(6)  
(5)  
(7)  
(3)  
(2)  
4.3.1.3 - Stand-By  
EXTERNAL  
INDICATION  
0
0
0
0
X
X
SLIC behaves like a constant current source with  
typical 7mA feeding current. Open loop voltage is  
equal to (Vbat - 5.85V). COFISLIC power con-  
sumption is reduced to 150mW typical. Current  
limit and Off-Hook threshold are programmable  
by register CR7. Both off-hook and ground-key  
detectors are operating.  
LOOP OPEN  
STAND BY  
0
0
0
0
0
0
1
0
0
X
1
1
X
0
1
X
0
1
GROUND START  
4.3.1.1 - External Indication  
4.3.1.4 - Ground Start  
When this mode is selected both STLC3040 and  
HV (L3000N, L3000S, STLC3170) are set in  
Power Denial. STLC3040 cuts the bias current,  
sunk by the HV (L3000N, L3000S, STLC3170) via  
the PDO pin. In this mode the HV (L3000N,  
L3000S) shows a high impedance on TIP and  
The SLIC is set in Stand-By with the TIP wire (the  
most positive wire) in high impedance.  
The current feeding is equal to Stand-By mode  
current feeding.  
Figure 5: Application Diagram.  
BGND AGND VCC  
VB+  
VCC VDD VEE AGND DGND  
RT  
VIN  
REF  
IT  
VOUT  
EXT  
RP  
SEL24  
DU/DD(2)  
DCL  
TIP  
PDO  
IT  
MNT  
FSC  
IL  
IL  
TSn(3)  
IOn(2)  
O1  
C1  
C1  
L3000S  
Power SO20  
STLC3040  
44PLCC  
RP  
RING  
RR  
C2  
C2  
I1  
VBIM  
VBIM  
MR  
IDn(3)  
STRn/SIRn(7)  
CDVB  
DS  
VB-  
BGND  
VL2  
VL1  
CAP  
REF  
RAC  
RAC  
RDC  
RDC  
ACDC  
CAC  
CAC  
REF  
CAP  
D95TL203B  
VCC  
7/49  
STLC3040  
in 1.1mA steps ranging from 0mA to 69.3mA. In  
resistive feeding region SLIC kit operates like a  
constant voltage source with a series impedance  
4.3.2 - ACTIVE  
This operating mode is selected by the card proc-  
essor after an Off-Hook detection in order to allow  
signal transmission on the line. Both Off-Hook  
and ground-key detectors are operating.  
GCI Command - Indicate channel and CR1 regis-  
ter configuration (programmed by GCI Monitor)  
defining Active modes are herebelow shown:  
Rfeed = 2Rp+n 2 50 (being Rp the external  
protection resistor and n a value set from 1 to 8  
via CR8 register).  
Voltage drop (Fig. 4) can be programmed in order  
to optimize voltage feeding characteristic, accord-  
ing to AC signal swing requested (ex: voice, voice  
+ 2Vrms TTX, voice + 5Vrms TTX):  
Table 5:  
VDROP = Vd3000 + 40 (VdAC + VdTTX)  
SLIC MODE  
C/I  
(7)  
C/I  
(6)  
C/I CR1 (*)CR1 (*)CR1  
Vd3000 = drop due to internal HV (L3000N,  
L3000S, STLC3170) architecture  
(2.8V typ.)  
(5)  
(7)  
(3)  
1/0  
1/0  
(2)  
1/0  
1/0  
ACTIVE  
0
0
1
1
0
X
ACTIVE + TTX  
1
X
VdAC = AC headroom on Vout (170mV typ.)  
(*) This condition refers to STLC3040 only. If CR1.3 and CR1.2 are  
equal (either 0 or 1) both STLC3040 and HV (L3000N, L3000S,  
STLC3170) are in Active State. If CR1.3 and CR1.2 are different, one  
of two line wires will be set in high impedance, while the STLC3040  
will still be in Active mode.  
VdTTX = TTX headroom on Vout (from 0 to 465mV  
(15x31) typ. depending on programmed TTX level).  
At HV (L3000N, L3000S, STLC3170) two wires  
the following equation must be used:  
Current Limit and Off-Hook threshold are pro-  
grammable by CR6 register. If the fifth bit of the  
Command-Indicate channel is set to 1 the Teletax  
Signal is superimposed to the voice signal.  
VDROP(TIP/RING) = 9.6V + CR10 [7..3] 15mV 40.  
4.3.2.2 - Metering Generation  
TTX signal is internally generated, filtered and  
shaped. Shaping is carried out by a gradual in-  
crease of metering pulse level of a level step (see  
CR10 register) per signal half period (please see  
Fig. 6). TTX can be programmed both in fre-  
quency (12 or 16 KHz ) and open loop amplitude  
(from 0 to 10Vrms in 255 steps). The output im-  
pedance at TTX frequency is just 2 x Rp; there-  
fore the proper value should consider the drops  
4.3.2.1 - DC feeding  
As far as DC characteristic is concerned, SLIC is  
basically working as a constant current device. It  
turns automatically into a resistive feeding when  
the programmed current limitation value cannot  
be held due to high line resistance. In active  
mode the constant current value is programmable  
Figure 6: TTX Shaping  
V  
SS  
V  
S
TIM  
D96TL265A  
V 2 CR10 LSB  
S
V PROGRAMMED VOLTAGE AS PROG IN CR10  
SS  
8/49  
STLC3040  
across the 2Rp. Filtering is performed inside the  
device without external circuitry.  
sent to C/I upstream.  
Feeding voltage polarity can be reversed in both  
soft and hard ways under software command.  
4.3.3.2 - Power Reduced Ring  
The modes in Table 6 differ only during the ring-  
pause phase.  
During the pause of reduced-power-ring mode the  
SLIC Kit is set in Stand-By.  
The pause state is forced by stop ring command  
(C/I.5 downstream = 0) or by the detection of Off-  
Hook.  
4.3.2.3 - Boost Battery  
To supply very long lines (high loop resistance),  
the SLIC can be set in "Boost battery" mode. In  
this mode the line is fed with a total battery volt-  
age equal to |Vb+| + |Vb-|, keeping the same cur-  
rent limiting values as in active mode. The Vb+  
battery is the same positive supply voltage  
needed for ringing generation.  
4.3.3.3 - Unbalanced Ringing  
The device allows an unbalanced Ring applica-  
tion. This application requires an external ringing  
generator. A digital I/O pin can be used to drive  
the external relay driver.  
An external ring sync. signal synchronised on the  
Vring zero crossing, must be provided on pin 29  
of STLC3040. The external ring frequency must  
be the same as the value programmed in the in-  
ternal register.  
4.3.3 - RING  
In this mode COFISLIC provides ringing signal  
equivalent to a maximum 85Vrms ring line volt-  
age. HV L3000N and L3000S handle a maximum  
65Vrms balanced ring signal; HV STLC3170 han-  
dles a maximum 85Vrms. It is possible to reduce  
power consumption if Power Reduced Ring mode  
is chosen. The output impedance is represented  
only by the two Rp protection resistors and the  
current is limited to 100mA.  
4.4 - TESTING FEATURES  
C/I and CR1 register configuration (programmed  
by GCI monitor channel) define Ring conditions  
as herebelow shown:  
STLC3040/HV (L3000N, L3000S, STLC3170) kit  
allows to perform up to 11 tests. They are aimed  
at covering the following issues.  
1. Line and Battery Characteristics AC, DC  
Leakage.  
Table 6:  
SLIC MODE  
C/I  
(7)  
C/I  
(6)  
C/I CR1 CR1(*) CR1(*)  
(5)  
(7)  
(3)  
(2)  
2. SLIC Kit block testing.  
3. Signal Path Behavior  
Every test is set by internal registers, which are  
written through GCI data down Monitor.  
RING  
1
1
1
0
X
X
1/0 1/0  
1/0 1/0  
Reduced Power  
Ring  
X
X
Test results are typically digitalized, codified and  
dropped in the first PCM channel (byte B1) of GCI  
interface. For four go/nogo tests (Analog Loop-  
back, Ring Generator, TTX Generator and TTX  
filter) the result of the test is also written in one bit  
of CR5 register that is readable through Monitor.  
Test functions are carried out with SLIC Kit in a  
mode set automatically by COFISLIC. For detailed  
explanation about tests see chapter 6.  
(*) CR1.3 has to be equal to CR1.2 : 0 or 1  
If unbalanced ringing is requested, SLIC can sup-  
port also external ringing injection configuration,  
providing both logic command for relay driver and  
ringing detection circuitry.  
4.3.3.1 - Ring Generation  
When the ringing function is selected, a low level  
ringing signal (1.5Vrms typ.) is generated inside  
the STLC3040 and provided on the VOUT pin.  
This signal is then amplified and injected in bal-  
anced mode into the line through the HV  
(L3000N, L3000S, STLC3170), with superim-  
posed DC voltage of 24V typical. Both ringing fre-  
quency and amplitude are software programma-  
ble.  
4.4.2 - Loop Backs  
LOOP1 and LOOP2 bits of CR4 register set up  
some internal loop backs. This feature is typically  
used for COFISLIC tests (see fig. 3).  
Any Loopback is enabled by CR1.5 bit. Loopback  
type is selected by register CR4.  
There are three types of loopback.  
The first and the last ring cycles are synchronized  
by the STLC3040 so that the ringing signal al-  
ways starts and stops with zero phase.  
In Ring mode the Off Hook indication is asserted  
whenever during two consecutive ring periods ( or  
an equivalent time in pause) the mean value of  
the IT current exceedes the programmed thresh-  
old. After the persistance time the Off Hook is  
Loopback 1 (CR4.2 = 0, CR4.1 = 1) simply copies  
the downstream B1 to the upstream B1 through  
the GCI interface. In this case no Rx signal is sent  
to the line. The kit operates as previously set.  
Loopback 2 (CR4.2 = 1, CR4.1 = 0) sets Kit SLIC  
in Active mode. It copies the output of DSD (Digi-  
tal Sigma Delta converter) to the input of the DEC  
9/49  
STLC3040  
block, as shown in fig. 3. Rx signal goes on to the  
line. Please note that this loopback function cuts  
off the Tx channel connection to the line.  
4.5.1.3 Reset bit RST (SOP command bit 4)  
If RST bit is programmed to 1 COFISLIC is reset.  
SOP register is set by GCI down stream channel.  
All other functionalities are those of Active mode.  
Until the end of the current command processing,  
the GCI is kept active.  
Loopback 3 (CR4.2 = 1, CR4.1 = 1) sets Kit SLIC  
in Active mode. Rx signal is prevented to go the  
line. Tx path is cut off from the line as well. Output  
of ASD is copied to input of AFE port filter. DSP  
part can be still exercised via B1. All the function-  
alities are those of active mode.  
4.5.1.4 - CLK fail Reset  
Clock fail triggers a reset routine of the DSP  
which lasts, until the first good frame that follows  
the failed ones.  
In active mode during the Reset routine, the voice  
channel of "Data up" (Du, pin 6) is forced IDLE  
dependent on the selected codification law.  
4.4.3 - Test Tones Generation  
In Active mode STL3040 can generate either  
1kHz or 800Hz frequencies towards the 2-wire  
line. The two tones can also be enabled at the  
same time.  
As far as "Data down" (DD, pin 5) is concerned,  
the voice channel does not reach the Vout during  
this phase.  
TON bit of CR1 register enables the 1 kHz test  
tone generator. 800Hz is enabled by CR5[3.0] =  
4h.  
800Hz amplitude is programmable through the  
same register (CR10) used to set TTX amplitude.  
1kHz level is fixed at PCM full scale and can be  
modified changing Rx channel gain.  
Z sinthesys is partially performed, the DSP  
branch is not active while the analog loop is kept  
active.  
Coefficients and CR registers’ contents do not  
change because of this partial reset, GCI state as  
well. Metering pulse injection signaling is not af-  
fected too. Ring generation and ring trip detection  
are not influenced too.  
4.5 COFISLIC Reset  
Any reset to COFISLIC sets SLIC kit in External  
Indication. COFISLIC is set in Power denial.  
There are four different reset sources:  
4.5.2. Start-up State  
During reset the device is in Power- Denial Mode.  
After Reset, COFISLIC is automatically switched  
to its basic start-up state in which it uses internal  
default values for all filters and settings (AC and  
DC).  
Power-On Reset,  
Reset pin MR (pin 36),  
Reset bit (SOP command bit 4).  
During Reset, output pins are set as follows:  
Programmed coefficients of filters are not reset.  
Bit 0 of CR6 register, FIXC, is set to 1, this means  
that fixed values are used after a Reset until FIXC  
is set to 0.  
Even if FIXC = 1, both checksum and reading of  
filter coefficients are carried out on formerly pro-  
grammed coefficient set.  
DU  
C1  
(pin 6)  
High impedance  
Vhv  
(pin 9)  
C2  
(pin 10)  
(pin 28)  
( pin 39)  
Vhv  
PDO  
O1  
High impedance  
Low Level  
Table 7: Fixed Filter Coefficients  
Additionally a Reset of the DSP part of the  
COFISLIC is triggered by CLK fail detection (see  
also page 17).  
Filter  
Coefficients (h)  
KA, KD 0E00  
Z
X
019C, 24A0, 1600  
149A, 0521, 3F40,3EF2  
4.5.1.1 Power On Reset  
When voltage at VDD pin crosses over an internal  
fixed threshold (typ. 2.5V) COFISLIC is reset.  
R
1879, 39E0, 00B4,0006  
GTX  
GRX  
B
FF  
60  
4.5.1.2 Reset Pin MR  
If an high level is applied to pin 36 (MR) the  
COFISLIC is reset.  
MR pin has built-in filter to reduce spike sensitiv-  
ity. Spikes smaller than 90ns are neglected.  
0, 0, 0, 0050, 0680, 06D0, 0, 3C80  
SLIC is switched to operating mode carried by  
GCI Command Indicate at least two frames after  
reset. SLIC status and Filter configuration can be  
changed by SOP and COP commands.  
Therefore at MR pin a high level is surely recog-  
nised as a Reset if it is present for at least 2 s.  
After reset the device is internally set as follows:  
- configuration registers are set to their default  
µ
10/49  
STLC3040  
values (see Chapter 4-8 Configuration Regis-  
ter)  
Check Configuration-registers reset-value for  
more detailed information.  
- RST bit (SOP command bit 4) is set to 1 to in-  
dicate that a reset has occured  
- GCI interface is reset. After software Reset its  
former state is kept. On-going GCI communi-  
cation is stopped  
4.6 GCI Backplane Interface  
GCI is a standard serial interface for interconnec-  
tion of SLIC kit to the line card backplane.  
The digital interface is used to transfer status in-  
formation to and from the SLIC as well as to  
transfer filter coefficients for the DSP.  
With this approach an analog Line Card could be  
replaced by an ISDN one and viceversa without  
need to change the interface to the linecard con-  
troller.  
- DU is in high impedance state  
- FIXC = 1 (CR6 Register) Fixed Coefficients  
are selected  
– DC characteristics of SLIC-Kit  
- External Indication  
- Normal Battery  
As far as physical level is concerned this standard  
consists of four wires:  
- Serial Transmitted data to the backplane: DU  
- Serial Received data from the backplane: DD  
- 8KHz Frame Synchronization: FSC  
- Test Disabled  
- Persistence for Off-Hook and I1: 10ms  
- Persistence for Ground Key: 20ms  
- Ring Trip threshold = 4.2mA  
- Ilim = 22mA in active mode  
- Ilim = 7.7mA in Stand-By mode  
- Master Data Clock (2048KHz or 4096KHz): DCL  
The frame is divided into eight time-slots which  
contains four bytes each. Bit rate in both direc-  
tions is 2048Kbit/sec and it’s not affected by clock  
frequency. This can be chosen setting SEL24 pin.  
Eight GCI time slots are selectable via three pins  
TS2-TS0 (see Table 8).  
- Off-Hook detection threshold in active mode =  
10mA  
For every time slot the first bit, received or trans-  
mitted, is the Most Significant one, according to  
timing diagram shown in fig. 7.  
Information is clocked out on the rising edge of  
data clock and it is latched in on the falling edge  
of DCL signal.  
Frame Synchronization FSC is a 8KHz signal and  
its rising edge gives the time reference of the first  
bit in the first GCI (input or output) channel and  
resets the slot counter at the next falling edge of  
the clock every frame.  
- Off-Hook detection threshold in Stand-By  
mode = 7.7mA  
- Feeding Resistance in either Active or Stand-  
By mode = 2 (50 + Rp) (fuse impedance  
value is not included)  
- Ring: Internal  
- Ring Frequency = 25Hz  
- Ring Voltage = 65Vrms  
- Line Voltage Drop = 28.2V  
- External Indication Voltage Threshold for Off-  
Hook detection = 9.0V  
- A-law is programmed  
Four bytes of any GCI time slot are:  
- B1 channel for PCM data,  
- B2 channel not used,  
- M (Monitor) channel used to write and monitor  
COFISLIC internal registers,  
- C/I (Command/Indication) channel used to set  
the Operating Mode.  
AC characteristics of SLIC-Kit  
- Metering with Teletax  
- Line Impedance: (Synthetized Impedance + 2  
Rp) = 700 + 2Rp  
8bits  
B1  
8bits  
B2  
8bits  
MONITOR  
Byte 3  
6bits  
C/I  
1bit  
A
1bit  
E
- Balance Impedance: 910 / / 62nF  
- Tx Gain: 0dBr  
- Rx Gain: -7dBr  
Byte 1 Byte 2  
Byte 4  
- Teletax Voltage onto line VTTX = 10Vrms  
- Teletax Frequency = 16kHz  
- Battery Reversal: Hard  
A single GCI channel has 256kbit/s data rate.  
Exchange Protocol  
Further after the reset  
- I/O pins are set as inputs  
STLC3040 validates a received byte if it is detected  
identical two consecutive times. (see figg. and 7and 8)  
- PD bit of CR1 is reset (means STLC3040 in  
Power-Denial mode).  
- All bits of Signalling Register are masked  
- Data Upstream C/I byte is reset to 0  
The exchange protocol is identical for both direc-  
tions. The sender uses the E bit to indicate that it  
is sending a Monitor byte while the receiver uses  
A bit to acknowledge the received byte. When no  
11/49  
STLC3040  
Table 8: GCI Time Slot assignment.  
SEL24  
TS2  
TS1  
TS0  
GCI operating mode  
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
time slot 0:DCL = 2048kHz  
time slot 1:DCL = 2048kHz  
time slot 2:DCL = 2048kHz  
time slot 3:DCL = 2048kHz  
time slot 4:DCL = 2048kHz  
time slot 5:DCL = 2048kHz  
time slot 6:DCL = 2048kHz  
time slot 7:DCL = 2048kHz  
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
time slot 0:DCL = 4096kHz  
time slot 1:DCL = 4096kHz  
time slot 2:DCL = 4096kHz  
time slot 3:DCL = 4096kHz  
time slot 4:DCL = 4096kHz  
time slot 5:DCL = 4096kHz  
time slot 6:DCL = 4096kHz  
time slot 7:DCL = 4096kHz  
Figure 7.  
GCI Interface Timing (DCL = 2048KHz, SEL24 = 0)  
125µs  
FSC  
DCL  
2048KHz  
TS0  
TS1  
TS1  
TS2  
TS2  
TS3  
TS3  
TS4  
TS4  
TS5  
TS5  
TS6  
TS6  
TS7  
TS7  
DD  
DU  
TS0  
Detail C  
Detail C  
FSC  
DCL  
DD/DU  
Bit 0  
Bit n  
Bitn - 1  
D95TL210A  
12/49  
STLC3040  
Figure 7. (continued)  
GCI Interface Timing for 8 voice channels (per 8 KHz frame)  
125µs  
FSC  
DCL  
4096KHz  
TS0  
TS0  
TS1  
TS1  
TS2  
TS3  
TS4  
TS4  
TS5  
TS5  
TS6  
TS6  
TS7  
TS7  
DD  
DU  
TS2  
TS3  
Detail A  
Detail A  
DD  
Voice Channel  
Voice Channel  
don't care  
Monitor Channel C/I Channel A E  
DU  
High Impedance Monitor Channel C/I Channel A E  
GCI Interface Timing (DCL = 4096KHz, SEL24 = 1, per 8 KHz frame)  
125µs  
FSC  
DCL  
4096KHz  
TS0  
TS1  
TS1  
TS2  
TS2  
TS3  
TS3  
TS4  
TS4  
TS5  
TS5  
TS6  
TS6  
TS7  
TS7  
DD  
DU  
TS0  
Detail B  
Detail B  
FSC  
DCL  
DD/DU  
Bit 0  
Bit n  
Bit n-1  
D95TL209A  
13/49  
STLC3040  
message is transferred, E bit and A bit are forced  
to inactive state (high = 5V).  
the B1 channel on DD pin and outputs PCM bytes  
on DU pin.  
A transmission is started by the sender (Transmit  
section of the Monitor channel protocol handler)  
by putting the E bit from inactive to active state  
(low = 0V) and by sending the first byte on Moni-  
tor channel in the same frame. Transmission of a  
message is allowed only if A bit, sent from the re-  
ceiver, has been set inactive for at least one con-  
secutive frame. When the receiver is ready, it vali-  
dates the incoming byte when received identical  
in two consecutive frames. Then, the receiver  
sets A bit from the inactive to the active state  
(preacknowledgement) and maintain active at  
least in the following frame (acknowledgement).  
4.6.1.2 Linear codification  
STLC3040 allows Linear codification simply set-  
ting two bits of CR12 register.  
COMTX (bit 0) enables the linear code in trans-  
mission, while COMRX (bit 1) enables the linear  
code in receive.  
STLC3040’s linear code consists of 16 bits which  
means a range from (-215) to (215-1) Linear Code  
is housed in B1 and B2 channels, B1 is the least  
significant byte end B2 is the most significant  
byte.  
If validation is not possible (two last bytes re-  
ceived are not identical) the receiver aborts the  
message by setting the A bit active for only a sin-  
gle frame.The second byte can be transmitted by  
the sender putting the E bit from the active to the  
inactive state and sending the second byte on the  
Monitor channel in the same frame . The E bit is  
set inactive for only one frame. If it remains inac-  
tive more than one frame, it means an end of  
message. The second byte may be transmitted  
only after receiving of the pre-acknowledgement  
of the previous byte . Each byte has to be trans-  
mitted at least in two consecutive frames.  
15 bits are dedicated to the module while the  
most significant bit is the sign bit.  
If bit 15 (sign bit) = 0 bit 14.....bit 0 represent the  
module.  
If bit 15 = 1 module is got by 2-complementing bit  
14 ...... bit 0.  
4.6.2 C/I Channel  
Command/Indicate byte is a 6 bits wide command  
full duplex transmission.  
Internal C/I registers will be loaded if downstream  
command is stable for two frames.  
The receiver validates the current received byte  
as for the first one and then set the A bit in the  
next two frames first from the active state to the  
inactive state (pre-acknowledgement) and back to  
the active (acknowledgement). If the receiver can-  
not validate the received current byte (two bytes  
received not identical)it pre-acknowledges nor-  
mally but lets the A bit in the inactive state in the  
next frame which indicates an abort request . If a  
message sent by the COFISLIC is aborted, the  
COFISLIC will send again the complete message  
until receiving of an acknowledgement . A mes-  
sage received by the COFISLIC can be acknow-  
ledged or aborted with flow Control.  
The most significant bit (MSB) of Monitor byte is  
sent first on the Monitor channel. E & A bits are  
active low and inactive state on DU is 5 V. When  
no byte is transmitted, Monitor channel time slot  
on DU is in the high impedance state.  
The GCI interface transmitter will abort after 8  
times during which it hasn’t succesfully received  
any acknowledge from the device upstream. The  
GCI interface receiver will go in abort request  
mode after 8 times of unsuccessful attempts to  
get 2 identical copies of the data. This means that  
after 8 frames of unsuccessful handshake, the  
GCI interface transmitter will abort while the re-  
ceiver will make a request for abort.  
Also upstream Command/Indicate byte lasts for at  
least two consecutive 8KHz frames. Com-  
mand/Indicate is mainly used to set SLIC operat-  
ing mode and to monitor subscriber On/Off-Hook  
and Ground-Key detection.  
Any change of line conditions like On-Off/Hook  
and Ground Key is signalled via upstream C/I.  
HOOK and GNDK bits always reflect line condi-  
tions even if corresponding bits of Signalling Reg-  
ister are masked by CR12 register. Bit 5 of up-  
stream Command/Indicate says that at least one  
of Signalling Register six most significant bits has  
changed its logical value.  
Bit 5 of upstream Command/Indicate does not  
change if related bits of Signalling Register have  
been masked by CR12 register.  
Input/Output pins (IO1/2,I1,O1) can be set and  
monitored by C/I channel too. Note that there is  
no address in both directions because there is  
one GCI time slot per each COFISLIC.  
C/I channel in Downstream direction consists of  
six bits as shown below :  
BIT7  
BIT6  
BIT5  
TIM  
BIT4  
IO1  
BIT3  
IO2  
BIT2  
O1  
RING  
CONV  
Basically the first 3 Most significant Bits of C/I  
downstrean operate as follows. For a complete  
description please refer to Table 13.  
4.6.1 B1/B2 Channels  
4.6.1.1 PCM codifications  
GCI interface extracts receiving PCM data from  
14/49  
STLC3040  
Figure 8: GCI Monitor Channel messaging examples.  
X
M1  
M1  
M2  
M2  
X
X
X
M
E
A
1st byte  
(M1)  
2nd byte  
(M2)  
3rd byte??  
(X)  
EOM  
pre-ack  
(M2)  
ack  
pre-ack??  
(X)  
Ready for  
a new message  
Ready  
for a message  
pre-ack  
(M1)  
ack  
(M2)  
(M1)  
TWO BYTES MESSAGE - NORMAL TRANSMISSION  
X
M1  
M1  
M2  
M2  
X
X
M1  
M1  
M2  
X
X
M
E
A
1st byte  
(M1)  
1st byte  
(M1)  
2nd byte  
(M2)  
EOM  
(or abort ack)  
3rd byte??  
(X)  
Ready for  
a message  
Ready for  
retransmission  
pre-ack  
(M1)  
ack  
(M1)  
pre-ack  
(M2)  
abort  
(M2)  
pre-ack  
(M1)  
TWO BYTES MESSAGE ABORTED ON THE SECOND AND RETRANSMITTED  
M1 = start Byte  
E & A BITS TIMING  
RING = Sets COFISLIC into ringing state.  
= 0 COFISLIC is not in ringing state.  
= 1 COFISLIC is in ringing state.  
IO1, IO2 define the value for the programmable  
Input/Output pins (7, 8) if programmed as output  
pins by CR2 register.  
CONV = Sets COFISLIC into power up state.  
= 0 COFISLIC is in a power down state.  
= 1 COFISLIC in power up state.  
TIM = Timing bit to control the timing of ringing  
and meterpulses.  
IO1 = 0 The related pin 7 at the digital interface  
of the COFISLIC is set to a logic 0  
= 1 The related pin 7 at the digital interface  
of the COFISLIC is set to a logic 1  
IO2 = 0 The related pin 8 at the digital interface  
of the COFISLIC is set to a logic 0  
= 1 The related pin 8 at the digital interface  
of the COFISLIC is set to a logic 1  
= 0 COFISLIC is in ringing pause  
or no meterpulse is on.  
= 1 COFISLIC is in ringing  
or output of a meterpulse is running.  
O1 sets value for fixed output pin 39  
15/49  
STLC3040  
channel transfers: SOP, COP, TOP.  
= 0 The related pin 39 at the digital interface  
of the COFISLIC is set to a logic 0  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
= 1 The related pin 39 at the digital interface  
of the COFISLIC is set to a logic 1  
X
R/W  
X
X
B3  
B2  
X
X
R/W = 0  
= 1  
Write Operation  
Read Operation  
C/I channel in Upstream direction is herebelow  
described:  
B3  
0
B2  
1
BIT7  
BIT6  
BIT5  
BIT4  
IO1  
BIT3  
IO2  
BIT2  
I1  
SOP command  
TOP command  
COP command  
HOOK GNDK SLCX  
1
1
X
0
HOOK indicates loop condition:  
= 0 Subscriber is On-Hook  
= 1 Subscriber is Off-Hook  
GNDK indicates Ground Key detection:  
= 0 No Detected Longitudinal Current  
= 1 Detected Longitudinal Current  
For SOP, COP, TOP commands the Start Byte is  
81 in DU directions.  
SOP commands set and monitor COFISLIC  
status.  
TOP commands read Signalling register and co-  
efficient checksum.  
COP commands set and read filters coefficient.  
SOP and COP can be either write or read com-  
mands, while TOP is used only for reading.  
A write command (SOP and COP) can be fol-  
lowed by up to 14 bytes. An answer to SOP,  
COP, TOP commands consists of maximum 16  
bytes. First byte is always the start byte (81h).  
SLCX is the summary output of the signalling reg-  
ister (See TOP command)  
= 0 No unmasked bit in signalling register has  
toggled  
= 1 An unmasked bit in signalling register, has  
toggled, it is reset only if SR register is read.  
Registers from CR1 to CR12 are accessed by  
SOP command both in reading and writing. TOP  
command is used to read the Signalling Register  
and the Coefficient Checksum. The RAM, where  
filters coefficient are stored, is accessed by COP  
commands.  
A fourth command of the Monitor Channel is the  
so called Channel Identification Command (CIC).  
This command will be run if the COFISLIC re-  
ceives the following code on the Monitor Channel  
for at least two frames:  
IO1,IO2 give logical state of programmable In-  
put/Output pins (7, 8)  
IO1 = 0 Corresponding pin 7 at digital  
interface of COFISLIC is receiving  
a logic 0  
= 1 Corresponding pin 7 at digital  
interface of COFISLIC is receiving  
a logic 1  
IO2 = 0 Corresponding pin 8 at digital  
interface of the COFISLIC is receiving  
a logic 0  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
= 1 Corresponding pin 8 at digital  
interface of COFISLIC is receiving  
a logic 1  
1
0
0
0
0
0
0
0
Upon CIC command is received COFISLIC will  
place two bytes on DU line, each byte is repeated  
at least twice.  
If as per CR1 register IO1 and IO2 are pro-  
grammed as outputs, data up command indicate,  
IO1 and IO2 are set to 1  
I1 gives logical state of fixed input pin 38.  
= 0 pin 38 is receiving a logic 0.  
BIT7 BIT6 BIT5 BIT4 BIT3  
BIT2  
BIT1  
BIT0  
1
0
0
0
CONF(3) CONF(2) CONF(1) CONF(0)  
= 1 pin 38 is receiving a logic 1.  
This byte replaces usual Start byte. Low nibble  
CONF(3)-CONF(0) defines the identification code  
according to the logic values of three input pins  
IDH (pin 35), IDL and IDM (pin 31 and 32).  
4.7.1 Monitor-Channel (M-channel)  
As already mentioned COFISLIC can be pro-  
grammed and monitored via GCI Monitor.  
Data transfer from and to STLC3040 starts with a  
specific byte, called Start Byte:  
Herebelow it is the Table of Identification:  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
1
0
0
0
0
0
0
X
In downstream a second byte selects one of the  
three different kinds of commands which Monitor  
16/49  
STLC3040  
Table 9:  
SIGNALLING REGISTER (SR)  
SR provides information about loop condition:  
Off/OnHook condition, line constant current, line  
voltage. It also signals temperature alarm related  
to HV SLIC (L3000N, L3000S, STLC3170) and  
clock fails (see page 10). The Clock fail indication  
is set whenever the number of DCL periods in  
one frame (between two-FSC pulses) is different  
from the standard one.  
Hook and Ground Key state variations toggle the  
related bits of SR register and therefore switch  
HOOK and GNDK bits of upstream C/I.  
Every change of any of the six most significative  
bits of SR register is summarized in SLCX bit (bit  
5) of upstream Command/Indicate, provided that  
these bits are not masked by CR12 register.  
Masking acts only on SLCX bit.  
IDH  
+5V  
+5V  
+5V  
+5V  
+5V  
+5V  
+5V  
+5V  
0V  
IDM  
-5V  
-5V  
-5V  
0V  
IDL  
-5V  
0V  
Id. Code  
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
+5V  
-5V  
0V  
0V  
0V  
+5V  
-5V  
0V  
+5V  
+5V  
+5V  
+5V  
0V  
0V  
0V  
-5V  
+5V  
0V  
0V  
0V  
0V  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
0V  
0V  
-5V  
+5V  
0V  
HOOK GNDK VB_2 ILIM TEMP CK_FAIL XX  
XX  
0V  
-5V  
-5V  
-5V  
Reset Value: 00h  
0V  
0V  
-5V  
HOOK indicates loop condition (same as in up-  
stream C/I):  
= 0 Subscriber is On-Hook  
= 1 Subscriber is Off-Hook  
Data transfer is completed by the next byte:  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
1
0
0
0
1
0
0
0
GNDK shows a Ground Key detection (same as  
in upstream C/I):  
= 0 No Detected Longitudinal Current  
= 1 Detected Longitudinal Current  
4.7.1.1 TOP Command  
As above mentioned TOP command allows read-  
ing Signalling Register and Coefficient RAM  
checksum.  
VB_2 half battery voltage across the line is detected  
VOL  
(VLINE compared to  
).  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
2
X
R/W  
X
X
1
1
LSEL1 LSEL0  
This bit is designed to indicate the line DC operat-  
ing point only in Stand-By and Active modes, with  
no TTX injection  
R/W = 0 No Operation  
= 1 Read Operation  
VOL  
LSEL1  
0
LSEL0  
0
= 0 if (|VLINE|<|  
= 1 if (|VLINE|>|  
|)  
|)  
2
VOL  
2
1 byte for signalling register  
reading  
0
1
1 byte for signalling register and  
2 bytes for filter coefficients  
checksum reading, low byte is  
read first and then high byte.  
where: |VLINE| = |VTIP - VRING|  
|VOL| = |VBAT-VDROP|  
ILIM Current Limit Region  
This interrupt is automatically masked in Ringing  
Mode  
= 0 Resistive Feeding Region  
1
0
15 bytes for Line Card  
Identification Code reading  
In answer to TOP command COFISLIC will place  
the Start byte first.  
Coefficient checksum is defined by this algorithm:  
= 1 Constant Current Feeding Region  
X16 X10 X7  
X
1
TEMP Temperature alarm of HV SLIC (L3000N,  
L3000S, STLC3170) which is signalled through  
HV (L3000N, L3000S, STLC3170) interface  
This algorithm guarantees a fault coverage of:  
(1 - 2-15  
)
= 0 Normal Temperature  
17/49  
STLC3040  
command the SOP is started by Start Byte, in  
downstream, followed by a byte that sets the SOP  
register.  
= 1 Temperature Alarm from HV (L3000N,  
L3000S, STLC3170)  
SOP register:  
CK_FAIL Receiving Clock and/or Synchronization  
signals failures  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
= 0 no Detected Clock or Sync fails  
= 1 Detected Clock or Sync fails  
Bits ILIM, TEMP, VB_2 have 7ms persistance  
fixed.  
X
R/W POL RST  
0
1
LSEL1 LSEL0  
R/W = 0 Write to Cofislic  
= 1 Read Operation  
POL = 0 Normal Polarity Feeding  
4.7.1.2 COP Command  
= 1 Reverse Polarity Feeding  
RST = 0 Normal Operation  
Every COP command is started by the Start Ad-  
dress. A second byte contains the RAM address  
related to the programmable filters.  
Address is defined by the least significative five  
bits except the third one which identifies a COP  
command.  
= 1 Reset, set the COFISLIC to the basic  
setting mode  
After a reset, RST is set to 1. RST is toggled to 0  
after a SOP read operation with LSEL bits pro-  
grammed to 00b.  
COP commands consist of maximum 14 bytes  
used to set and monitor digital filter coefficients.  
If R/W = 0  
Write to COFISLIC  
No byte is following  
COP register:  
LSEL1  
LSEL0  
0
0
0
1
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
Two bytes, which write CR1 and  
CR2 Registers, follow  
X
R/W COD5 COD4 COD3 COD2 COD1 COD0  
R/W = 0 Subsequent bytes are written to  
COFISLIC  
1
1
0
1
12 bytes, which set CR1,.,CR12  
registers, follow  
= 1 Subsequent bytes are read from  
COFISLIC  
Not available  
COD2 = 0 Identifies a COP command COD5,  
COD4, COD3, COD1, COD0 bits identify filters  
address as shown here below (Table 10).  
If R/W = 1  
LSEL1  
0
Read from COFISLIC  
LSEL0  
0
Replies the SOP * command  
received by COFISLIC  
For every coefficient, but B filter, with 14bit width  
the Least significant Byte is sent first. In the Most  
Significant Byte the first two bits must be stuffed  
with 0.  
0
1
1
1
0
1
Replies the SOP * command  
received by COFISLIC, followed  
by two bytes: CR1, CR2  
Registers  
For B Filter the 14 bytes are the result of the con-  
catenation of the 8 coefficients of 14 bits  
Replies the SOP * command  
received by COFISLIC, followed  
by twelve bytes: CR1, CR2  
CR12 Registers  
4.7.1.3 SOP Command  
Reading and writing of CR and SOP register is  
performed via SOP commands. Configuration,  
operation and test data can be set and updated  
by this command. As for every Monitor channel  
Not available  
SOP *: during the on going SOP command SOP* is  
the previously processed SOP command.  
Table 10:  
COD5  
COD4  
COD3  
COD1  
COD0  
ADDRESS  
Filter B  
Following Bytes  
0
0
0
0
1
0
1
0
0
0
1
0
1
0
0
0
1
1
0
1
0
0
1
0
1
0
0
1
1
1
1
1
1
1
1
14  
8
Filter R  
Filter X  
8
Filter GR  
Filter GX  
Filter KA, KD  
Filter Z  
1
1
2
6
Filters coefficients must be evaluated using a proper ST simulation software.  
18/49  
STLC3040  
XVA OKTON OKTTX OKRNG TMN NOSL IO1 IO2  
Reset value: 00h  
4.8 Configuration Registers  
As already mentioned, Configuration Registers  
are set and read by SOP command.  
XVA Internal measurement results shown in the  
following three bits are or not valid (read only)  
CR1 sets SLIC kit operating features and some  
test features.  
= 0 the following 3 ok-bits are not valid  
= 1 the following 3 ok-bits are valid  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
PD N/BB LB  
TON HIA  
HIB DHP COR  
OKTON Test Tone meaurement information (read  
only), see test mode 7  
Reset value = 00 h.  
PD sets the kit either in Stand By or External Indi-  
cation/Loop open (for further details please see  
table 13 pag. 45)  
= 0 Test tone level out of defined range  
= 1 Test tone level in defined range  
= 0 SLIC kit (STLC3040/HV (L3000N, L3000S,  
STLC3170)) in External Indication Mode  
= 1 SLIC kit (STLC3040/HV (L3000N, L3000S,  
STLC3170)) in Stand By Mode  
OKTTX Test teletax metering information (read  
only), see Test Mode D and E  
= 0 Test teletax metering different from the  
defined value  
= 1 Test teletax metering equal to the  
defined value  
N/BB sets COFISLIC Battery Mode  
= 0 Normal Battery  
OKRNG Test Ring tone information (read only),  
see Test Mode C  
= 1 Boosted Battery  
= 0 Ring tone level out of defined range  
= 1 Ring tone level within the defined range.  
LB enables Loop Back functions for on chip test  
= 0 normal function (no loop back)  
= 1 Loop Back as defined in CR4 register  
TMN Enables or disables COFISLIC testmodes  
(see chapter 6)  
= 0 stops the assigned tests (normal mode)  
= 1 starts the assigned tests selected by Regis-  
ter CR5  
TON enables 1KHz test tone generator  
= 0 Test Tone Generator Off  
= 1 Test Tone Generator On  
HIA and HIB set tip and ring status in active and  
standby mode  
NOSL Defines if the shaping of teletax signal is  
switched On or Off  
= 0 Teletax shaping is on  
Standby  
Active  
HIA  
0
HIB  
0
TIP  
RING  
normal  
Hiz  
TIP  
RING  
normal  
Hiz  
= 1 Hard switch of Teletax signal  
normal  
normal  
0
1
normal  
normal  
IO1 Selection for programmable I/O pin IO1  
= 0 sets pin IO1 as input  
= 1 sets pin IO1 as output  
negative  
negative  
1
1
0
1
Hiz  
Hiz  
normal  
normal  
Hiz  
normal  
normal  
normal  
DHP enables High-Pass filter for test purpose  
= 0 High Pass filter On  
= 1 High Pass filter Off  
IO2 Selection for programmable I/O pin IO2  
= 0 sets pin IO2 as input  
= 1 sets pin IO2 as output  
COR cuts off Receive Path for test purpose  
= 0 Receive Path transmission is enabled  
= 1 Receive Path is disable  
CR3 sets Persistence Check for upstream signal-  
ling: Off-Hook and Ground-Key.  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
DUP3 DUP2 DUP1 DUP0 DUB3 DUB2 DUB1 DUB0  
CR2 enables or disables Test Mode, Teletax Sig-  
nal Shaping Mode and sets the I/O pin direction.  
The high nibble is only readable and defines test  
mode results.  
Reset value: A5 h  
Persistence Reset value is 10 ms both for Off-  
Hook and I1 input pin. 20ms for Ground-Key.  
BIT7 BIT6  
BIT5  
BIT4 BIT3 BIT2 BIT1 BIT0  
19/49  
STLC3040  
Figure 9.  
I1  
I1 AFTER PERSISTENCE  
CHECK ON UPSTREAM  
0
N-1ms  
Nms  
I1  
I1 AFTER PERSISTENCE  
CHECK ON UPSTREAM  
N-1  
N
D96TL264  
0
(HX) is defined by programmed filter  
coefficients (COP command)  
R represents R-filter  
= 0 R-filter is Off, Related Transfer Function  
(HR = 1) is one  
= 1 R-filter is On, Related Transfer Function  
(HR) is defined by programmed filter  
coefficients (COP command)  
GX/GR represents GX/GR-filter  
= 0 GX/GR-filter is Off, Related Transfer  
Function (HGX/GR = 1) is one  
= 1 GX/GR-filter is On, Related Transfer  
Function (HGX/GR) is defined by  
programmed filter coefficients  
(COP command)  
DUP3-DUP0 Persistence check for signalling up-  
stream Off-Hook and I1. New status information  
will be transmitted upstream, after it has been sta-  
ble for from (N-1) to N millisecond (see fig. 9).  
N is programmable in range of 1 to 15 ms in steps  
of 1 ms. DUP3-DUP0 = 0000 means no persist-  
ence check.  
DUB3-DUB0 Persistence check for signalling up-  
stream Ground-Key. New status information will  
be transmitted upstream, after it has been stable  
for N millisecond. N is programmable in range  
from 0 to 60 ms in steps of 4 ms. DUB3-DUB0 =  
0000 means no persistence check.  
CR4 enables internal filters B, Z, X, R, GX/GR. It  
also programs the Loop Back and sets the codifi-  
µ
cation law: A-law or -law.  
LOOP1-LOOP0 select the loop back (see Block  
Diagram fig. 3 and paragraph 4.42)  
BIT7 BIT6 BIT5 BIT4 BIT3  
BIT2  
BIT1 BIT0  
= 00 No loop-Back  
B
Z
X
R
GX/GR LOOP1 LOOP0 A/U  
= 01 Loop-Back only GCI interface (LB1 on).  
= 10 Loop-Back the digital part (Digital  
Sigma-Delta converter is included, LB2 on).  
Reset value: F9h  
B represents B-filter  
= 0 B-filter is Off, Related Transfer Function  
is zero (HB = 0)  
= 11 Loop-Back the Analog part (Analog  
Sigma-Delta converter is included, LB3 on).  
= 1 B-filter is On, Related Transfer Function  
(HB) is defined by programmed filter  
coefficients (COP command)  
A/U chooses coding law  
µ
= 0 -law coding  
= 1 A-law coding  
Z represents Z-filter  
= 0 Z-filter is Off, Related Transfer Function is  
zero (HZ = 0)  
CR5 sets ring-trip thresholds and test modes  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
RTV3 RTV2 RTV1 RTV0 TESM3 TESM2 TESM1 TESM0  
= 1 Z-filter is On, Related Transfer Function  
(HZ) is defined by programmed filter  
coefficients (COP command)  
Reset value: 60h.  
X represents X-filter  
RTV3-RTV0 set Ring-Trip Threshold Value. This  
value is programmable in the range from 9.6/16  
mA to 9.6 mA in steps of 9.6/16 mA.  
= 0 X-filter is Off, Related Transfer Function  
(HX = 1) is one  
= 1 X-filter is On, Related Transfer Function  
20/49  
STLC3040  
threshold in Stand-by mode.  
Programmable range is from 0mA to 69.3mA in  
steps of 1.1mA.  
= 0h corresponds to 9.6/16 mA  
= Fh corresponds to 9.6 mA  
For further details please see parameters IRNGGTH  
(pag 34)  
= 0000 corresponds to 0mA  
= 1111 corresponds to 69.3mA  
At reset the value will be 7.7mA.  
TESM3-TESM0 select the testmode.  
PDDIS used for state setting as per table 14 (pag  
45)  
RTEN enables Ring-trip in test mode TST-IRING  
= 0 Ring-trip disabled  
= 0h  
= 1h  
= 2h  
= 4h  
= 5h  
= 7h  
= 8h  
= 9h  
= Ah  
= Ch  
= Dh  
= Eh  
= Fh  
No-Test  
TST-LEAK [CR8.1 = 0, CR5(3:0) = 01h]  
TST-LKA [CR8.1 = 0, CR5(3:0) = 02h]  
TST-800Hz  
= 1 Ring-trip enabled  
TST-TONE-CAL  
TST-ALB  
CR8 sets synthesized feeding resistance, TTX  
frequencies. The least significant bit sets the ring-  
ing source: internal or external.  
DON’T USED  
TST-LINE-IMPDC  
TST-LINE-IMPAC  
TST-IRING  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
RFED2 RFED1 RFED0 TTX12 TTXNO SOREV XRNG TMM  
TST-PTTX  
Reset Value: 00h  
TST-TTXFILT  
RFED2-RFED0 Values of the synthesized feeding  
resistance‘.  
TST-ILIM  
Every test will be described in Chapter 6  
DC Synthesis Value = 2 Rp + 2 50  
[RFED [2:0] + 1]  
TTX12 selects Teletax frequencies  
= 0 16KHz teletax  
= 1 12KHz teletax  
CR6 sets current limitation values and off-hook  
threshold in Active mode.  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
ILIM5 ILIM4 ILIM3 ILIM2 ILIM1 ILIM0 ITHR FIXC  
TTXNO sets Battery Reversal for metering in-  
stead of 16/12KHz pulse  
=0 Metering with Teletax pulse  
=1 Metering with Battery reversal  
SOREV selects hard or soft Battery Reversal  
= 0 Hard Battery Reversal  
Reset Value: 51h  
ILIM5-ILIM0 Set Current Limit in Active mode.  
Current Limit is programmable in range of 0mA to  
69.3mA in steps of 1.1mA.  
= 000000 corresponds to 0mA  
= 1 Soft Battery Reversal  
= 111111 correspondso to 69.3mA  
ITHR Defines Off-Hook threshold value in Active  
mode  
= 0 Threshold at 10mA  
= 1 Threshold at 13mA  
XRNG selects ringing source: internal or external  
= 0 Internal Ring  
= 1 Ring signal from EXT pin  
TMM enables sign modulation at 1kHz square  
wave of measurement carried out during test mode  
Loop indication is set if a loop current greater  
than 10mA or 13mA is detected.  
FIXC, COFISLIC uses either fixed coefficients or  
programmed ones.  
= 0 No Modulation  
= 1 Modulation enabled  
CR9 programs Ring frequency and amplitude.  
= 0 Programmed coefficients used  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
RVR RNGF2 RNGF1 RNGF0 RNGV3 RNGV2 RNGV1 RNGV0  
= 1 Fixed coefficients used (see paragraph  
4.5.2)  
CR7 sets current-limit value and Off-Hook thresh-  
old in Stand-By mode.  
Reset Value: 2F h  
RVR fixes Ring Voltage Range  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
PDSV5 PDSV4 PDSV3 PDSV2 PDSV1 PDSV0 PDDIS RTEN  
= 0 Ring Amplitude = 34.4Vrms + RNGV [3:0] x  
2.039Vrms  
= 1 Ring Amplitude = 45Vrms + RNGV [3:0] x  
2.66Vrms  
Reset Value is 65 Vrms  
Reset Value: 1Ch  
PDSV5-PDSV0 Set Current Limit and Off-hook  
21/49  
STLC3040  
cleared and two things could happen. If the con-  
tents of the shadow register differ from the en-  
abled SR (meaning there was at least one toggle  
of the enabled SR bits between the time when the  
interrupt bit is set and the TOP READ command),  
then the SR byte will be latched into the shadow  
register while the interrupt bit (SLCX) will remain  
cleared (low) for 2 frames and then will be set  
high. On the other hand, if the contents of the  
shadow-register are equal to the enabled SR,  
then the interrupt bit remains cleared and will be  
set only by the next event. At reset, the shadow  
register content mirrors that of SR register. A  
mask-bit change causes SR to be latched in the  
shadow-Register, nevertheless the SCLX bit is  
cleared  
RNGF2-RNGF0 select Ring frequency value  
= 0h  
= 1h  
= 2h  
= 3h  
= 4h  
= 5h  
= 6h  
= 7h  
16.6Hz Ringing Frequency  
20Hz Ringing Frequency  
25Hz Ringing Frequency  
50Hz Ringing Frequency  
60Hz Ringing Frequency  
Ringing Frequency not used  
Ringing Frequency not used  
Ringing Frequency not used  
Ring Reset Value is 25 Hz  
RNGV3-RNGV0 fix Ring Voltage programmation  
step.  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1  
BIT0  
CR10 sets Teletax Voltage Level.  
HOOK GNDK VB_2M ILIM TEMP CLKF COMRX COMTX  
Reset Value: FFh  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
TTXV7 TTXV6 TTXV5 TTXV4 TTXV3 TTXV2 TTXV1 TTXV0  
HOOK Mask bit for Hook information in the sig-  
nalling register  
Reset Value: FF h  
TTXV7-TTXV0  
Teletax Amplitude [V] = TTXV (7:0) 10Vrms/255.  
A dc drop (TTXV [7:3] 15mV 40)is applied as  
indicated in electric specification section.  
= 1 No influence on SLCX bit (Upstream C/I.5)  
= 0 Each change of the HOOK bit sets SLCX bit  
(Upstream C/I.5)  
GNDK Mask bit for Ground Key information in the  
signalling register  
= 1 No influence on SLCX bit (Upstream C/I.5)  
= 0 Each change of the GNDK bit sets SLCX bit  
(Upstream C/I.5)  
CR11 Bit (7:4) set External-indication threshold  
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0  
ETHR3 ETHR2 ETHR1 ETHR0 STRES3 TXONEDHPRX  
X
VB_2M Mask bit for half-battery information in the  
signalling register  
= 1 No influence on SLCX bit (Upstream C/I.5)  
RESET value = 10 h  
ETHR [3:0] set the External-indication threshold:  
for ETHR[3:0] = 0h, threshold = 0V;  
for ETHR[3:0] > 0h:  
= 0 Each change of the VB_2 bit sets SLCX bit  
(Upstream C/I.5)  
ILIM Mask bit for current limit information in the  
signalling register  
Threshold = 8V + ETHR [3 : 0] 1V  
TXONE and STRES3 must be always pro-  
grammed to 0  
DHPRX = 1 disable the Rx high pass filter  
= 1 No influence on SLCX bit (Upstream C/I.5)  
= 0 Each change of current limit bit sets  
SLCX bit (Upstream C/I.5)  
TEMP Mask bit for temperature information in the  
signalling register  
= 1 No influence on SLCX bit (Upstream C/I.5)  
= 0 Each change of the temperature bit sets  
SLCX bit (Upstream C/I.5)  
CLKF Mask bit for clock-fail information in the sig-  
nalling register  
CR12 can mask the effect on SLCX of the six most  
significant bits of Signalling Register. If a bit is  
masked it will not affect the SLCX bit of upstream  
C/I channel. The unmasked SR bits are used to  
trigger an event-detect circuit and will latch the SR  
signals into a shadow register whenever an event  
occurs. An event is defined as a toggling of one or  
more of the enabled SR bits. Once the interrupt is  
set and the shadow registers are latched, any fur-  
ther event does not influence the interrupt or the  
shadow registers.  
= 1 No influence on SLCX bit (Upstream C/I.5)  
= 0 Each change of the clock-fail bit sets SLCX  
bit (Upstream C/I.5)  
With the SR TOP READ command, the byte repre-  
senting the SR will be sent out to the DU depend-  
ing on the values of the MASK bits. For unmasked  
SR bit its shadow register bit is sent out; otherwise  
the value of SR bit is sent out. At the end of the  
readout of the above byte, the interrupt bit is  
COMRX = 0 Linear code in Rx is enabled  
= 1 PCM in Rx is Enabled  
COMTX = 0 Linear code Tx is enabled  
= 1 PCM in Tx is enabled  
22/49  
STLC3040  
4.9. COFSLIC PROGRAMMING PROCEDURE  
SOP - Write Commands  
DD  
Address  
SOP-Write 0 Byte  
7
1
6
0
0
5
0
4
0
3
0
0
2
0
1
1
0
0
0
1
0
Bit  
Bit  
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
DU  
DU  
Idle  
Idle  
DD  
Address  
SOP-Write 2 Bytes  
7
1
6
0
0
5
0
4
0
3
0
0
2
0
1
1
0
0
0
1
1
Idle  
Idle  
Idle  
Idle  
CR1  
CR2  
Data  
Data  
DD  
Address  
SOP-Write 12 Bytes  
7
1
6
0
0
5
0
4
0
3
0
0
2
0
1
1
0
1
0
1
0
Bit  
7
6
5
4
3
2
1
0
DU  
Idle  
Idle  
Idle  
:
CR1  
:
Data  
:
CR12  
Data  
Idle  
COP - Write Commands  
DD  
7
1
X
6
0
0
5
0
0
4
3
0
0
2
0
0
1
0
1
0
1
1
Bit  
7
6
5
4
3
2
1
0
DU  
Address  
0
0
Idle  
Idle  
Idle  
:
COP-Write 8 Bytes  
Coeff. 1  
:
Data  
:
Coeff. 8  
Data  
Idle  
23/49  
STLC3040  
SOP - Read Commands  
DD  
7
1
X
6
0
1
5
0
X
4
0
X
3
0
0
2
0
1
1
0
0
0
1
0
Bit  
7
6
5
0
4
0
3
Idle  
Idle  
0
2
1
0
DU  
Address  
SOP-Read  
Idle  
1
0
0
0
0
1
0
1
Address  
SOPK-1  
Idle  
0
(*)  
(*)  
LSEL1 LSEL0  
Idle  
DD  
7
1
X
6
0
1
5
0
X
4
0
3
0
0
2
0
1
1
0
0
0
1
1
Bit  
7
1
6
0
5
0
4
0
3
Idle  
Idle  
0
2
1
0
DU  
Address  
SOP-Read  
X
Idle  
0
1
0
1
Address  
SOPK-1  
Idle  
0
(*)  
(*)  
LSEL1 LSEL0  
Idle  
Idle  
Data  
Data  
CR1  
CR2  
DD  
7
1
6
0
1
5
0
4
0
3
0
2
0
1
1
0
1
0
1
0
Bit  
7
1
6
0
5
0
4
0
3
Idle  
Idle  
0
2
1
0
DU  
Address  
SOP-Read 12 Bytes  
Idle  
Idle  
0
1
0
1
Address  
SOPK-1  
0
(*)  
(*)  
LSEL1 LSEL0  
Idle  
:
Data  
:
CR1  
:
Idle  
Data  
CR12  
(*) LSEL1, LSEL0 of previous SOP processed command, SOPK-1 is former SOP command  
24/49  
STLC3040  
TOP - Read Commands  
DD  
7
1
X
6
0
1
5
0
X
4
0
X
3
0
1
2
0
1
1
0
0
0
1
0
Bit  
7
1
6
0
5
0
4
0
3
0
2
0
1
0
0
1
DU  
Address  
Idle  
Idle  
TOP-Read 1 Byte  
Idle  
Idle  
Address  
SR  
Data  
DD  
7
1
X
6
0
1
5
0
X
4
0
X
3
0
1
2
0
1
1
0
0
0
1
1
Bit  
7
1
6
0
5
0
4
3
2
0
1
0
0
1
DU  
Address  
Idle  
Idle  
TOP-Read 3 Bytes  
Idle  
Idle  
Idle  
Idle  
0
0
Address  
SR  
Data  
Data  
Data  
CKS1  
CKS2  
DD  
7
1
X
6
0
1
5
0
X
4
0
X
3
0
1
2
0
1
1
0
1
0
1
0
Bit  
7
1
6
0
5
0
4
3
2
0
1
0
0
1
DU  
Address  
Idle  
Idle  
TOP-Read 15 Bytes  
Idle  
Idle  
:
0
0
Address  
IDCOD0  
:
Data  
:
Idle  
Data  
IDCOD14  
COP - Read Commands  
DD  
7
1
X
6
0
1
5
0
0
4
0
0
3
0
0
2
0
0
1
0
1
0
1
1
Bit  
7
1
6
0
5
0
4
3
2
0
1
0
0
1
DU  
Address  
Idle  
Idle  
COP-Read 8 Bytes  
Idle  
Idle  
:
0
0
Address  
Coeff. 1  
:
Data  
:
Idle  
Data  
Coeff. 8  
25/49  
STLC3040  
If CR1.2 = 0, CR1.3 = 0, line current is measured  
allowing line resistance and capacitance to be ob-  
tained.  
5. APPLICATION & EXTERNAL COMPONENTS  
LIST  
Typical COFISLIC application is shown in Fig. 5.  
It shows the HV (L3000N, L3000S, STLC3170)  
driving the phone line and interfacing the COFIS-  
LIC with the external components summarized in  
the following table.  
If CR1.2 = 1, CR1.3 = 0, TIP wire leakage to  
ground is measured with RING wire in high im-  
pedance.  
If CR1.2 = 0, CR1.3 = 1, RING wire leakage to  
ground is measured with TIP wire in high imped-  
ance.  
Table 11:  
Ref  
RREF  
RAC  
RDC  
Typ. Value  
37.2k1%  
16201%  
8201%  
Function  
Measured value, available on Tx B1 byte:  
Bias resistor (Iref) @ VDD  
AC reference impedance  
DC reference impedance  
It  
50  
RDC  
6
/ / CAC Tx GAIN  
It = transversal line current  
CAC (*) 11µF 5V 20% AC/DC current splitting  
RDC = DC reference resistance (typically 820 )  
DS  
BAT 49  
100nF  
Protective Shottky Diode  
Battery Reversal Capacitor  
Battery Voltage Rejection  
CR8.0 = 1 Active Modulation for returned value.  
CAP  
Operating Mode:  
B filter:  
Test dedicated, H.V. Active  
CDVB 47µF - 20V  
±20%  
Off  
Z filter:  
Off  
(*) unbiased capacitor  
Rx Path:  
Functional  
L3000N and L3000S require dotted components  
(see fig. 5) for Off/Hook detection in "External In-  
dication" (see table 12).  
Tx Path:  
Functional with input  
connected to RDC  
resistance.  
Table 12:  
R, X, GX, GR Filters:  
KD filter:  
Programmable  
Programmable (suggested  
max value to avoid  
saturation = 0800h)  
Ref  
Typ. Value  
Function  
Line Feed  
RT, RR  
33kΩ  
DC Synthesis:  
TTX:  
Off  
Not Applicable  
6. INTEGRATED TEST FEATURES  
Internal Tone Generation Only 1KHz Available  
in Rx:  
The device has built-in several functionalities  
dedicated to perform generic testing.  
Each test is enabled if CR2.3 (TMN) bit is set to 1.  
In each test description more details about active  
functionalities are written.  
Hook Detection:  
ILIM  
As in Active Mode  
Off  
High-Pass Filters:  
Reverse Polarity  
Controlled by CR1.1  
set by SOP register  
Command  
6.1.1. LINE TEST MODE 1 (TST-LEAK)  
Enabled by CR2.3 = 1 and CR5 (3:0) = 01h and  
CR8.1 = 0.  
Boosted Battery  
set by CR1 register  
A trapezoidal signal (see Fig. 10) is sent to 2-wire line.  
6.1.2. LINE TEST MODE 2 (TST-LKA)  
Enabled by CR2.3 = 1, CR5 [3:0] = 02h and  
CR8.1 = 0.  
Figure 10.  
GND  
VDROP  
VPP  
The setup is the same of Test 1 except the meas-  
ured value that is:  
It RDC  
Tx GAIN  
50  
6
T1  
T2  
T3  
T4  
D95TL206C  
If CR1.2 = 1, CR1.3 = 0, TIP wire leakage to  
ground is measured with RING wire in high im-  
pedance.  
T1=T2=T3=T4=100ms  
VDROP = -170mV - 15 CR10[7:3]  
25  
VPP  
=
V if CR9.7=0  
If CR1.2 = 0, CR1.3 = 1, RING wire leakage to  
ground is measured with TIP wire in high imped-  
ance.  
40  
32.7  
VPP  
=
V if CR9.7=1  
40  
17  
13  
V
OUT = (VPP + VDROP + RX) =  
if CR 9.7 = 1  
VOUT = (VPP + VDROP + RX) = 1 if CR 9.7 = 0  
26/49  
STLC3040  
When this Test mode is on, all the functionalities  
of Active mode are still available. In addition the  
window detector is switched on.  
6.1.4. TEST MODE 4 (TST-800Hz)  
The device is in Active mode. An 800Hz tone is  
injected into the line. The tone amplitude is pro-  
grammable through TTX voltage register (CR10).  
1KHz tone can be added (CR1.4), in this case Rx  
input is disabled.  
6.1.7. TEST MODE 9 (TST-LINE-IMPDC)  
In this mode thr Rx channel is functional and its  
gain is increased by a factor 16 (the same gain is  
also applied to the 1KHz enabled by CR1.4).  
Z, ILIM and DC feed characteristics are disabled.  
A drop of roughly 3.9V/step is superimposed to  
the line under control of CR10 [7:3].  
Tx path is fully functional and controllable. Trans-  
versal line current (It) is measured across the par-  
allel RDC, CAC:  
6.1.5. TEST MODE 5 (TST-TONE-CAL)  
It carries out a tone calibration.  
1KHz frequency is sent to backplane (TX direc-  
tion)  
Returned Information on Tx B1 byte:  
1KHz Tone at the maximum digital level  
Operating Mode:  
B filter:  
Active  
It  
50  
RDC  
6
Programmable  
Programmable  
Functional  
Off  
Tx GAIN  
CAC  
Z Synthesis:  
Rx Path:  
Modulated if TMM = 1 in CR8 register.  
Tx Path:  
Operating Mode:  
Test Dedicated, H.V. set by  
R, GR Filters:  
Gain as per programmed  
coefficients  
downstream C/I  
Programmable  
Off  
B Filter:  
Z Filter:  
Rx Path:  
Tx Path:  
R, X, GR, Gx:  
KD:  
DC Synthesis:  
TTX:  
On  
Functional  
1KHz available  
Functional  
Internal Tone  
Generation in Rx:  
Functional  
ILIM  
:
On  
Programmable  
Hook Detection:  
As in Active  
Programmable (Suggested  
max. value to avoid  
saturation = 800h)  
High Pass Filters:  
Controlled by CR1.1 and  
CR11.1  
DC Synthesis:  
TTX:  
Only Programmable Voltage  
drop  
6.1.6. TEST MODE 7 (TST-ALB)  
Not Applicable  
1KHz available  
A 1KHz Tone can be generated in digital section.  
This Test mode is equivalent to the Active mode.  
Disabling B filter, the gain of the whole path (Rx +  
HV (L3000N, L3000S, STLC3170) + external load  
+ Tx) can be measured.  
The measurement is carried out by a window de-  
tector placed at the input of the PCM encoder.  
Internal Tone  
Generation in Rx:  
Hook detection:  
ILIM  
As in active mode  
As per programmed value in  
Active mode  
High Pass Filters  
Reverse Polarity  
Controlled by CR1.1 and  
CR11.1  
The window detector compares the negative or  
positive amplitude peak (it depends on the pro-  
grammed battery polarity) of the input signal with  
a range of values.  
Set by SOP register  
command  
6.1.8. TEST MODE A (TST-LINE-IMPAC)  
The range is centred around 6dB below the PCM  
This test follows the same procedure as Test 9  
having the sensing done only on RDC.  
Measured value:  
±
±
full scale. Range width is 0.5dB or 1.5dB de-  
pending on the programmed polarity.  
Returned information on upstream GCI channel:  
It  
it  
50  
RDC  
6
Tx GAIN  
1.  
RAC Tx GAIN  
50  
6.1.9. TEST MODE C (TST-IRING)  
2. CR2.6 (OKTON)  
3. CR2.7 (XVA) = 1means measurement has  
settled  
Normal Ring signal (no power reduced mode  
available) is generated and sent to 2-wire in order  
to test internal ring generator. Frequency and Am-  
plitude are programmable by CR5 register.  
CR2.6 = 1 means signal level within the window  
range.  
Auto Ring Trip function can be disabled by RTEN  
27/49  
STLC3040  
bit (CR7 Register). The Hook state is anyway  
sent upstream.  
Returned Information on upstream GCI channel:  
quently about the functionalities of TTX genera-  
tion circuitry. 800Hz frequency is used instead of  
standard 12KHz/16KHz, because 12KHz or  
16KHz would be cut out by filters in Tx path.  
Returned Information on TXB1 channel:  
It  
50  
R
DC  
6
1.  
Tx GAIN  
It  
50  
2. CR2.4 (OKRNG)  
R
AC  
GTX  
OKRNG = 1 means that ring amplitude is  
within the accepted range see fig. 11.  
3. CR2.7(XVA) = 1 means measurement has  
settled.  
Operating Mode:  
Active  
B filter:  
Programmable  
Programmable  
Functional  
Z filter:  
Modulated if TMM = 1 in CR2 Register.  
Rx Path:  
Tx Path:  
Functional  
Figure 11: VRDC sign depending on Battery Po-  
larity.  
R, X, GR, Gx:  
KD:  
Programmable  
Programmable (suggested  
max value to avoid saturation  
= 800h  
VRDC Sign depending  
on Battery Polarity  
V
RDC  
DC Synthesis:  
TTX:  
Functional  
800Hz with programmable  
amplitude  
RING  
PAUSE  
D95TL207A  
RING  
BURST  
RING AMPLITUDE  
PEAKS "MEASURED" BY  
THE WINDOWS DETECTOR  
Internal Tone  
1KHz Available  
Generation in Rx:  
Hook detection:  
As in active  
Functional  
Connecting a known impedance across the line  
and considering the programmed Ring level  
(CR9 register), a window detector, as for Test  
7, allows to monitor if the signal at PCM en-  
coder input is in the correct range.  
Through this procedure the ring functionality in-  
cluding several effects, HV device, protect resis-  
tor, battery voltage etc, can be evaluated.  
ILim  
:
High Pass Filters:  
Controlled by CR1.1 and  
CR11.1  
6.1.11. TEST MODE E (TST-TTXFILT)  
Purpose of this test is to check the functionality of  
the TTX filter.  
A TTX signal at 12kHz or 16kHz superimposed to  
a 1KHz tone, enabled by CR1.4, is sent to the  
line.  
Operating Mode:  
B Filter:  
Z Filter:  
Ring  
Off  
Returned Information on upstream GCI channel:  
Off  
Rx Path:  
Tx Path:  
X, Gx:  
Off  
It  
50  
1.  
R
AC  
Tx GAIN  
Functional  
Programmable  
2. CR2.5 (OKTTX)  
KD:  
Programmable (Suggested  
max value to avoid saturation  
= 800h)  
3. CR2.6 (OKTON)  
4. CR2.7(XVA) = 1 means measurement has  
settled.  
OKTTX says that programmed TTX level has  
been caught up.  
OKTON set to 1 indicates that 1kHz tone has not  
been compressed by the superimposed TTX sig-  
nal. In this case the TTX filter properly works.  
DC Synthesis:  
TTX:  
Off  
Not applicable  
Not applicable  
Internal Tone  
Generation in Rx:  
Hook detection  
As in Ring Mode  
Off  
ILIM  
:
High Pass Filters:  
Controlled by CR1.1 and  
CR11.1  
Operating Mode:  
B Filter:  
Active  
Programmable  
Programmable  
Functional  
Z Filter:  
6.1.10. TEST MODE D (TST-PTTX)  
Tx Path:  
800Hz tone is sent to 2-wire. This pseudo TTX  
signal (800Hz) requires C/I.5 bit (TIM) set to 0.  
Shaping functions are disabled. The internal win-  
dow detector is enabled as for Test Mode 7.  
Measured line current gives information about  
amplitude of generated pseudo TTX and conse-  
Rx Path:  
R, X, GR, GX  
KD:  
Functional  
Programmable  
Programmable (suggested  
max value to avoid saturation  
= 800h  
28/49  
STLC3040  
DC Synthesis:  
TTX:  
Functional  
Operating Mode:  
B Filter:  
Test Dedicated, H.V. Active  
ON with programmable  
amplitude and frequency.  
Off  
Z Filter:  
Off  
Internal Tone  
Generation in Rx  
1KHz available  
Tx Path:  
Functional  
Rx Path:  
Functional with input  
connected to RDC resistance.  
Hook detection  
ILIM  
As in Active Mode  
Functional  
R, X, GR, Gx  
KD:  
Programmable  
High Pass Filter  
Controlled by CR1.1 and  
CR11.1  
Programmable (Suggested  
max value to avoid saturation  
= 800h)  
DC Synthesis:  
TTX:  
Functional  
6.1.12. TEST MODE F (TST-DC LOOP)  
Not applicable  
1kHz available  
Purpose of this test is to check if DC charac-  
teristics (RFEED and ILIM) synthesis works cor-  
rectly.  
Internal Tone  
Generation in Rx:  
Hook detection:  
As in Active Mode  
Functional  
A trapezoidal signal (see Fig. 10) is sent to the 2-  
wire line.  
ILIM  
:
Returned information on Tx B1 byte:  
High Pass Filters:  
Controlled by CR1.1 and  
CR11.1  
It  
RDC  
C
AC  
Reverse Polarity:  
Set by SOP register  
command Boosted Battery  
Tx GAIN  
50  
6
29/49  
STLC3040  
ABSOLUTE MAXIMUM RATINGS (*)  
Symbol  
Parameter  
Test condition  
Min.  
Max.  
Unit  
Vdd  
Positive Digital Supply Voltage  
Referred to DGND  
-0.3  
+5.5  
V
VCC  
VEE  
Positive Analog Supply Voltage  
Referred to AGND  
Negative Analog Supply Voltage  
Referred to AGND  
-0.3  
-5.5  
-0.3  
-0.3  
+5.5  
+0.3  
+0.3  
V
V
V
AGND to  
DGND  
CC to VDD Difference VCC to VDD  
Difference AGND to DGND  
V
+0.3  
100  
V
mA  
ILTH  
DC input and output current at  
any input or output pin (free  
from latch-up)  
Tj  
Tstg  
VIGCI  
Maximum Junction Temperature  
Storage Temperature Range  
Voltage Referred to DGND  
150  
-55  
-0.3  
°C  
°C  
V
+150  
VDD +0.3  
Input GCI pins 3, 4, 5, 40, 41,  
42 and 43  
VOGCI  
VTHVI  
IPDN  
VLINT  
VCHVI  
Output GCI pin 6  
-0.3  
VEE -0.3  
-0.5  
-80  
VEE -0.3  
VDD +0.3  
VCC +0.3  
0.5  
80  
VCC +0.3  
V
V
mA  
V
Voltage Referred to AGND  
Input Current  
Voltage Referred to AGND  
Interface to H.V. pins: 9, 10  
Interface to H.V. pin: 28  
Interface to line pins: 11,12  
Interface to H.V. Current Input  
pins: 15, 19  
V
VBHVI  
V2WI  
VDIO  
VMIS  
VDUN  
VTID  
Voltage Reference Input pin: 25  
Ouput Buffer pin: 26  
I/O pins: 7, 8, 38, 39  
Ring Sync pins: 29, 36  
Reserved pins: 37, 44  
Identification Code pins:31, 32  
Identification Code pin: 35  
VEE -0.3  
VEE -0.3  
-0.3  
-0.3  
-0.3  
VEE -0.3  
-0.3  
VEE -0.3  
VCC +0.3  
VCC +0.3  
VDD +0.3  
VDD +0.3  
VDD +0.3  
VCC +0.3  
VCC +0.3  
+0.3  
V
V
V
V
V
V
V
V
Voltage Referred to AGND  
Voltage Referred to DGND  
Voltage Referred to AGND  
VBID  
VCREV  
Battery Reversal capacitor  
input pin: 14  
VACDC  
AC and DC - synthesis  
Reference Resistor pins 16, 22  
-3  
+3  
V
AC/DC line split pin: 20  
V
EE -0.3  
-0.3  
-0.3  
-0.3  
VCC +0.3  
+0.3  
VCC +0.3  
VCC +0.3  
V
V
V
V
AC splitter capacitor pin: 21  
Reference Voltage output pin: 23  
Reserved pins: 13, 17, 18, 24, 30  
VOREF  
VAUN  
(*) Stresses in excess of those listed under "Absolute Maximum Rate" may cause permanent damage to the device. This is a stress rating only  
and functional operation of the device at these or any other conditions in excess of those indicated in the operational sections of this  
specification is not implied.  
THERMAL DATA  
Symbol  
Parameter  
Value  
Unit  
Rth j-amb  
Thermal Resistance Junction to Ambient  
Max.  
60  
°C/W  
OPERATING RANGE  
Symbol  
Parameter  
Value  
4.75 to 5.25  
4.75 to 5.25  
-4.75 to -5.25  
0
Unit  
V
VDD  
VCC  
VEE  
Positive Digital Supply Voltage Referred to DGND  
Positive Analog Supply Voltage Referred to AGND  
Negative Analog Supply Voltage Referred to AGND  
Difference AGND to DGND  
V
V
DGND to  
AGND  
V
Top  
Ambient Operating Temperature  
-40 to +85  
°C  
30/49  
STLC3040  
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70°C, VDD = VCC = 5V ±5%,  
VEE = -5V ±5%, AGND = DGND = 0V; for operating in ext. temp. range -40° +85°C the same limits are  
confirmed by characterisation data unless otherwise specified.)  
Symbol  
Parameter  
Test Condition  
Min.  
Typ.  
Max.  
1.5  
Unit Notes  
Vil  
Input Voltage at Logical "0"  
Pins 29,35,36,38,40,41,42,43.  
Pins 7, 8 [when inputs]  
0
0
V
V
V
V
1.5  
Vih  
Input Voltage at Logical "l"  
Pins 29,35,36,38,40,41,42,43 VDD-1.5  
Pins 7, 8 [when inputs]  
0V < Vin < VDD  
VDD-1.5  
-1  
Ii  
Input Current  
1
µA  
1
Vol  
Output Voltage at Logical "0" Pin 7, 8 (when outputs),  
39 IOl = 4mA  
0.45  
V
Voh  
Output Voltage at logical "l"  
Pin 7, 8 (when outputs),  
39 IOh = -3mA  
VDD-0.45  
V
VT+  
VT-  
Positive going Threshold  
Negative going Threshold  
Threshold Hysteresis  
pins: 3, 4, 5  
3.15  
V
V
V
V
2
2
1.35  
0.5  
VH  
VOLOD  
Output Voltage at Logical  
"0"on open drain output  
pin: 6, IO = 7.5mA  
0.45  
5
V
hv1, Vhv2 Output Voltage at High Level pin 10: IO = 10µA  
2
-1  
V
V
V
V
V
V
on pins 9, 10 pin 9: 10µA IO 300µA  
Vmv1, Vmv2 Output Voltage at Zero Level pin 10: IO = 10µA  
1
on pins 9, 10  
pin 9: 10µA IO 300µA  
Vlv1, Vlv2 Output Voltage at Low Level  
on pins 9, 10  
pin 10: IO = 10µA  
pin 9: 10µA IO 300µA  
-5  
-2  
VihID  
Ternary input pins 31, 32  
High level  
2
VCC  
-2  
ViIID  
Ternary input pins 31, 32  
Low level  
VEE  
-1  
VimID  
Ternary input pins 31, 32  
medium level  
1
(1) for all the digital inputs: TTL, CMOS, 3-Levels, with Hysteresis. Except pins 18, 24, 30, 44, 43, which have internally 22Kpull-down.  
(2) see figure 12.  
Figure 12.  
V
OUT  
HIGH  
LOW  
V
IN  
V
V
T+  
T-  
D96TL255A  
31/49  
STLC3040  
SUPPLY CURRENTS:  
see Table 13 with coefficient and configuration register contents set as per de-  
±
±
fault values after reset; Tamb = 0 to 70°C, VDD = VCC = 5V 5%, VEE = -5V 5%, AGND = DGND = 0V.  
Typical values are measured at Tamb = 25°C, VDD = VCC = 5V, VEE = -5V ; for operating in ext. temp.  
range -40° +85°C the same limits are confirmed by characterisation data unless otherwise specified.  
VOLTAGE SUPPLY  
OPERATING MODES  
ACTIVE  
VDD  
VCC  
VEE  
IDDACT Min  
ICCACT Min  
Typ  
IEEACT Min  
Typ  
Typ 8mA  
Max 13mA  
Max 23mA  
Max 23mA  
POWER DENIAL  
RING  
I
DDPDEN Min  
ICCPDEN Min  
Typ  
IEEPDEN Min  
Typ  
Typ  
Max 3mA  
Max 5mA  
Max 2mA  
IDDRNG Min  
Typ  
ICCRNG Min  
Typ  
IEERNG Min  
Typ  
Max 13mA  
Max 23mA  
Max 23mA  
STAND-BY  
I
DDSTB Min  
ICCSTB Min  
Typ  
IEESTB Min  
Typ  
Typ  
Max 7mA  
Max 13mA  
Max 10mA  
DC ELECTRICAL CHARACTERISTICS OF ANALOG PINS  
±
±
(Tamb = 0 to 70°C, VDD = VCC = 5V 5%, VEE = -5V 5%, AGND = DGND = 0V; for operating in ext. temp.  
range -40° +85°C the same limits are confirmed by characterisation data unless otherwise specified)  
Symbol  
Parameter  
Test Condition  
VPDO = +1.0V  
Min.  
Typ.  
Max.  
Unit  
IPDOHiZ  
Leakage Current at pin 28 in  
High impedance  
-1  
1
µA  
IPDOLOZ  
Sinked Current at pin 28 in low  
impedance  
VPDO = +1.0V  
45  
55  
µA  
VPDO  
VL1, VL2  
Itmax  
Operating Voltage at pin 28  
0
5
V
V
Operating Voltage at pin 11, 12  
-70  
+70  
2.6  
Absolute Value of Input Current  
at pin 19  
mA  
Ilmax  
Absolute Value of Input Current  
at pin 15  
2.6  
mA  
VBIM  
VOUT  
ZVOUT  
IVOUT  
Battery Image Voltage  
2-wire Ouput Voltage  
2-wire Output Impedance  
2-wire Output Current  
-3.5  
-3.3  
0
V
V
3.3  
200  
-1  
1
mA  
RAC, CAP, see External Component List  
ACDC,CAC,  
RDC, REF  
DC ELECTRICAL CHARACTERISTICS OF ANALOG PINS  
±
±
(Tamb = 0 to 70°C, VDD = VCC = 5V 5%, VEE = -5V 5%, AGND = DGND = 0V; for operating in ext. temp.  
range -40° +85°C the same limits are confirmed by characterisation data unless otherwise specified)  
Active Mode  
Symbol  
(see Table 13)  
Parameter  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
Notes  
VOUTDROP Operation Dropout  
Voltage on pin 26  
It = 0  
DD (pin 5): Idle  
CR1.6 (N/BB) = 0  
VOUT1  
-30  
VOUT1 VOUT1  
+30  
mV  
1
Operation Dropout  
Voltage on pin 26  
It = 0  
DD (pin 5): Idle  
CR1.6 (N/BB) = 1  
-725  
-685  
-645  
mV  
RFEED  
DC feeding resistance on  
pin 26  
It < Ilim/50  
DD (pin 5): Idle  
CR1.6 (N/BB) = X  
RFEED1 RFEED1 RFEED1  
-10% +10%  
2
32/49  
STLC3040  
DC ELECTRICAL CHARACTERISTICS OF ANALOG PINS  
(continued)  
Symbol  
Parameter  
Test Condition  
Min. Typ. Max. Unit Notes  
RFEEDL  
DC feeding resistance in It Ilim/50  
15  
kΩ  
limited current pin 26  
DD (pin 5): Idle  
CR1.6 (N/BB) = X  
Programmable Limitation CR1.6 (N/BB) = 0  
ILIM/50  
-10% IL1 +10% mA  
-10% IL1 +10% mA  
3
3
current on pin 19  
CR1.6 (N/BB) = 1  
It < 1mA  
IPOFF-HK  
Programmable off-hook  
threshold for positive  
transition on pin 19  
CR6.1 (ITHR) = 0 0 < Tamb < 70°C  
SOP.5 (POL) = X -40 < Tamb < +85°C 175  
CR6.1 (ITHR) = 1 0 < Tamb < 70°C 234  
SOP.5 (POL) = X -40 < Tamb < +85°C 225  
CR6.1 (ITHR) = 0 0 < Tamb < 70°C 160  
SOP.5 (POL) = X -40 < Tamb < +85°C 155  
CR6.1 (ITHR) = 1 0 < Tamb < 70°C 214  
SOP.5 (POL) = X -40 < Tamb < +85°C 205  
OFFHKPERS Off-hook persistency check CR6.1 (ITHR) = X  
180  
200  
195  
260  
255  
220  
220  
286  
286  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
ms  
µA  
INOFF-HK  
Programmable off-hook  
threshold for negative  
transition on pin 19  
NH  
4
5
IPGNDK  
Ground-key bit current  
threshold for positive  
transition on pin15  
SOP.5 (POL) = X  
|140|  
|240|  
INGND  
Ground-key threshold for  
negative transition  
|120|  
µA  
GNDKPERS Ground-key persistence  
check  
NG  
20  
ms  
Ithv  
Current drained for  
thermal overload from pin9  
SR.3 (TEMP) = 0  
SR.3 (TEMP) = 1  
180  
800  
µA  
µA  
µA  
320  
HITHV  
VB/2  
Thermal overload  
hysteresis  
Voltage on pin25 to toggle See test conditions 8  
VBIMT VBIMT VBIMT  
V
the SR.5 bit (VB_2)  
C/I.6 (conv) = 1  
SOP.5 (POL) = 0  
-20%  
+20%  
SRBITPERS Limiting current, thermal  
overload, half battery bit  
persistence  
5.5  
8.5  
ms  
Stand-By Mode  
(see Table 13)  
Symbol  
Parameter  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
Notes  
VODROPSBY Stand-by Dropout Voltage  
on pin 26  
It = 0µA  
-85  
-70  
-55  
mV  
RFEEDSBY DC feeding resistance on  
pin 26  
It < Ilim/50  
It Ilim/50  
-10% RFEED1 +10%  
15  
2
RFEEDL  
Stand-by DC feeding  
resistance in limited  
current pin 26  
kΩ  
ILIM/50SBY Programmable limitation  
current in stand-by on pin 19  
-10% ILSBY +10%  
-10% ILSBY +10%  
NH  
µA  
µA  
ms  
µA  
6
6
4
IOFF-HKSBY  
Stand-by programmable  
off-hook threshold on pin 19  
OHKSBYPERS Stand-by off-hook  
persistence check  
ISBYGNDK  
Stand-by ground-key bit  
current threshold for  
|140|  
|240|  
positive transition on pin 15  
GNDSBYPERS Stand-by ground-key  
persistence check  
NG  
ms  
5
ISBYthv  
Current drained for thermal SR.3 (TEMP) = 0  
180  
800  
µA  
µA  
overload from pin 9 in  
stand-by  
SR.3 (TEMP) = 1  
320  
5.5  
SRSBYBITPERS Limiting current, thermal  
overload, half battery bit  
8.5  
ms  
persistence in stand-by  
33/49  
STLC3040  
DC ELECTRICAL CHARACTERISTICS  
(continued)  
Ring Mode  
(Downstream C/I.7 [RING] = 1 see Table 13)  
Symbol  
Parameter  
Test Condition  
Downstream  
C/I.5 (TIM) = 1 &  
C/I.6 (CONV) = X  
Min.  
Typ.  
Max.  
Unit  
Notes  
VODROPRNG Ring mode Dropout  
Voltage on pin 26 Ring On  
-20  
20  
mV  
Ring mode Dropout  
Voltage on pin 26 Reduced C/I.5 (TIM) = 0 &  
Power Ring Pause  
Downstream  
-85  
-20  
-70  
-55  
20  
mV  
mV  
C/I.6 (CONV) = 0  
Ring mode Dropout  
Voltage on pin 26 Ring  
Pause  
Downstream  
C/I.5 (TIM) = 0 &  
C/I.6 (CONV) = 1  
RFEEDRNG Ring mode DC feeding  
resistance on pin 26  
Downstream C/I.5 (TIM) = 0 & -10%  
C/I.6 (CONV) = 1 It < Ilim/50  
0
+10%  
2
6
RFEELRNG Ring DC feeding resistance It Ilim/50  
15  
kΩ  
µA  
in limited current on pin 26  
ILIM/50RNG Programmable limitation  
current on pin 19 in  
Downstream  
-10% ILSBY +10%  
C/I.5 (TIM) = 0 &  
C/I.6 (CONV) = 0  
reduced power ring pause  
OHKRNGPER Ring mode off-hook  
persistence check  
NH  
ms  
ms  
µA  
4
5
GNDRNGPER Ring mode ground-key  
persistence check  
NG  
ISBYthv  
Current drained for thermal SR.3 (TEMP) = 0  
180  
overload from pin 9 in ring  
mode  
Downsteam  
C/I.5 (TIM) = 0 &  
C/I.6 (CONV) = 0  
SR.3 (TEMP) = 1  
Downsteam  
320  
800  
µA  
C/I.5 (TIM) = 0 &  
C/I.6 (CONV) = 0  
SRRNGBITPER Limiting current, thermal  
overload, half battery bit  
5.5  
8.5  
ms  
persistence in ring mode  
IRNGGTH  
Ring trip off-hook current  
threshold on pin 19  
Downstream  
-10%  
THR  
+10%  
µA  
7
6
C/I.5 (TIM) = 1 &  
C/I.6 (CONV) = X OR  
Downsteam  
C/I.5 (TIM) = 0 &  
C/I.6 (CONV) = 1  
Downsteam  
C/I.5 (TIM) = 0 &  
C/I.6 (CONV) = 0  
-10% ILSBY +10%  
µA  
µA  
IRNGGNDKTH Ring ground-key bit current Downsteam  
|140|  
|240|  
threshold for positive  
transition on pin15  
C/I.5 (TIM) = X &  
C/I.6 (CONV) = X  
Power Denial Mode  
(Downstream C/I.[7,5] [RING, CONV, TIM] = 0, CR1.7 [PD] 0, see Table 13.  
DVOFFHKPD Power denial differential  
voltage off-hook threshold  
-15%  
-60  
+15%  
+60  
CVOFFHKPD Power denial threshold  
voltage off-hook common  
mode range  
V
OHKPERSPD Off-hook persistence check  
in power denial mode  
CR6.1 (ITHR) = X  
NH  
ms  
4
Notes:  
(4) NH = CR3 [7..4] 1ms  
(5) NG = CR3 [3..0] 4ms  
(6) ILSBY = (CR7 [7..2] 1.1mA)/50  
(7) THR = {(1 + CR5[7..4]) 9.6mA/16}/50  
(1) VOUT1 = -(170mV + CR10[7..3] 15mV)  
(2) RFEED1 = (RDC/6.56) (1+CR8 [7..5])  
(3) IL1 = (CR6[7..2] 1.1mA)/50  
34/49  
STLC3040  
AC ELECTRICAL CHARACTERISTICS OF ANALOG PINS  
±
±
Tamb = 0 to 70°C, VDD = VCC = 5V 5%, VEE = -5V 5%, AGND = DGND = 0V (see Table 13); for operat-  
ing in ext. temp. range -40° +85°C the same limits are confirmed by characterisation data unless other-  
wise specified.  
Symbol  
Parameter  
Test Condition  
Min.  
Typ.  
Max.  
Unit  
GX  
Absolute gain in TX  
see fig. 13 Normal temp. range  
Extended temp. range  
-0.2  
-0.4  
0.2  
0.4  
dB  
dB  
GR  
Absolute gain in RX  
see fig. 13 Normal temp. range  
Extended temp. range  
-0.2  
-0.4  
0.2  
0.4  
dB  
dB  
THDX  
THDR  
Total harmonic distortion in TX  
Total harmonic distortion in RX  
see fig. 13;  
-48  
-48  
dB  
dB  
f
ref = 1kHz; reference signal  
level 0dBm0 @ digital side;  
measurements of 2nd and 3rd  
order harmonics  
GFTX  
GFRX  
GLTX  
GLRX  
Gain Variation with frequency in fref = 1kHz; reference signal  
see  
fig.12  
see  
fig.12  
see  
fig.13  
see  
fig.13  
TX  
level @ digital side;  
-10dBm0  
Gain Variation with frequency in  
RX  
Gain Variation with level in TX  
Sinusoidal Test Method;  
fref = 1kHz; reference signal  
level @ digital side;  
-10dBm0  
Gain Variation with level in Rx  
S/NTX  
S/NRX  
NTP  
Signal to noise ratio in TX  
Signal to noise ratio in Rx  
Idle channel noise in transmit  
Sinusoidal Test Method;  
see  
fig.14  
fref = 1kHz;  
see test cond. 1  
Teletax enabled with  
Downstream C/I.5 (TIM) = 0; A-  
Law  
0 < Tamb < 70°C  
-40 < Tamb < +85°C  
Teletax enabled with  
Downstream C/I.5 (TIM) = 0; A-  
Law  
-73  
-71  
-67  
12  
dBmp  
dBmp  
µVp  
NRP  
Idle channel noise in receive  
NTTX-TP  
Idle channel noise in receive  
with metering pulse on output  
see test cond. 1  
12  
µVp  
Teletax enabled with  
Downstream C/I.5 (TIM) = 1; A-  
Law  
SOSRX  
SOSTX  
Spurious out of band signals at  
analog output  
Spurious out of band signals at  
digital output  
see test cond. 2, Sinusoidal test  
method  
-31  
-25  
dB  
dB  
Thl  
Arl  
PSRRP2W  
Cofislic Transhybrid loss  
Return loss  
Positive power supply rejection  
ratio on 2-wire  
see test cond. 3  
see test cond. 4  
VRIPPLE = 100mV,  
300Hz f 3400Hz, on VCC  
Residual measured on VOUT  
(pin 26) see test cond. 5  
40  
25  
dB  
dB  
dB  
-56  
-30  
PSRRPGCI Positive power supply rejection  
ratio on data-up GCI  
VRIPPLE = 100mV,  
dB  
300Hz f 3400Hz, on VCC  
Residual measured on 5GCI  
data-up DU (pin 6)  
see test cond. 5  
PSRRN2W  
Negative power supply  
rejection ratio on 2-wire  
VRIPPLE = 100mV,  
-56  
-30  
dB  
dB  
300Hz f 3400Hz, on VEE  
Residual measured on VOUT  
(pin 26) see test cond. 5  
PSRRNGCI Negative power supply  
rejection ratio on data-up GCI  
VRIPPLE = 100mV,  
300Hz f 3400Hz, on VEE  
Residual measured on GCI  
data-up DU (pin 6)  
see test cond. 5  
35/49  
STLC3040  
AC ELECTRICAL CHARACTERISTICS OF ANALOG PINS  
(continued)  
Symbol  
Parameter  
Test Condition  
see test cond. 6  
Min.  
Typ.  
Max.  
Unit  
V2WRNG  
Ring amplitude at 2-wire output  
-5%  
2WRNG +5%  
Vrms  
VOUT (pin 26)  
THDRNG  
VTTX  
Total harmonic distortion in  
Ring mode  
see test cond. 6  
see test cond. 7  
2%  
2-wire amplitude at VOUT (pin  
26) during teletax emission  
-5%  
2WTTX  
+5%  
2%  
Vrms  
THDTTX  
Total harmonic distortion during see test cond. 7  
teletax emission  
ABSOLUTE GAIN Rx/Tx (law A)  
CR[ 1] = 00  
CR[ 2] = 00  
CR[ 3] = 00  
CR[ 4] = F9  
CR[ 5] = 60  
CR[ 6] = 50  
CR[ 7] = 1C  
target Vout represents the rms level to be measured  
at Vout starting from a DD Vpcm (dBm0) code with a  
certain set of coefficient.  
target Vout = (mVrms) = (2 1.514 2) [10^ ((Vpcm -  
3.14)/20)]/16 (0.98 (R[1]/8192) (GR/256)/(2 sqr (2)))  
CR[ 8] = 08  
CR[ 9] = 2F  
CR[10] = 00  
CR[11] = 10  
CR[12] = 03  
GR = FFh  
GX = FFh  
K = 1000h  
(255)  
(255)  
(4096)  
Example if DD Vpcm = 0dBm0 target Vout =  
45.5mVrms (0dBm0/COFISLIC)  
absolute gain = 20 log (Vout / target Vout)  
| 1000h  
(4096) |  
target DU represents the dBm0 level expected on DU  
with a certain set of coefficient and a Vrac of  
41.4Vrms  
VRac_ref is the amplitude of the sine wave (1kHz) to  
be applied on RAC (pin 16) in order to expect on DU  
a Vpcm dBm0 level with the same set of coefficient.  
R
X
| 0h  
| 0h  
| 0h  
(0)  
(0)  
(0)  
|
|
|
| 1000h  
| 0h  
| 0h  
(4096) |  
(0)  
(0)  
(0)  
|
|
|
target DU (dBm0) = 3.14 + 20 Log((0.0414  
3 (2  
sqr(2)) / 1.514) 16 (K/8192) (X[1]/8192) (GX/256)  
0.966)  
| 0h  
VRac_ref = (41.4mV 10^ ((Vpcm - target DU)/20)  
B[1..8] = 0  
Z[1..3] = 0  
Reference frequency = 1kHz  
Example if target DU = 0dBm0 then VRac_ref =  
32.3mVrms (A_law)  
absolute gain = dBm0 level on DU (full scale  
3.14dBm0 A_law)  
Figure 13.  
DU  
RAC  
16  
26  
6
5
0dBm0  
0dBm0  
VRAC  
1620Ω  
DD  
VOUT  
V2W  
D96TL256A  
36/49  
STLC3040  
FREQUENCY RESPONSE Rx/Tx  
Multitone on DD (pin 5) total level = -10dBm0  
Multitone on VRac (pin 16) total amplitude about  
24mVp  
CR[ 1] = 00  
CR[ 2] = 00  
CR[ 3] = 00  
CR[ 4] = F9  
CR[ 5] = 60  
CR[ 6] = 5C  
CR[ 7] = 1C  
CR[ 8] = 08  
CR[ 9] = 2F  
CR[10] = 00  
CR[11] = 10  
CR[12] = 03  
freq.resp. Rx = 20 log(V2w fx / V2w 1kHz)  
freq.resp. Tx = dBm0 level at fx - dBm0 level at  
1kHz  
GR = 79h  
GX = 80h  
K = 1000h  
(121)  
(128)  
(4096)  
where 300Hz < fx < 3.400kHz  
| 1DBCh  
(7612) |  
R
X
| 1AE6h  
| 24B8h  
| 8CCh  
(6886) |  
(-6984)|  
(2252) |  
| 3CFChh  
| 3F41h  
| 1476h  
| 1449h  
(-772) |  
(-191) |  
(5238) |  
(5193) |  
Z[1..3] = 0  
B[1..8] = 0  
Reference frequency = 1kHz  
Figure 14.  
RECEIVE:  
ATTENUATION  
(dB)  
2
1.4  
1
0.9  
0.65  
0.45  
0.25  
0
-0.25  
-1  
0
.3 .4 .6  
1.0  
2.0  
2.4  
3.0  
3.4 3.6  
FREQUENCY (KHz)  
TRANSMIT:  
ATTENUATION  
(dB)  
2
1.4  
1
0.9  
0.65  
0.45  
0.25  
0
-0.25  
-1  
0
.2 .3.4 .6  
1.0  
2.0  
2.4  
3.0  
3.4 3.6  
D96TL257A  
FREQUENCY (KHz)  
37/49  
STLC3040  
GAIN TRACKING Rx/Tx  
Voutref = voltage on Vout with DDref = -10dBm0  
Voutmes = voltage on Vout with -55dBm0 <  
DDmes < 3dBm0  
Rx gain tracking = 20 log (Vout mes / Voutref)  
- (DDmes - DDref)  
CR[ 1] = 00  
CR[ 2] = 00  
CR[ 3] = 00  
CR[ 4] = F9  
CR[ 5] = 60  
CR[ 6] = 50  
CR[ 7] = 1C  
CR[ 8] = 08  
CR[ 9] = 2F  
CR[10] = 00  
CR[11] = 10  
CR[12] = 03  
Tx gain tracking = starting from the same consid-  
eration of the absolute gain.  
GR = FFh  
GX = FFh  
K = 1000h  
(255)  
(255)  
(4096)  
target DU represents the dBm0 level expected on DU  
with a certain set of coefficient and a Vrac of  
41.4Vrms  
VRac_ref is the amplitude of the sine wave (1kHz) to  
be applied on RAC (pin 16) in order to expect on DU  
a Vpcm dBm0 level with the same set of coefficient.  
| 1000h  
(4096) |  
R
X
| 0h  
| 0h  
| 0h  
(0)  
(0)  
(0)  
|
|
|
target DU (dBm0) = 3.14 + 20 ((0.0414  
3
(2  
| 1000h  
| 0h  
| 0h  
(4096) |  
sqr(2)) / 1.514) 16 (K/8192) (X[1]/8192) (GX/256)  
0.966)  
VRac_ref = 41.4mV 10^ ((Vpcm - target DU)/20)  
(0)  
(0)  
(0)  
|
|
|
| 0h  
B[1..8] = 0  
Z[1..3] = 0  
DUref = dBm0 level at DU with (target DU) ref = -  
10dBm0  
DUmes = dBm0 level at DU with -55dBm0 < (tar-  
get DU) mes < 3dBm0  
Tx gain tracking = (DUmes - DUref) - ((target  
DU)mes - (target DU)ref)  
Reference frequency = 1kHz  
Reference level on DD = -10dBm0 (or expected  
value at Vout, pin 26, in the range of  
14.39mVrms)  
Figure 15. (Valid for 0 < Tamb < 70°C)  
RECEIVE:  
G
(dB)  
2
1.4  
1
0.5  
0.25  
0
-0.25  
-0.5  
-1  
-1.4  
-2  
-70  
-60 -55 -50  
-40  
-30  
-20  
-10  
0
3
10  
D96TL258A  
INPUT LEVEL (dBm0)  
TRANSMIT:  
G
(dB)  
2
1.4  
1
0.5  
0.25  
0
-0.25  
-0.5  
-1  
-1.4  
-2  
-70  
-60 -55 -50  
-40  
-30  
-20  
-10  
0
3
10  
D96TL262  
INPUT LEVEL (dBm0)  
38/49  
STLC3040  
SIGNAL TO NOISE RATIO  
Use the same Test Configuration of Gain Tracking Test.  
Figure 16. (Valid for 0 < Tamb < 70°C)  
S/D  
(dB)  
Input Level  
(dBm0)  
S/DCLOSED LOOP  
(dB)  
35  
30  
25  
20  
-44.5  
-40  
-30  
-20  
-10  
0
19.725  
24.625  
32.716  
34.709  
34.97  
34.997  
35  
15  
TRANSMIT:  
10  
5
+3  
0
-50  
-45  
-40  
-35  
-30  
-25  
-20  
-15  
-10  
-5  
0
5
INPUT LEVEL (dBm0)  
S/D  
(dB)  
Input Level  
(dBm0)  
S/DCLOSED LOOP (dB)  
35  
30  
25  
-44.5  
-40  
-30  
-20  
-10  
0
23.02  
27.9  
34.538  
34.95  
35  
RECEIVE:  
20  
15  
10  
5
35  
+3  
35  
0
-50  
-45  
-40  
-35  
-30  
-25  
-20  
-15  
INPUT LEVEL (dBm0)  
CLOSED LOOP as per Q.552 ITU-T specifications with line impedance = 900Ω  
-10  
-5  
0
5
D96TL259C  
Figure 17:  
Overload Compression (Transmit: measured with sine wave f = 984Hz).  
9
8
7
6
5
ACCEPTABLE  
REGION  
4
3
2
1
0
1
2
3
4
5
6
7
8
9
D96TL266A  
INPUT POWER (dBm)  
39/49  
STLC3040  
IDLE_CHANNEL NOISE Rx/Tx (TTX off)  
(Test Cond. 1)  
DD = idle code (A_law)  
Id_ch_noise at Tx = dBm0 level at DU  
CR[ 1] = 00  
CR[ 2] = 00  
CR[ 3] = 05  
CR[ 4] = F9  
CR[ 5] = 60  
CR[ 6] = 50  
CR[ 7] = 1C  
CR[ 8] = 08  
CR[ 9] = 2F  
CR[10] = 00  
CR[11] = 10  
CR[12] = FF  
Id_ch_noise at Rx = voltage (rms) at Vout  
µ
( Vrms) (psophometric weighted)  
GR = FFh  
GX = B4h  
K = 05A0h  
(255)  
(180)  
(1440)  
| 09CDh  
(2509) |  
R
X
| 042Dh  
| 0919h  
| 39BBh  
(1069) |  
(2329) |  
(-1605)|  
| 178Dh  
| 0E31h  
| 2922h  
| 0CCFh  
(6029) |  
(3633) |  
(-5854) |  
(3279) |  
| 39D3h  
| 0859h  
| 21EDh  
(-1581) |  
(2137) |  
(-7699) |  
Z
B
| 000Dh  
| 3F0Eh  
| 00AB  
| 039Eh  
| 0483h  
| 044Fh  
| 03AB  
(13)  
|
(-242) |  
(171)  
(926)  
|
|
(1155) |  
(1103) |  
(939)  
|
| 3C00h  
(-1024) |  
OUT OF BAND NOISE (Test Cond. 2)  
Out of band signal at Analog output (Rx)  
CR[ 1] = 00  
CR[ 2] = 00  
CR[ 3] = A5  
CR[ 4] = F9  
CR[ 5] = 60  
CR[ 6] = 50  
CR[ 7] = 1C  
CR[ 8] = 08  
CR[ 9] = 2F  
CR[10] = 00  
CR[11] = 10  
CR[12] = FF  
DD 5 frequencies between 2.8 and 3.8kHz + single  
frequency at 1kHz, the total amplitude is 0dBm0  
(in this condition the expected value on 2W at  
1kHz is about 23mVrms)  
GR = FFh  
GX = FFh  
K = 05A0h  
(255)  
(255)  
(1440)  
(
±
)
Vout @ 32KHz 5freq.  
OBN on Vout =  
Vout @ 1kHz  
| 1000h  
(4096) |  
R
X
Z
(0)  
(0)  
(0)  
|
|
|
OBN (out of band noise) min 31dB  
| 0h  
| 0h  
| 0h  
Out of band signal at Digital output (Tx)  
| 1000h  
| 0h  
| 0h  
(4096) |  
VRAC = 5 frequencies between 32kHz  
(0)  
(0)  
(0)  
|
|
|
3.8kHz and 32kHz - 2.8kHz + single frequency  
at 1kHz.  
| 0h  
The total amplitude to be applied on VRAC  
(pin 16) is calculated applying the same  
law of the absolute gain. VRACpicco = 133mV.  
| 39D3h  
| 0859h  
| 21EDh  
(-1581) |  
(2137) |  
(-7699) |  
OBN on Tx = dBm0 level at 1kHz - dBm0 level  
at each frequency reflected in band.  
B[1..8] = 0  
Z[1..3] = 0  
OBN (out of band noise) min 25dB.  
40/49  
STLC3040  
ECHO CANCELLING (Test Cond. 3)  
DD = tone at 1kHz and -5dBm0  
measured_result = (tone level on DD) - (tone level  
onDU)  
CR[ 1] = 20 *)  
CR[ 2] = 00  
CR[ 3] = A5  
CR[ 4] = FD  
CR[ 5] = 60  
CR[ 6] = 50  
CR[ 7] = 1C  
CR[ 8] = 08  
CR[ 9] = 2F  
CR[10] = 00  
CR[11] = 10  
CR[12] = FF  
GR = FFh  
GX = FFh  
K = 0100h  
(255)  
(255)  
(256)  
| 1FFFh  
| 0h  
| 0h  
(8191) |  
R
X
(0)  
(0)  
(0)  
|
|
|
| 0h  
| 1FFFh  
| 0h  
| 0h  
(8191) |  
(0)  
(0)  
(0)  
|
|
|
| 0h  
| 0800h  
| 3000h  
| 1000h  
(2048) |  
(-4096) |  
(4096) |  
Z
B
| 3FE0h  
| 0h  
| 14h  
| 34h  
| 22Ch  
| 4h  
(-32)  
(0)  
(20)  
|
|
|
|
(52)  
(556) |  
(4)  
(8)  
(-32)  
|
|
|
| 8h  
| 3FE0h  
*) CR[1] = 20h means digital loop-back 2 on.  
RETURN LOSS (Test Cond. 4)  
multitone applied on RAC of amplitude 100mVp  
and measure performed on Vout  
CR[ 1] = 00  
CR[ 2] = 00  
CR[ 3] = A5  
CR[ 4] = F9  
CR[ 5] = 60  
CR[ 6] = 60  
CR[ 7] = 1C  
CR[ 8] = 08  
CR[ 9] = 2F  
CR[10] = 00  
CR[11] = 10  
CR[12] = FF  
F(s) - F(m)  
COFISLIC return loss  
----------------  
F(s) + F(m)  
where F(s) is the ideal transfer function  
(RAC/Vout) from simulation  
GR = 0  
GX = 0  
K = 05A0 (1440)  
F(m) is the measured transfer function  
R[1..4] = 0  
X[1..4] = 0  
| 39D3h  
| 0859h  
| 1E13h  
(-1581) |  
(2137) |  
(7699) |  
Z
B[1..8] = 0  
41/49  
STLC3040  
P.S.R.R. from VEE and VCC (Test Cond. 5)  
DD = idle code  
Stimulus applied on VEE and VCC separately as  
a multitone (5 tone) of amplitude 100mVp  
PSRR on Rx (Vout)  
= 20 log (Vout at each tone / amplitude of the  
same tone applied on VEE or VCC)  
if referred to TIP/RING wire  
= above measure - 20log(20)  
(20 is due to the effect of closed loop)  
CR[ 1] = 00  
CR[ 2] = 00  
CR[ 3] = A5  
CR[ 4] = F9  
CR[ 5] = 60  
CR[ 6] = 50  
CR[ 7] = 1C  
CR[ 8] = 08  
CR[ 9] = 2F  
CR[10] = 00  
CR[11] = 10  
CR[12] = FF  
GR = FFh  
GX = B4h  
K = 05A0h  
(255)  
(180)  
(1440)  
| 09CDh  
(2509) |  
PSRR on Tx (DU)  
R
X
(1069) |  
(2329) |  
(-1605)|  
| 042Dh  
| 0919h  
| 39BBh  
considering as dBm0 reference level an ampli-  
tude of 0.775Vrms  
= 20 log ((0.775 10^ (dBm0 level at each  
tone / 20)) / amplitude of the same  
tone applied on VEE or VCC)  
| 178Dh  
| 0E31h  
| 2922h  
| 0CCFh  
(6029) |  
(3633) |  
(-5854) |  
(3279) |  
| 39D3h  
| 0859h  
| 21EDh  
(-1581) |  
(2137) |  
(-7699) |  
Z
B
| Dh  
(13)  
|
| 3F0Eh  
| 00ABh  
| 039Eh  
| 0483h  
| 044Fh  
| 03ABh  
| 3C00h  
(-242) |  
(171)  
(926)  
|
|
(1155) |  
(1103) |  
(939)  
|
(-1024) |  
RING FUNCTIONALITY (Test Cond. 6)  
f ring = 50Hz  
2 WRNG = as volt on = ((CR9 [3..0] 2.039 Vrms + 34.4  
= CR9 [6..4]  
Ring ON  
Vrms)/40)/1 + (fring 200Hz)2  
2WRNG (reported on TIP/RING wire) = (Vout pk  
40) / sqr (2)  
IHOOK_RING = {(1+CR5 [7..4]) 9.6mA/16}/50  
RVR if 1  
Vring on TIP/RING = Vring 17/13  
Ring PAUSE  
CR[ 1] = 80  
CR[ 2] = 03  
CR[ 3] = 20  
CR[ 4] = F9  
CR[ 5] = I prog  
CR[ 6] = FC  
CR[ 7] = 1C  
CR[ 8] = 08  
CR[ 9] = Ring f/V  
CR[10] = FF  
CR[11] = 10  
CR[12] = FF  
2WRNG = V2wpk  
GR = GX = 40h (64)  
K = 06A1h (1697)  
Z = [1..3] = 0  
B = [1..8] = 0  
| 1000h  
(4096) |  
R
| 0h  
| 0h  
| 0h  
(0)  
(0)  
(0)  
|
|
|
| 1000h  
| 0h  
| 0h  
(4096) |  
X
(0)  
(0)  
(0)  
|
|
|
| 0h  
42/49  
STLC3040  
TELETAX (Test Cond. 7)  
| 39D3h  
| 0859h  
| 21EDh  
(-1581) |  
(2137) |  
(-7699) |  
Z
B
2WTTX amplitude on Vout = (10Vrms (CR10[7..0]  
/ 255))/40  
TTx offset = CR10 [7..3] 15mV + X  
| 000Dh  
| 3F0Eh  
| 00AB  
| 039Eh  
| 0483h  
| 044Fh  
| 03AB  
(13)  
|
(-242) |  
where X depends on normal or boosted battery  
(171)  
(926)  
|
|
CR[ 1] = 01h  
CR[ 2] = 00h  
CR[ 3] = A5h  
CR[ 4] = F9h  
CR[ 5] = 60h  
CR[ 6] = 50h  
CR[ 7] = 1Ch  
CR[ 8] = 10h  
CR[ 9] = 2Fh  
CR[10] = 32h  
CR[11] = 10h  
CR[12] = FFh  
(1155) |  
(1103) |  
(939)  
|
| 3C00h  
(-1024) |  
GR = FFh  
GX = B4h  
K = 05A0h  
(255)  
(180)  
(1440)  
TTx amplitude on TIP/RING wire = Vout TTX  
40  
| 09CDh  
(2509) |  
TTx Offset = Vout dc level  
R
X
(1069) |  
(2329) |  
(-1605)|  
| 042Dh  
| 0919h  
| 39BBh  
measurement of 2nd/3rd harmonic noise (psoph.  
weighted on Vout)  
| 178Dh  
| 0E31h  
| 2922h  
| 0CCFh  
(6029) |  
(3633) |  
(-5854) |  
(3279) |  
HALF BATTERY DETECTION (Test Cond. 8)  
target VBIM (VBIMT) represents the voltage to supply  
the VBIM (Pin 25) to toggle the SR.5 bit (VB_2)  
CR[ 1] = 00h  
CR[ 2] = 03h  
CR[ 3] = 00h  
CR[ 4] = F9h  
CR[ 5] = 60h  
CR[ 6] = FEh  
CR[ 7] = FCh  
CR[ 8] = 08h  
CR[ 9] = 2Fh  
CR[10] = 00h  
CR[11] = 10h  
CR[12] = DFh  
target VBIM  
drop  
=
(CR8 [7.5] + 1) 125Ω  
= 2  
+ IT RDC 0.288 + IT RDC  
2
RDC  
Where:  
IT = -440µA  
drop = VOUT for IT = 0  
GR = 40h  
GX = 40h  
K = 06A1h  
(64)  
(64)  
(1697)  
RDC = 820Ω  
Z = [1..3] = 0h (0)  
B = [1..8] = 0h (0)  
| 1000h  
If STLC3040 is in kit with HV (L3000N, L3000S,  
STLC3170) the SR.5 bit (VB_2) toggles when  
|VLINE| > |VOL / 2| see 4.7.1.1 paragraph.  
(4096) |  
R
(0)  
(0)  
(0)  
|
| 0h  
| 0h  
| 0h  
|
|
Figure 18.  
| 1000h  
| 0h  
| 0h  
(4096) |  
X
(0)  
(0)  
(0)  
|
|
|
| 0h  
chip status: conversation normal polarity  
DU  
6
26  
25  
VOUT  
IT  
VBIM  
19  
440µF  
D98TL379  
43/49  
STLC3040  
GROUP DELAY  
Guaranteed by design  
Group Delay absolute values:  
Signal level 0dBm0  
Symbol  
DXA  
Parameter  
Transmit delay  
Receive delay  
Test condition  
Min.  
Typ.  
Max.  
300  
Unit  
µs  
f = 1.5kHz  
f = 1.5kHz  
DRA  
250  
µs  
Figure 19:  
Group Delay Distortion receive and transmit: Signal level 0dBm0, fTEST @ TGmin  
500  
400  
300  
200  
150  
100  
85  
0.6  
2.8  
0
0.5  
1
1.5  
2
2.5 2.6  
FREQUENCY(KHz)  
3
3.5  
4
D97TL299  
44/49  
STLC3040  
Table 13:  
Complete list of mode control bits.  
Mode name  
for SLIC  
Kit  
CI.7  
CI.6  
CI.5 CR1.7  
|
CR8.3 CR0.5 CR1.6 CR7.1 C/I  
Mode  
Mode  
HV  
Part  
6V Interface  
PDN C1 C2  
CR1.3|CR1.2  
|
Hook LV Part  
PoweDen  
+ 2 15k  
Ext. Ind.  
Stand-by  
0
0
0
0
X
| X  
X
X
X
X
X
Poweden  
Hiz not Vlv Vlv  
0
0
0
0
0
0
0
0
0
1
1
1
0 | 0  
0 | 0  
0 | 0  
X
X
X
X
X
X
X
X
X
1
0
0
X
0
1
StdBy  
StdBy  
StdBy  
StdBy  
StdBy  
Acts.  
LoZ Vhv Vhv  
LoZ Vhv Vhv  
LoZ Vhv Vmv  
Ground Start  
Loop open  
Conv. N.P.  
Conv. R.P.  
Boost N.P.  
Boost R.P.  
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
X
X
X
X
X
1 | 1  
X
X
X
X
X
X
X
X
0
1
0
1
X
X
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
StdBy  
HiA  
LoZ Vmv Vhv  
X | X  
PowDen PowDen HiZ Vlv Vlv  
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
Act.  
Act.  
Act.  
Act.  
Act.  
Act. + RP LoZ Vhv Vlv  
Boost LoZ Vmv Vmv  
Boost+RP LoZ Vmv Vlv  
LoZ Vhv Vmv  
Conv. NP+ TTx  
12kHz/16kHz  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Act. + OF  
Act.  
Act.  
LoZ Vhv Vmv  
Conv. NP+ TTx  
Reversal  
Act. + RP LoZ Vhv Vlv  
Conv. RP+ TTx  
12kHz/16kHz  
Act. + OF Act. + RP LoZ Vhv Vlv  
Conv. RP+ TTx  
Reversal  
Act.  
Act.  
LoZ Vhv Vmv  
LoZ Vmv Vmv  
LoZ Vmv Vlv  
LoZ Vmv Vlv  
LoZ Vmv Vmv  
Boost NP + TTx  
12kHz/16kHz  
Act. + OF Boost  
Boost NP + TTx  
Reversal  
Boost +  
Act.  
RP  
Boost RP + TTx  
12kHz/16kHz  
Boost +  
Act. + OF  
RP  
Boost RP + TTx  
Reversal  
Act.  
Boost  
1
1
1
0
0
0
0
0
0
X
X
X
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
X
X
X
X
X
X
X
X
X
1
0
0
X
0
1
StdBy  
StdBy  
StdBy  
StdBy  
StdBy  
Act.  
LoZ Vhv Vhv  
LoZ Vhv Vhv  
LoZ Vhv Vmv  
Ring. Pause  
red. Power  
Ring red Pow  
1
0
1
X
0 | 0 or 1 | 1  
X
0
X
X
0
Ring +RB  
Ring  
LoZ Vlv Vmv  
Ring red Pow  
+ Reversal  
Ring  
+RP  
1
0
1
X
0 | 0 or 1 | 1  
X
1
X
X
0
Ring +RB  
LoZ Vlv Vlv  
1
1
0
0
1
1
X
X
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
X
X
X
X
X
X
1
0
1
1
StdBy  
StdBy  
StdBy  
Act.  
LoZ Vhv Vhv  
LoZ Vhv Vmv  
Stand-By  
Ring Pause  
1
1
0
X
0 | 0 or 1 | 1  
X
0
X
X
X
Ring  
Ring  
LoZ Vlv Vmv  
Ring Pause  
+ Reversal  
1
1
0
X
0 | 0 or 1 | 1  
X
1
X
X
X
Ring  
Ring +RP LoZ Vlv Vlv  
1
1
1
1
1
1
X
X
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
X
X
0
0
X
X
X
X
0
1
Ring +RB  
Ring  
Ring  
Ring  
LoZ Vlv Vmv  
LoZ Vlv Vmv  
Ringing  
1
1
1
1
1
1
X
X
0 | 0 or 1 | 1  
0 | 0 or 1 | 1  
X
X
1
1
X
X
X
X
0
1
Ring +RB Ring +RP LoZ Vlv Vlv  
Ringing + RP  
Ring  
Ring +RP LoZ Vlv Vlv  
0
1
0
0
1
1
0
0
1
1
1
X
0
0
0
1
0
1
1
1 | 0  
1 | 0  
1 | 0  
1 | 0  
1 | 0  
1 | 0  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
StdBy  
StdBy  
HiA  
HiA  
HiA  
HiA  
HiA  
HiA  
LoZ Vmv Vhv  
LoZ Vmv Vhv  
LoZ Vmv Vhv  
LoZ Vmv Vhv  
LoZ Vmv Vhv  
LoZ Vmv Vhv  
X
X
X
X
X
Act.  
HiA  
HiB  
Act. +OF  
Ring  
Ring +RB  
0
1
0
0
1
1
0
0
1
1
1
X
0
0
0
1
0
1
1
0 | 1  
0 | 1  
0 | 1  
0 | 1  
0 | 1  
0 | 1  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
StdBy  
StdBy  
Act.  
Act. +OF  
Ring  
Ring +RB  
HiB  
HiB  
HiB  
HiB  
HiB  
HiB  
LoZ Vlv Vhv  
LoZ Vlv Vhv  
LoZ Vlv Vhv  
LoZ Vlv Vhv  
LoZ Vlv Vhv  
LoZ Vlv Vhv  
X
X
X
X
X
’0 | 1’: at the Bits HiA and HiB means  
HiA = 0 and HiB = 1.  
’+RB’: Additional ring burst on.  
’+OF’: Additional out of band frequency.  
’+BB’: Feeding with additional +Vbatt.  
’X’: don’t care means any combination is valid ’+RP’: Additional DC voltage in A/B wire  
in this mode. reversed.  
’LoZ’: The PDN output (LW Part) pin has low ’HiZ’: The PDN output Pin (LV partI has high  
impedance to ground. impedance or +5V to ground).  
45/49  
STLC3040  
TIMING OF GCI INTERFACE  
Figure 20:  
DCL, FSC, DU and DD Characteristics.  
t
t
DCLh  
DCL  
DCL  
t
FSC  
t
FSC_H  
t
FSC_S  
FSC  
t
DD_H  
t
DD_S  
DD  
DU  
t
dDU  
D96TL268  
Switching characteristics  
Limit Values  
typ.  
Symbol  
Parameter  
Units  
min.  
max.  
tDCL  
tDCL  
Period DCL ’slow’ mode (*)  
Period DCL ’fast’ mode (**)  
DCL Duty Cycle  
1/2048kHz  
1/4096kHz  
40  
60  
%
µs  
ns  
ns  
ns  
ns  
ns  
tFSC  
tFSC S  
tFSC H  
tDD S  
tDD H  
tdDU  
Period FSC  
125  
FSC set-up time  
70  
40  
20  
50  
tDCLh  
FSC hold time  
DD data in set-up time  
DD data in hold time  
DU data out delay  
150 (***)  
250  
(*) DCL = 2048KHz: tFSC = 256 * tDCL  
(**) DCL = 4096KHz: tFSC = 512 * tDCL  
(***) Depending on Pull up resistor (typical 1....10k)  
46/49  
STLC3040  
APPENDIX 1  
Internal Protections of digital pins.  
Figure A1.  
INPUT  
VPOS  
PAD  
VNEG  
VNEG  
OUTPUT  
VPOS  
VNEG  
D97TL300  
VPOS = VCC or VDD  
VNEG = DGND or AGND or VEE  
47/49  
STLC3040  
mm  
inch  
DIM.  
OUTLINE AND  
MECHANICAL DATA  
MIN. TYP. MAX. MIN. TYP. MAX.  
A
B
17.4  
16.51  
3.65  
4.2  
17.65 0.685  
16.65 0.650  
0.695  
0.656  
0.146  
0.180  
0.108  
C
3.7  
0.144  
D
4.57 0.165  
2.74 0.102  
d1  
d2  
E
2.59  
0.68  
0.027  
14.99  
16  
0.590  
0.630  
e
1.27  
12.7  
0.46  
0.71  
0.050  
0.500  
0.018  
0.028  
e3  
F
F1  
G
0.101  
0.004  
M
M1  
1.16  
1.14  
0.046  
0.045  
PLCC44  
48/49  
STLC3040  
ESD  
- The STMicroelectronics Internal Quality Standards set a target of 2 KV that each pin of the device should withstand in a series of tests  
based on the Human Body Model (MIL-STD 883 Method 3015): with C = 100pF; R = 1500and performing 3 pulses for each pin versus VCC  
and GND.  
Device characterization showed that, in front of the STMicroelectronics Internaly Quality Standards, all pins, of STLC3040 except H.V ones  
(11, 12), withstand at least 1.5kV. H.V. pins n. 11, 12 withstand up to 350V due to their specific functionality.  
The above points are not expected to represent a pratical limit for the correct device utilization nor for its reliability in the field. Nonetheless  
they must be mentioned in connection with the applicability of the different SURE 6 requirements to STLC3040.  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is  
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are  
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products  
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics  
© 1999 STMicroelectronics – Printed in Italy – All Rights Reserved  
STMicroelectronics GROUP OF COMPANIES  
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -  
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.  
http://www.st.com  
49/49  

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