STLC3040-TR_技术文档

STLC3040

®

SUBSCRIBER LINE INTERFACE CODEC FILTER, COFISLIC

Single chip CODEC and FILTER including all

LOW-VOLTAGE SLIC functions.

Advanced 12V BJT, 5V CMOS 0.8um technol-

ogy.

Low external component count.

Over-sampling A/D and D/A conversion.

No functional trimming or adjustments re-

PLCC44

quired.

ORDERING NUMBERS: STLC3040

STLC3040-TR

Serves a wide range of specifications; i.e. ITU-

T, LSSGR.

A-law, and µ-law PCM and Linear voice cod-

ing, sw selectable

Figure 1: Pin Connection (Top view)

GCI compatible interface.

Programmable Digital-Filters for impedance-

matching, hybrid-balance, frequency-response

and gain.

6

5 4 3 2 1 44 43 42 41 40

Programmable Feeding-Resistance (2 x 50Ω

to 2 x 400Ω) and current-limiting (0-69.3mA).

Programmable voltage-drop according to

transmission needs.

12kHz/16kHz Teletax Generation with Pro-

grammable Level 0-10 Vrms in 40mV steps in-

cluding shaping and filtering.

Integrated Ring-Generator with Zero-Crossing.

Programmable frequency from 16.6Hz to

60Hz, programmable level up to 85Vrms, Inte-

grated auto ring-trip.

IO1

IO2

C1

7

39

38

37

36

35

34

33

32

31

30

29

O1

8

I1

9

SIR2

MR

IDH

C2

10

11

12

13

14

15

16

17

VL1

VL2

SIR0

CAP

IL

V

CC

V

EE

IDM

IDL

RAC

SIR1

STR2

EXT

Signalling functions ON/OFF - Hook, Gnd-key

with filter and Programmable persistence

check.

18 19 20 21 22 23 24 25 26 27 28

D94TL161D

Advanced test capabilities:

On-board line tests and circuit tests.

Signalling tests for meterpulse TTX and Ring-

ing.

On chip Line-card identification.

Tone generator for circuit test.

3 Loop-back paths.

DESCRIPTION

The subscriber line codec-filter, STLC3040, is

fabricated in BiCMOS (12V bipolar / 5V CMOS)

technology. It uses Digital-Signal-Process-

ing(DSP) to implement central-office telephone in-

terface features: DC-feed, Supervision, PCM-

Codec-Filter, Ring, Teletax metering (TTX) and

Test functions. The STLC3040 is fully program-

mable and needs few external resistors and ca-

pacitors.

Three operating conditions:

Power Down, Active, Ringing. Off-hook pro-

grammable threshold-level in each of these

conditions.

Interface to High-Voltage SLIC to select

modes, provide hard or soft Polarity-Reversal

and sense HV (L3000N, L3000S, STLC3170)

High Thermal condition.

On-hook transmission capability.

Selectable 2/4MHz backplane clock.

Standard PLCC 44 package.

The STLC3040 interfaces the subscriber’s line via

the High-Voltage (HV) (L3000N, L3000S,

STLC3170) device and the central-office back-

1/49

January 1999

STLC3040

is possible in all operating modes as described in

section 4.

Ring-signal with zero-crossing start/stop injection

is generated on chip with programmable fre-

quency and amplitude. In addition, when Ring-

trip is detected, the Ring-signal is automatically

disconnected at the next zero-crossing.

Power consumption is kept low by providing a

"Power-Down" mode where the HV-SLIC is

switched off (Power Denial). A set of internal re-

sistors connected to the line allows Off-hook de-

tection in this mode. Overall power dissipation is

around 50mW (max.) in Power Down mode.

Several testing features are included in the

STLC3040, both for self-test and to test line leak-

age, capacitance ..etc, thus saving on test equip-

ment and relays. Measured DC quantities are dig-

itized and sent via the B1 voice channel to the

backplane. With proper software selection each

signal can be modulated by a 1KHz carrier before

being sent to B1 voice channel. Programmable

linear code, software selectable, boosts the calcu-

lation resolution.

DESCRIPTION (continued)

plane via a GCI compatible interface (see fig.2).

The GCI handles all STLC3040 control and voice

channel.

The STLC3040 processes the transversal line-

current sensed by the ST HV (L3000N, L3000S,

STLC3170) Line Driver Circuit and generates

voltage-drive to the line via the HV (L3000N,

L3000S, STLC3170), thus synthetizing the imped-

ances required by various world administrations .

Line impedances as well as the two-to-four wire

conversion synthesis are software programmable.

Also Transmit (Tx) and Receive(Rx) AC fre-

quency–response, determined by DSP-filters,

guarantee voice-band flat-response. Tx and Rx

Gains are programmable as well. Digitized voice

can be encoded on A-law or u-law.

The DC characteristic is obtained by selecting

limit-current value, DC-feed resistance (2 X 50

steps) and Drop-voltage. It also permits On-hook

transmission and TTX pulse injection with filtering

and shaping. TTX metering pulse generation (12

or 16kHz) has programmable amplitude up to 10

Vrms.

Ω

Sigma-Delta converters (ASD: Analog, DSD: Digi-

tal) make the conversion independent of technol-

ogy parameters (fig. 3).

Off-hook detection with programmable thresholds

Figure 2: Functional Diagram.

LV

HV

STLC3040

L3000N

FSC

DIGITAL

SIGNAL

PROCESSOR

RP1

RP2

DCL

GCI

VOUT

VIN

TIP

I_TIP

INT.

DU

A=20

DD

RING

I_RING

A=-20

Iline

IT

CURRENT

SENSORS

ANALOG

FRONT

END

IL

REF

C2

PDO

C2

C1

HV

CONTROL

C1

VBIM

CDVB

ACDC

CAC

CAP

RAC

RDC

REF

V_CC

D95TL204B

STLC3040 PIN DESCRIPTION (This list is grouped according to Function)

N.

Symbol

Type (*)

Description

POWER SUPPLY

1

2

27

33

34

DGND

VDD

AGND

VEE

PS

Digital Ground

+5V Digital Supply Voltage

Analog Ground

-5V Analog Supply Voltage

+5V Analog Supply Voltage

VCC

2/49

STLC3040

STLC3040 PIN DESCRIPTION (continued)

N.

GCI

40

Symbol

Type (*)

Description

SEL24

DI

Select Clock Frequency for GCI Interface 2MHz/4MHz not affecting the data rate

(2Mbit/s)

If SEL24 = 0, Clock Frequency = 2048KHz

If SEL24 = 1, Clock Frequency = 4096KHz

43,42, TS0,TS1,

DI

GCI Select Time Slot Identifier Pins

41

3

4

5

TS2

FSC

DCL

DD

DI

Frame Sync 8kHz GCI Interface

Master Data Clock GCI Interface

Data Down link GCI Interface

6

DU

OD

Data Up link GCI Interface (Open Drain Driver)

INTERFACE TO HV SLIC

9

C1

AI/O

State Control Signal 1. Combination of C1 and C2 defines HV (L3000N, L3000S,

STLC3170) operating mode. Current sense for thermal indication.

10

28

C2

AO

State Control Signal 2. Combination of C1 and C2 defines HV (L3000N, L3000S,

STLC3170) operating mode.

Power down output. Proper bias current is provided to HV (L3000N, L3000S, STLC3170) by this

pin. When the current is 0 the HV (L3000N, L3000S, STLC3170) goes in Power Denial (high

impedance). Proper combinations of PDO with C1, C2 set additional operating modes for

STLC3170 High Voltage Interface.

PDO

AO

11,12 VL1, VL2

AI

Comparator Input. These are inputs of the comparator that senses the line voltage in

Power Denial allowing Off/Hook detection in this mode.

15

19

25

26

IL

IT

VBIM

VOUT

AI

Longitudinal Line-Current input IL = (I_TIP- I_RING)/100.

Transversal Line-Current input IT=(I_TIP+ I_RING)/100.

Battery image monitor.

Output feeding the line voltage (DC, AC, RING, TTX) through H.V. HV (L3000N,

L3000S, STLC3170).

AO

I/O

7, 8

39

IO1, IO2

O1

DI/O

DO

DI

Programmable GCI controlled I/O.

Digital output written via GCI.

Digital input read via GCI.

38

I1

MISCELLANEOUS FUNCTION

29

36

EXT

MR

DI

External Ring Sync. Input.

Master Reset Input. Active High. The STLC3040 is forced in Loop-open and internal

registers are preset to default values.

31,32 IDL, IDM

AI

DI

AI/O

AI

Identification Code Signals, M+L ternary digits

H most significant bit, L least significant bit.

Capacitor must be connected to this pin. Its value defines the Soft Battery Reversal slope.

AC-Synthesis Reference Resistor.

AC/DC Line Split. Scaled line-current output, DC feedback input.

Splitter Capacitor. Scaled AC line-current input.

35

IDH

CAP

RAC

ACDC

CAC

RDC

REF

14

16

20

21

22

23

AI

AI/O

DC-Synthesis Reference Resistor.

Reference Voltage Output. A resistor on this pin sets the internal reference current.

UNUSED

18,24 STR0,STR1 DI/O

30,44 STR2,STR3

Reserved for testing, must be shorted to DGND.

13,17 SIR0, SIR1

37 SIR2

DI/O

Must be left open.

Can be left open

(*) Type Description

Type Description

AI

AO

Analog Input

Analog Output

DI

PS

Digital Input

Chip Power/Ground

DO

OD

Digital Output

Open Drain Output

AI/O Analog Input/Output

DI/O Digital Input/Output

3/49

STLC3040

different conditions are present and depend on

loop resistance.

4 FUNCTIONAL DESCRIPTION

The STLC3040 is implemented by a combination

of analog and digital circuits, merging the best

available analog and digital processing perform-

ances of the BiCMOS technology. In particular

two main blocks of the STLC3040 can be identi-

fied: an analog front end interfacing the HV

(L3000N, L3000S, STLC3170) and a programma-

ble DSP. (See fig. 3)

a) Resistive Feed Region: the SLIC kit operates

as a voltage source with a series resistance

Ω

50 ), where n can be

equal to (2Rp+n

2

programmed from 1 to 8 via CR8 register. Vari-

ous values of voltage drops are possible as

shown in Fig. 4.

b) Constant current region: when IL reaches the

programmed limiting current value (from 0 to

69.3mA; 1.1mA step via CR6 register), the Kit

operates as a proper constant current source.

(see Fig. 4).

4.1 - Signal processing.

The line-current signal received in pin IT from the

HV (L3000N, L3000S, STLC3170) is mirrored out

of pin ACDC. On its way, its value is sensed to

determine Off-Hook signalling. While in active

conversation this istantaneous sensing is used for

fast Hook signalling such as numbering. Then

line-current AC and DC parts are splitted by RDC

and CAC. The signal is processed to realize AC

and DC impedance synthesis. Indeed IT pin car-

ries the AC current due to voice signals present at

line terminals and the DC current related to the

specific V-I operating point.

During Stand-By mode signal is created by the

DC current after AC part has been removed. This

filtered Hook produces robust signalling in Stand-

by mode or pause-period during reduced-power

Ring mode.

Concerning AC Processing the AC current-signal

is converted to voltage on the reference resistor

Ω

RAC (1620 ).

Line impedance (real or complex) synthesis is

carried out thanks to programmable filters. All the

filters are integrated in the digital side of COFIS-

LIC except the so called KA filter that is in the

Analog Front End.

KD and Z (in digital side) filters allow to match the

line impedance if properly programmed. Further-

more KA ensures stability to impedance synthesis

loop.

In the Receive direction (Rx), the Analog Front

End (AFE) receives a 1-bit modulated composite

signal, which represents part of the voltage to be

forced into the line. It performs DAC and filtering

As far as the DC characteristic is concerned, two

Figure 3: Block Diagram.

DIGITAL SIGNAL PROCESSOR

ANALOG FRONT END

Post

Filter

A/u

exp.

GR

R

+

DSD

LB1

LB3

Rx

FSC

DCL

DU

TTX

RING

TEST

Echo

Canc.

B

+

VOUT

GCI

INT.

Z

DD

Tx

KA

LB1

LB2

LB3

+

A/u

Comp.

GX

X

+

KD

DEC

ASD

ANTIALIAS

FILTER

TTX

Canc.

Ilim

DC Char

Curr. buff.

RDC

ACDC

CAC

RAC

IT

RAC

RDC

D95TL205D

4/49

STLC3040

Figure 4.

I

L

V_DROP= 9.6V + V_dTTX.40 (see par 4.3.2.1)

I_LIM: 0-70mA 1.1mA step

I

LIM

V

DROP

R

FEED

= 2 * R + n * 100Ω

P

V

BAT

V

L

V

OL

I

L

100mA

(typ)

RING MODE

R

FEED

= 2R

P

V

L

V

-22V

BAT

I

L

I

LIM

STAND-BY MODE

_LIM: 0-70mA 1.1mA step

I

R

FEED

= 2 * R + n * 100Ω

P

V

L

V

BAT

-5.85V

D95TL208D

functions. This voltage is then combined with the

AC and DC analog impedance signals, plus a

TTX pulse, in a summing buffer that feeds the Vin

pin of the HV (L3000N, L3000S, STLC3170).

The architecture of the digital section is based on

Digital Signal Processor which synthetises 7 digi-

tal filters (B, Z, X, R, KD, GX, GR). KA uses the

some register value as KD. In Table 1 you can

find the number of coefficients and their bit width

for each filter.

deep registers. These internal filters can be en-

abled setting the most significant 5 bits of CR4

register and CR11 (1). PCM encoding and ITU-T

high/lowpass-filtering are done by dedicated state

machines. Setting the bit 0 of CR4 register A-law

µ−

or law can be selected.

In order to match the complex line impedance,

both amplitude and phase can be programmed

using Filter Z.

The two to four wires echo cancellation is imple-

mented thanks to programmable echo canceler

(B Filter) with Gain and Group-delay equalizer.

Table 1:

Two programmable FIR filters X and R, can be

set in order to guarantee the best overall line fre-

quency response in the frequency domain, ac-

cording to the local specifications. In this way the

signal distorsion can be reduced with 14-bits

resolution.

Gain Setting, both in transmission and in receive,

is done by two FIR filters (GX for transmission,

GR for Receive).

A coefficient optimization software let the users

calculate GX and GR filters coefficients.

In transmission the maximum achievable gain

without distortion is 3dB.

NUMBER OF

COEFFICIENTS

COEFFICIENT

WIDTH

FILTER

B

R

8

4

1

3

14 BITS

X

14 BITS

GR

GX

KA, KD

Z

8 BITS

8, 14 BITS (*)

14 BITS

(*) KA is a subset of KD = most significant bits, (5-12) but sign bit,

of KD register.

Filter coefficients can be programmed by 14 bits

5/49

STLC3040

In receive the maximum programmable gain is

0dB.

Table 3:

PDO = 50 A

µ

Gain step resolution in both sides (Rx and Tx) de-

pends on the value of the gains. See table below

to gain/step accuracy.

pin 9 (C1)

(*)V^mv

(*)V^hv

(*)Vlv

(*)V^hv

ST-BY

TIP OPEN RING OPEN

pin 10

(C2)

Table 2.

(*)V^mvCONV.NP

(*)V^lvCONV.RP

BB.NP

BB.RP

RING NP

RING RP

Tx & Rx Gain

Step accuracy

0.070dB

0.14dB

Xmax - 6dB (1/128)

Xmax - 12dB (1/64)

Xmax - 18dB (1/32)

Xmax - 24dB (1/16)

Xmax - 30dB (1/8)

Xmax - 36dB (1/4)

Xmax - 42dB (1/2)

µ

PDO = 0 A

pin 9 (C1)

(*)V^mv

0.27dB

(*)V^hv

(*)Vlv

0.56dB

(*)V^hvExt. Indication Ext. Indication

Ext.

Indication

1.16dB

2.5dB

(*)V^mvExt. Indication

(*)V^lvExt. Indication

Ext.

Indication

Ext.

Indication

10

(C2)

6.0dB

Tx: Xmax = 3dB; Rx: Xmax = 0dB

Ext.

Indication

Loop Open

(HV Internal

Resistors

The Voice Signal Processing is shown in Block

diagram in Fig.3.

In the RX direction, after being decoded, the voice

sample passes through a set of interpolator and

correction filters. The signal is finally oversampled

to a high-rate of 256kHz before being summed to

the feed-back impedance synthesis signal.

disconnect)

(*) V^hv, V^mv, V^lvsee digital interface electrical characteristics.

Through PDO pin (pin 28) the STLC3040 forces

the HV (L3000N, L3000S, STLC3170) in Power

Denial if the current at this pin is 0. When the

µ

STLC3040 sinks 50 A the HV (L3000N, L3000S,

STLC3170) will be turned on. In Power Denial,

TIP and RING wires are disconnected from the

HV (L3000N, L3000S, STLC3170) driver (Power

Analog circuits performs Off-Hook sense and al-

lows On-Hook Signaling.

The longitudinal line current provided by the HV

(L3000N, L3000S, STLC3170) is sensed at pin IL;

Ground Key signalling is activated when the ab-

solute longitudinal current on IL pin exceeds

threshold. A low pass filter and programmable

persistance filter (register CR3) elaborates the

detection.

µ

Denial). Table 3 related to PDO = 0 A is valid

only for STLC3170.

VL1, VL2 pins sense, the Off-Hook when HV

(L3000N, L3000S, STLC3170) is in power denial,

allowing very low power consumption in On-Hook

condition.

Other important features, which usually require

external circuitry, like Test Tones, Ringing, Meter-

ing Impulse Injection are programmable via soft-

ware. Ring signals can be programmed both in

Amplitude and Frequency via CR9 register.

The Metering Pulse Injection Level can be set by

the CR10 register. Ring-Trip detection is per-

formed by a dedicated internal circuitry.

The Vbim pin receives from the HV (L3000N,

L3000S, STLC3170) an information on the actual

battery voltage (Vbim = Vbat/40), this voltage is

then compared with the line voltage and one bit is

set in the upstream data flow if Vline < (V_OL/2).

This allows the system to be tailored for different

line requirements.

Line and circuit-test functions are discussed in

detail in the appendix.

The HV (L3000N, L3000S, STLC3170) is driven

by the STLC3040 through two ternary pins C1

and C2 (pin 9 & 10 of STLC3040) that define the

operating state of the HV (L3000N, L3000S,

STLC3170) (Table 3).

C1 and C2 are set according to the content of the

bytes received by STLC3040 at DD pin (pin 5) of

the GCI Interface. C1 pin is internally tied to a

current-sensing circuit. It senses an extra current

that the HV (L3000N, L3000S, STLC3170) issues

when in thermal overload conditions.

4.3 Slic Kit Operating Modes

STLC3040/HV (L3000N, L3000S, STLC3170) kit

can work in three main modes:

- POWER DOWN

- ACTIVE

- RING

Each mode is selected by Command-Indicate

(C/I) and Monitor GCI channels. Line State

changes are signalled through either upstream

C/I or SR register. During the switching between

any two modes the indication is frozen for

10msec in addition to the programmed persis-

6/49

STLC3040

tance.

RING pins; theHV shows on TIP pin the RT im-

pedance and on RING pin the RR impedance if it

integrates the 2 external resistors RT and RR

(STLC3170). This mode is used to get a low

power consumption obtaining supervision only via

the STLC3040 and a resistive sensing network.

The total power consumption of the SLIC Kit in

this mode is under to 50mW (being almost 0 the

consumption from battery).

All operating modes with related C/I command

bits and CR register bits are shown in table 13

pag 45.

4.3.1 POWER DOWN

In this condition SLIC Kit reduces strongly its

power consumption allowing Off-Hook detection.

Only the internal circuitry dedicated to the Off-

Hook detection is switched on.

C/I and CR1 register configuration (programmed

by Monitor) defining Power Down Submodes are

here below shown:

4.3.1.2 - Loop Open

This mode can be selected only if the High Volt-

age integrates the two external resistors (RR, RT

see fig. 5) of the feeding and sensing circuitry.

This is implemented on the STLC3170 high volt-

age device.

Table 4: Power Down Submodes

SLIC KIT MODE

C/I C/I C/I CR1 CR1 CR1

(7)

(6)

(5)

(7)

(3)

(2)

4.3.1.3 - Stand-By

EXTERNAL

INDICATION

0

X

SLIC behaves like a constant current source with

typical 7mA feeding current. Open loop voltage is

equal to (V^bat- 5.85V). COFISLIC power con-

sumption is reduced to 150mW typical. Current

limit and Off-Hook threshold are programmable

by register CR7. Both off-hook and ground-key

detectors are operating.

LOOP OPEN

STAND BY

0

1

0

X

1

X

0

1

X

0

1

GROUND START

4.3.1.1 - External Indication

4.3.1.4 - Ground Start

When this mode is selected both STLC3040 and

HV (L3000N, L3000S, STLC3170) are set in

Power Denial. STLC3040 cuts the bias current,

sunk by the HV (L3000N, L3000S, STLC3170) via

the PDO pin. In this mode the HV (L3000N,

L3000S) shows a high impedance on TIP and

The SLIC is set in Stand-By with the TIP wire (the

most positive wire) in high impedance.

The current feeding is equal to Stand-By mode

current feeding.

Figure 5: Application Diagram.

BGND AGND VCC

VB+

VCC VDD VEE AGND DGND

RT

VIN

REF

IT

VOUT

EXT

RP

SEL24

DU/DD(2)

DCL

TIP

PDO

IT

MNT

FSC

IL

TSn(3)

IOn(2)

O1

C1

L3000S

Power SO20

STLC3040

44PLCC

RP

RING

RR

C2

I1

VBIM

MR

IDn(3)

STRn/SIRn(7)

CDVB

DS

VB-

BGND

VL2

VL1

CAP

REF

RAC

RDC

ACDC

CAC

REF

CAP

D95TL203B

V_CC

7/49

STLC3040

in 1.1mA steps ranging from 0mA to 69.3mA. In

resistive feeding region SLIC kit operates like a

constant voltage source with a series impedance

4.3.2 - ACTIVE

This operating mode is selected by the card proc-

essor after an Off-Hook detection in order to allow

signal transmission on the line. Both Off-Hook

and ground-key detectors are operating.

GCI Command - Indicate channel and CR1 regis-

ter configuration (programmed by GCI Monitor)

defining Active modes are herebelow shown:

Ω

Rfeed = 2Rp+n 2 50 (being Rp the external

protection resistor and n a value set from 1 to 8

via CR8 register).

Voltage drop (Fig. 4) can be programmed in order

to optimize voltage feeding characteristic, accord-

ing to AC signal swing requested (ex: voice, voice

+ 2Vrms TTX, voice + 5Vrms TTX):

Table 5:

V_DROP= Vd3000 + 40 (VdAC + VdTTX)

SLIC MODE

C/I

(7)

C/I

(6)

C/I CR1 (*)CR1 (*)CR1

Vd3000 = drop due to internal HV (L3000N,

L3000S, STLC3170) architecture

(2.8V typ.)

(5)

(7)

(3)

1/0

(2)

1/0

ACTIVE

0

1

0

X

ACTIVE + TTX

1

X

VdAC = AC headroom on Vout (170mV typ.)

(*) This condition refers to STLC3040 only. If CR1.3 and CR1.2 are

equal (either 0 or 1) both STLC3040 and HV (L3000N, L3000S,

STLC3170) are in Active State. If CR1.3 and CR1.2 are different, one

of two line wires will be set in high impedance, while the STLC3040

will still be in Active mode.

VdTTX = TTX headroom on Vout (from 0 to 465mV

(15x31) typ. depending on programmed TTX level).

At HV (L3000N, L3000S, STLC3170) two wires

the following equation must be used:

Current Limit and Off-Hook threshold are pro-

grammable by CR6 register. If the fifth bit of the

Command-Indicate channel is set to 1 the Teletax

Signal is superimposed to the voice signal.

V^{DROP(TIP/RING)}= 9.6V + CR10 [7..3] 15mV 40.

4.3.2.2 - Metering Generation

TTX signal is internally generated, filtered and

shaped. Shaping is carried out by a gradual in-

crease of metering pulse level of a level step (see

CR10 register) per signal half period (please see

Fig. 6). TTX can be programmed both in fre-

quency (12 or 16 KHz ) and open loop amplitude

(from 0 to 10Vrms in 255 steps). The output im-

pedance at TTX frequency is just 2 x R_p; there-

fore the proper value should consider the drops

4.3.2.1 - DC feeding

As far as DC characteristic is concerned, SLIC is

basically working as a constant current device. It

turns automatically into a resistive feeding when

the programmed current limitation value cannot

be held due to high line resistance. In active

mode the constant current value is programmable

Figure 6: TTX Shaping

∆V

SS

∆V

S

TIM

D96TL265A

∆V ≡ 2 CR10 LSB

S

∆V ≡ PROGRAMMED VOLTAGE AS PROG IN CR10

SS

8/49

STLC3040

across the 2R^p. Filtering is performed inside the

device without external circuitry.

sent to C/I upstream.

Feeding voltage polarity can be reversed in both

soft and hard ways under software command.

4.3.3.2 - Power Reduced Ring

The modes in Table 6 differ only during the ring-

pause phase.

During the pause of reduced-power-ring mode the

SLIC Kit is set in Stand-By.

The pause state is forced by stop ring command

(C/I.5 downstream = 0) or by the detection of Off-

Hook.

4.3.2.3 - Boost Battery

To supply very long lines (high loop resistance),

the SLIC can be set in "Boost battery" mode. In

this mode the line is fed with a total battery volt-

age equal to |Vb+| + |Vb-|, keeping the same cur-

rent limiting values as in active mode. The Vb+

battery is the same positive supply voltage

needed for ringing generation.

4.3.3.3 - Unbalanced Ringing

The device allows an unbalanced Ring applica-

tion. This application requires an external ringing

generator. A digital I/O pin can be used to drive

the external relay driver.

An external ring sync. signal synchronised on the

Vring zero crossing, must be provided on pin 29

of STLC3040. The external ring frequency must

be the same as the value programmed in the in-

ternal register.

4.3.3 - RING

In this mode COFISLIC provides ringing signal

equivalent to a maximum 85Vrms ring line volt-

age. HV L3000N and L3000S handle a maximum

65Vrms balanced ring signal; HV STLC3170 han-

dles a maximum 85Vrms. It is possible to reduce

power consumption if Power Reduced Ring mode

is chosen. The output impedance is represented

only by the two Rp protection resistors and the

current is limited to 100mA.

4.4 - TESTING FEATURES

C/I and CR1 register configuration (programmed

by GCI monitor channel) define Ring conditions

as herebelow shown:

STLC3040/HV (L3000N, L3000S, STLC3170) kit

allows to perform up to 11 tests. They are aimed

at covering the following issues.

1. Line and Battery Characteristics AC, DC

Leakage.

Table 6:

SLIC MODE

C/I

(7)

C/I

(6)

C/I CR1 CR1(*) CR1(*)

(5)

(7)

(3)

(2)

2. SLIC Kit block testing.

3. Signal Path Behavior

Every test is set by internal registers, which are

written through GCI data down Monitor.

RING

1

0

X

1/0 1/0

Reduced Power

Ring

X

Test results are typically digitalized, codified and

dropped in the first PCM channel (byte B1) of GCI

interface. For four go/nogo tests (Analog Loop-

back, Ring Generator, TTX Generator and TTX

filter) the result of the test is also written in one bit

of CR5 register that is readable through Monitor.

Test functions are carried out with SLIC Kit in a

mode set automatically by COFISLIC. For detailed

explanation about tests see chapter 6.

(*) CR1.3 has to be equal to CR1.2 : 0 or 1

If unbalanced ringing is requested, SLIC can sup-

port also external ringing injection configuration,

providing both logic command for relay driver and

ringing detection circuitry.

4.3.3.1 - Ring Generation

When the ringing function is selected, a low level

ringing signal (1.5Vrms typ.) is generated inside

the STLC3040 and provided on the VOUT pin.

This signal is then amplified and injected in bal-

anced mode into the line through the HV

(L3000N, L3000S, STLC3170), with superim-

posed DC voltage of 24V typical. Both ringing fre-

quency and amplitude are software programma-

ble.

4.4.2 - Loop Backs

LOOP1 and LOOP2 bits of CR4 register set up

some internal loop backs. This feature is typically

used for COFISLIC tests (see fig. 3).

Any Loopback is enabled by CR1.5 bit. Loopback

type is selected by register CR4.

There are three types of loopback.

The first and the last ring cycles are synchronized

by the STLC3040 so that the ringing signal al-

ways starts and stops with zero phase.

In Ring mode the Off Hook indication is asserted

whenever during two consecutive ring periods ( or

an equivalent time in pause) the mean value of

the IT current exceedes the programmed thresh-

old. After the persistance time the Off Hook is

Loopback 1 (CR4.2 = 0, CR4.1 = 1) simply copies

the downstream B1 to the upstream B1 through

the GCI interface. In this case no Rx signal is sent

to the line. The kit operates as previously set.

Loopback 2 (CR4.2 = 1, CR4.1 = 0) sets Kit SLIC

in Active mode. It copies the output of DSD (Digi-

tal Sigma Delta converter) to the input of the DEC

9/49

STLC3040

block, as shown in fig. 3. Rx signal goes on to the

line. Please note that this loopback function cuts

off the Tx channel connection to the line.

4.5.1.3 Reset bit RST (SOP command bit 4)

If RST bit is programmed to 1 COFISLIC is reset.

SOP register is set by GCI down stream channel.

All other functionalities are those of Active mode.

Until the end of the current command processing,

the GCI is kept active.

Loopback 3 (CR4.2 = 1, CR4.1 = 1) sets Kit SLIC

in Active mode. Rx signal is prevented to go the

line. Tx path is cut off from the line as well. Output

of ASD is copied to input of AFE port filter. DSP

part can be still exercised via B1. All the function-

alities are those of active mode.

4.5.1.4 - CLK fail Reset

Clock fail triggers a reset routine of the DSP

which lasts, until the first good frame that follows

the failed ones.

In active mode during the Reset routine, the voice

channel of "Data up" (Du, pin 6) is forced IDLE

dependent on the selected codification law.

4.4.3 - Test Tones Generation

In Active mode STL3040 can generate either

1kHz or 800Hz frequencies towards the 2-wire

line. The two tones can also be enabled at the

same time.

As far as "Data down" (DD, pin 5) is concerned,

the voice channel does not reach the Vout during

this phase.

TON bit of CR1 register enables the 1 kHz test

tone generator. 800Hz is enabled by CR5[3.0] =

4h.

800Hz amplitude is programmable through the

same register (CR10) used to set TTX amplitude.

1kHz level is fixed at PCM full scale and can be

modified changing Rx channel gain.

Z sinthesys is partially performed, the DSP

branch is not active while the analog loop is kept

active.

Coefficients and CR registers’ contents do not

change because of this partial reset, GCI state as

well. Metering pulse injection signaling is not af-

fected too. Ring generation and ring trip detection

are not influenced too.

4.5 COFISLIC Reset

Any reset to COFISLIC sets SLIC kit in External

Indication. COFISLIC is set in Power denial.

There are four different reset sources:

4.5.2. Start-up State

During reset the device is in Power- Denial Mode.

After Reset, COFISLIC is automatically switched

to its basic start-up state in which it uses internal

default values for all filters and settings (AC and

DC).

Power-On Reset,

Reset pin MR (pin 36),

Reset bit (SOP command bit 4).

During Reset, output pins are set as follows:

Programmed coefficients of filters are not reset.

Bit 0 of CR6 register, FIXC, is set to 1, this means

that fixed values are used after a Reset until FIXC

is set to 0.

Even if FIXC = 1, both checksum and reading of

filter coefficients are carried out on formerly pro-

grammed coefficient set.

DU

C1

(pin 6)

High impedance

V^hv

(pin 9)

C2

(pin 10)

(pin 28)

( pin 39)

V^hv

PDO

O1

High impedance

Low Level

Table 7: Fixed Filter Coefficients

Additionally a Reset of the DSP part of the

COFISLIC is triggered by CLK fail detection (see

also page 17).

Filter

Coefficients (h)

KA, KD 0E00

Z

X

019C, 24A0, 1600

149A, 0521, 3F40,3EF2

4.5.1.1 Power On Reset

When voltage at VDD pin crosses over an internal

fixed threshold (typ. 2.5V) COFISLIC is reset.

R

1879, 39E0, 00B4,0006

GTX

GRX

B

FF

60

4.5.1.2 Reset Pin MR

If an high level is applied to pin 36 (MR) the

COFISLIC is reset.

MR pin has built-in filter to reduce spike sensitiv-

ity. Spikes smaller than 90ns are neglected.

0, 0, 0, 0050, 0680, 06D0, 0, 3C80

SLIC is switched to operating mode carried by

GCI Command Indicate at least two frames after

reset. SLIC status and Filter configuration can be

changed by SOP and COP commands.

Therefore at MR pin a high level is surely recog-

nised as a Reset if it is present for at least 2 s.

After reset the device is internally set as follows:

- configuration registers are set to their default

µ

10/49

STLC3040

values (see Chapter 4-8 Configuration Regis-

ter)

Check Configuration-registers reset-value for

more detailed information.

- RST bit (SOP command bit 4) is set to 1 to in-

dicate that a reset has occured

- GCI interface is reset. After software Reset its

former state is kept. On-going GCI communi-

cation is stopped

4.6 GCI Backplane Interface

GCI is a standard serial interface for interconnec-

tion of SLIC kit to the line card backplane.

The digital interface is used to transfer status in-

formation to and from the SLIC as well as to

transfer filter coefficients for the DSP.

With this approach an analog Line Card could be

replaced by an ISDN one and viceversa without

need to change the interface to the linecard con-

troller.

- DU is in high impedance state

- FIXC = 1 (CR6 Register) Fixed Coefficients

are selected

– DC characteristics of SLIC-Kit

- External Indication

- Normal Battery

As far as physical level is concerned this standard

consists of four wires:

- Serial Transmitted data to the backplane: DU

- Serial Received data from the backplane: DD

- 8KHz Frame Synchronization: FSC

- Test Disabled

- Persistence for Off-Hook and I1: 10ms

- Persistence for Ground Key: 20ms

- Ring Trip threshold = 4.2mA

- Ilim = 22mA in active mode

- Ilim = 7.7mA in Stand-By mode

- Master Data Clock (2048KHz or 4096KHz): DCL

The frame is divided into eight time-slots which

contains four bytes each. Bit rate in both direc-

tions is 2048Kbit/sec and it’s not affected by clock

frequency. This can be chosen setting SEL24 pin.

Eight GCI time slots are selectable via three pins

TS2-TS0 (see Table 8).

- Off-Hook detection threshold in active mode =

10mA

For every time slot the first bit, received or trans-

mitted, is the Most Significant one, according to

timing diagram shown in fig. 7.

Information is clocked out on the rising edge of

data clock and it is latched in on the falling edge

of DCL signal.

Frame Synchronization FSC is a 8KHz signal and

its rising edge gives the time reference of the first

bit in the first GCI (input or output) channel and

resets the slot counter at the next falling edge of

the clock every frame.

- Off-Hook detection threshold in Stand-By

mode = 7.7mA

- Feeding Resistance in either Active or Stand-

By mode = 2 (50 + Rp) (fuse impedance

value is not included)

- Ring: Internal

- Ring Frequency = 25Hz

- Ring Voltage = 65Vrms

- Line Voltage Drop = 28.2V

- External Indication Voltage Threshold for Off-

Hook detection = 9.0V

- A-law is programmed

Four bytes of any GCI time slot are:

- B1 channel for PCM data,

- B2 channel not used,

- M (Monitor) channel used to write and monitor

COFISLIC internal registers,

- C/I (Command/Indication) channel used to set

the Operating Mode.

AC characteristics of SLIC-Kit

- Metering with Teletax

- Line Impedance: (Synthetized Impedance + 2

Ω

Rp) = 700 + 2Rp

8bits

B1

8bits

B2

8bits

MONITOR

Byte 3

6bits

C/I

1bit

A

1bit

E

Ω

- Balance Impedance: 910 / / 62nF

- Tx Gain: 0dBr

- Rx Gain: -7dBr

Byte 1 Byte 2

Byte 4

- Teletax Voltage onto line V_TTX= 10Vrms

- Teletax Frequency = 16kHz

- Battery Reversal: Hard

A single GCI channel has 256kbit/s data rate.

Exchange Protocol

Further after the reset

- I/O pins are set as inputs

STLC3040 validates a received byte if it is detected

identical two consecutive times. (see figg. and 7and 8)

- PD bit of CR1 is reset (means STLC3040 in

Power-Denial mode).

- All bits of Signalling Register are masked

- Data Upstream C/I byte is reset to 0

The exchange protocol is identical for both direc-

tions. The sender uses the E bit to indicate that it

is sending a Monitor byte while the receiver uses

A bit to acknowledge the received byte. When no

11/49

STLC3040

Table 8: GCI Time Slot assignment.

SEL24

TS2

TS1

TS0

GCI operating mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

time slot 0:DCL = 2048kHz

time slot 1:DCL = 2048kHz

time slot 2:DCL = 2048kHz

time slot 3:DCL = 2048kHz

time slot 4:DCL = 2048kHz

time slot 5:DCL = 2048kHz

time slot 6:DCL = 2048kHz

time slot 7:DCL = 2048kHz

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

time slot 0:DCL = 4096kHz

time slot 1:DCL = 4096kHz

time slot 2:DCL = 4096kHz

time slot 3:DCL = 4096kHz

time slot 4:DCL = 4096kHz

time slot 5:DCL = 4096kHz

time slot 6:DCL = 4096kHz

time slot 7:DCL = 4096kHz

Figure 7.

GCI Interface Timing (DCL = 2048KHz, SEL24 = 0)

125µs

FSC

DCL

2048KHz

TS0

TS1

TS2

TS3

TS4

TS5

TS6

TS7

DD

DU

TS0

Detail C

FSC

DCL

DD/DU

Bit 0

Bit n

Bitn - 1

D95TL210A

12/49

STLC3040

Figure 7. (continued)

GCI Interface Timing for 8 voice channels (per 8 KHz frame)

125µs

FSC

DCL

4096KHz

TS0

TS1

TS2

TS3

TS4

TS5

TS6

TS7

DD

DU

TS2

TS3

Detail A

DD

Voice Channel

don't care

Monitor Channel C/I Channel A E

DU

High Impedance Monitor Channel C/I Channel A E

GCI Interface Timing (DCL = 4096KHz, SEL24 = 1, per 8 KHz frame)

125µs

FSC

DCL

4096KHz

TS0

TS1

TS2

TS3

TS4

TS5

TS6

TS7

DD

DU

TS0

Detail B

FSC

DCL

DD/DU

Bit 0

Bit n

Bit n-1

D95TL209A

13/49

STLC3040

message is transferred, E bit and A bit are forced

to inactive state (high = 5V).

the B1 channel on DD pin and outputs PCM bytes

on DU pin.

A transmission is started by the sender (Transmit

section of the Monitor channel protocol handler)

by putting the E bit from inactive to active state

(low = 0V) and by sending the first byte on Moni-

tor channel in the same frame. Transmission of a

message is allowed only if A bit, sent from the re-

ceiver, has been set inactive for at least one con-

secutive frame. When the receiver is ready, it vali-

dates the incoming byte when received identical

in two consecutive frames. Then, the receiver

sets A bit from the inactive to the active state

(preacknowledgement) and maintain active at

least in the following frame (acknowledgement).

4.6.1.2 Linear codification

STLC3040 allows Linear codification simply set-

ting two bits of CR12 register.

COMTX (bit 0) enables the linear code in trans-

mission, while COMRX (bit 1) enables the linear

code in receive.

STLC3040’s linear code consists of 16 bits which

means a range from (-2¹⁵) to (2¹⁵-1) Linear Code

is housed in B1 and B2 channels, B1 is the least

significant byte end B2 is the most significant

byte.

If validation is not possible (two last bytes re-

ceived are not identical) the receiver aborts the

message by setting the A bit active for only a sin-

gle frame.The second byte can be transmitted by

the sender putting the E bit from the active to the

inactive state and sending the second byte on the

Monitor channel in the same frame . The E bit is

set inactive for only one frame. If it remains inac-

tive more than one frame, it means an end of

message. The second byte may be transmitted

only after receiving of the pre-acknowledgement

of the previous byte . Each byte has to be trans-

mitted at least in two consecutive frames.

15 bits are dedicated to the module while the

most significant bit is the sign bit.

If bit 15 (sign bit) = 0 bit 14.....bit 0 represent the

module.

If bit 15 = 1 module is got by 2-complementing bit

14 ...... bit 0.

4.6.2 C/I Channel

Command/Indicate byte is a 6 bits wide command

full duplex transmission.

Internal C/I registers will be loaded if downstream

command is stable for two frames.

The receiver validates the current received byte

as for the first one and then set the A bit in the

next two frames first from the active state to the

inactive state (pre-acknowledgement) and back to

the active (acknowledgement). If the receiver can-

not validate the received current byte (two bytes

received not identical)it pre-acknowledges nor-

mally but lets the A bit in the inactive state in the

next frame which indicates an abort request . If a

message sent by the COFISLIC is aborted, the

COFISLIC will send again the complete message

until receiving of an acknowledgement . A mes-

sage received by the COFISLIC can be acknow-

ledged or aborted with flow Control.

The most significant bit (MSB) of Monitor byte is

sent first on the Monitor channel. E & A bits are

active low and inactive state on DU is 5 V. When

no byte is transmitted, Monitor channel time slot

on DU is in the high impedance state.

The GCI interface transmitter will abort after 8

times during which it hasn’t succesfully received

any acknowledge from the device upstream. The

GCI interface receiver will go in abort request

mode after 8 times of unsuccessful attempts to

get 2 identical copies of the data. This means that

after 8 frames of unsuccessful handshake, the

GCI interface transmitter will abort while the re-

ceiver will make a request for abort.

Also upstream Command/Indicate byte lasts for at

least two consecutive 8KHz frames. Com-

mand/Indicate is mainly used to set SLIC operat-

ing mode and to monitor subscriber On/Off-Hook

and Ground-Key detection.

Any change of line conditions like On-Off/Hook

and Ground Key is signalled via upstream C/I.

HOOK and GNDK bits always reflect line condi-

tions even if corresponding bits of Signalling Reg-

ister are masked by CR12 register. Bit 5 of up-

stream Command/Indicate says that at least one

of Signalling Register six most significant bits has

changed its logical value.

Bit 5 of upstream Command/Indicate does not

change if related bits of Signalling Register have

been masked by CR12 register.

Input/Output pins (IO1/2,I1,O1) can be set and

monitored by C/I channel too. Note that there is

no address in both directions because there is

one GCI time slot per each COFISLIC.

C/I channel in Downstream direction consists of

six bits as shown below :

BIT7

BIT6

BIT5

TIM

BIT4

IO1

BIT3

IO2

BIT2

O1

RING

CONV

Basically the first 3 Most significant Bits of C/I

downstrean operate as follows. For a complete

description please refer to Table 13.

4.6.1 B1/B2 Channels

4.6.1.1 PCM codifications

GCI interface extracts receiving PCM data from

14/49

STLC3040

Figure 8: GCI Monitor Channel messaging examples.

X

M1

M2

X

M

E

A

1st byte

(M1)

2nd byte

(M2)

3rd byte??

(X)

EOM

pre-ack

(M2)

ack

pre-ack??

(X)

Ready for

a new message

Ready

for a message

pre-ack

(M1)

ack

(M2)

(M1)

TWO BYTES MESSAGE - NORMAL TRANSMISSION

X

M1

M2

X

M1

M2

X

M

E

A

1st byte

(M1)

1st byte

(M1)

2nd byte

(M2)

EOM

(or abort ack)

3rd byte??

(X)

Ready for

a message

Ready for

retransmission

pre-ack

(M1)

ack

(M1)

pre-ack

(M2)

abort

(M2)

pre-ack

(M1)

TWO BYTES MESSAGE ABORTED ON THE SECOND AND RETRANSMITTED

M1 = start Byte

E & A BITS TIMING

RING = Sets COFISLIC into ringing state.

= 0 COFISLIC is not in ringing state.

= 1 COFISLIC is in ringing state.

IO1, IO2 define the value for the programmable

Input/Output pins (7, 8) if programmed as output

pins by CR2 register.

CONV = Sets COFISLIC into power up state.

= 0 COFISLIC is in a power down state.

= 1 COFISLIC in power up state.

TIM = Timing bit to control the timing of ringing

and meterpulses.

IO1 = 0 The related pin 7 at the digital interface

of the COFISLIC is set to a logic 0

= 1 The related pin 7 at the digital interface

of the COFISLIC is set to a logic 1

IO2 = 0 The related pin 8 at the digital interface

of the COFISLIC is set to a logic 0

= 1 The related pin 8 at the digital interface

of the COFISLIC is set to a logic 1

= 0 COFISLIC is in ringing pause

or no meterpulse is on.

= 1 COFISLIC is in ringing

or output of a meterpulse is running.

O1 sets value for fixed output pin 39

15/49

STLC3040

channel transfers: SOP, COP, TOP.

= 0 The related pin 39 at the digital interface

of the COFISLIC is set to a logic 0

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

= 1 The related pin 39 at the digital interface

of the COFISLIC is set to a logic 1

X

R/W

X

B3

B2

X

R/W = 0

= 1

Write Operation

Read Operation

C/I channel in Upstream direction is herebelow

described:

B3

0

B2

1

BIT7

BIT6

BIT5

BIT4

IO1

BIT3

IO2

BIT2

I1

SOP command

TOP command

COP command

HOOK GNDK SLCX

1

X

0

HOOK indicates loop condition:

= 0 Subscriber is On-Hook

= 1 Subscriber is Off-Hook

GNDK indicates Ground Key detection:

= 0 No Detected Longitudinal Current

= 1 Detected Longitudinal Current

For SOP, COP, TOP commands the Start Byte is

81 in DU directions.

SOP commands set and monitor COFISLIC

status.

TOP commands read Signalling register and co-

efficient checksum.

COP commands set and read filters coefficient.

SOP and COP can be either write or read com-

mands, while TOP is used only for reading.

A write command (SOP and COP) can be fol-

lowed by up to 14 bytes. An answer to SOP,

COP, TOP commands consists of maximum 16

bytes. First byte is always the start byte (81h).

SLCX is the summary output of the signalling reg-

ister (See TOP command)

= 0 No unmasked bit in signalling register has

toggled

= 1 An unmasked bit in signalling register, has

toggled, it is reset only if SR register is read.

Registers from CR1 to CR12 are accessed by

SOP command both in reading and writing. TOP

command is used to read the Signalling Register

and the Coefficient Checksum. The RAM, where

filters coefficient are stored, is accessed by COP

commands.

A fourth command of the Monitor Channel is the

so called Channel Identification Command (CIC).

This command will be run if the COFISLIC re-

ceives the following code on the Monitor Channel

for at least two frames:

IO1,IO2 give logical state of programmable In-

put/Output pins (7, 8)

IO1 = 0 Corresponding pin 7 at digital

interface of COFISLIC is receiving

a logic 0

= 1 Corresponding pin 7 at digital

interface of COFISLIC is receiving

a logic 1

IO2 = 0 Corresponding pin 8 at digital

interface of the COFISLIC is receiving

a logic 0

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

= 1 Corresponding pin 8 at digital

interface of COFISLIC is receiving

a logic 1

1

0

Upon CIC command is received COFISLIC will

place two bytes on DU line, each byte is repeated

at least twice.

If as per CR1 register IO1 and IO2 are pro-

grammed as outputs, data up command indicate,

IO1 and IO2 are set to 1

I1 gives logical state of fixed input pin 38.

= 0 pin 38 is receiving a logic 0.

BIT7 BIT6 BIT5 BIT4 BIT3

BIT2

BIT1

BIT0

1

0

CONF(3) CONF(2) CONF(1) CONF(0)

= 1 pin 38 is receiving a logic 1.

This byte replaces usual Start byte. Low nibble

CONF(3)-CONF(0) defines the identification code

according to the logic values of three input pins

IDH (pin 35), IDL and IDM (pin 31 and 32).

4.7.1 Monitor-Channel (M-channel)

As already mentioned COFISLIC can be pro-

grammed and monitored via GCI Monitor.

Data transfer from and to STLC3040 starts with a

specific byte, called Start Byte:

Herebelow it is the Table of Identification:

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

1

0

X

In downstream a second byte selects one of the

three different kinds of commands which Monitor

16/49

STLC3040

Table 9:

SIGNALLING REGISTER (SR)

SR provides information about loop condition:

Off/OnHook condition, line constant current, line

voltage. It also signals temperature alarm related

to HV SLIC (L3000N, L3000S, STLC3170) and

clock fails (see page 10). The Clock fail indication

is set whenever the number of DCL periods in

one frame (between two-FSC pulses) is different

from the standard one.

Hook and Ground Key state variations toggle the

related bits of SR register and therefore switch

HOOK and GNDK bits of upstream C/I.

Every change of any of the six most significative

bits of SR register is summarized in SLCX bit (bit

5) of upstream Command/Indicate, provided that

these bits are not masked by CR12 register.

Masking acts only on SLCX bit.

IDH

+5V

0V

IDM

-5V

0V

IDL

-5V

0V

Id. Code

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

+5V

-5V

0V

+5V

-5V

0V

+5V

0V

-5V

+5V

0V

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

0V

-5V

+5V

0V

HOOK GNDK VB_2 ILIM TEMP CK_FAIL XX

XX

0V

-5V

Reset Value: 00h

0V

-5V

HOOK indicates loop condition (same as in up-

stream C/I):

= 0 Subscriber is On-Hook

= 1 Subscriber is Off-Hook

Data transfer is completed by the next byte:

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

1

0

1

0

GNDK shows a Ground Key detection (same as

in upstream C/I):

= 0 No Detected Longitudinal Current

= 1 Detected Longitudinal Current

4.7.1.1 TOP Command

As above mentioned TOP command allows read-

ing Signalling Register and Coefficient RAM

checksum.

VB_2 half battery voltage across the line is detected

V_OL

(V_LINEcompared to

).

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

2

X

R/W

X

1

LSEL1 LSEL0

This bit is designed to indicate the line DC operat-

ing point only in Stand-By and Active modes, with

no TTX injection

R/W = 0 No Operation

= 1 Read Operation

V_OL

LSEL1

0

LSEL0

0

= 0 if (|V_LINE|<|

= 1 if (|V_LINE|>|

|)

2

V_OL

2

1 byte for signalling register

reading

0

1

1 byte for signalling register and

2 bytes for filter coefficients

checksum reading, low byte is

read first and then high byte.

where: |V_LINE| = |V^TIP- V^RING|

|V_OL| = |V^BAT-V^DROP|

ILIM Current Limit Region

This interrupt is automatically masked in Ringing

Mode

= 0 Resistive Feeding Region

1

0

15 bytes for Line Card

Identification Code reading

In answer to TOP command COFISLIC will place

the Start byte first.

Coefficient checksum is defined by this algorithm:

= 1 Constant Current Feeding Region

X¹⁶X¹⁰X⁷

X

1

TEMP Temperature alarm of HV SLIC (L3000N,

L3000S, STLC3170) which is signalled through

HV (L3000N, L3000S, STLC3170) interface

This algorithm guarantees a fault coverage of:

(1 - 2^-15

)

= 0 Normal Temperature

17/49

STLC3040

command the SOP is started by Start Byte, in

downstream, followed by a byte that sets the SOP

register.

= 1 Temperature Alarm from HV (L3000N,

L3000S, STLC3170)

SOP register:

CK_FAIL Receiving Clock and/or Synchronization

signals failures

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

= 0 no Detected Clock or Sync fails

= 1 Detected Clock or Sync fails

Bits ILIM, TEMP, VB_2 have 7ms persistance

fixed.

X

R/W POL RST

0

1

LSEL1 LSEL0

R/W = 0 Write to Cofislic

= 1 Read Operation

POL = 0 Normal Polarity Feeding

4.7.1.2 COP Command

= 1 Reverse Polarity Feeding

RST = 0 Normal Operation

Every COP command is started by the Start Ad-

dress. A second byte contains the RAM address

related to the programmable filters.

Address is defined by the least significative five

bits except the third one which identifies a COP

command.

= 1 Reset, set the COFISLIC to the basic

setting mode

After a reset, RST is set to 1. RST is toggled to 0

after a SOP read operation with LSEL bits pro-

grammed to 00b.

COP commands consist of maximum 14 bytes

used to set and monitor digital filter coefficients.

If R/W = 0

Write to COFISLIC

No byte is following

COP register:

LSEL1

LSEL0

0

1

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

Two bytes, which write CR1 and

CR2 Registers, follow

X

R/W COD5 COD4 COD3 COD2 COD1 COD0

R/W = 0 Subsequent bytes are written to

COFISLIC

1

0

1

12 bytes, which set CR1,.,CR12

registers, follow

= 1 Subsequent bytes are read from

COFISLIC

Not available

COD2 = 0 Identifies a COP command COD5,

COD4, COD3, COD1, COD0 bits identify filters

address as shown here below (Table 10).

If R/W = 1

LSEL1

0

Read from COFISLIC

LSEL0

0

Replies the SOP * command

received by COFISLIC

For every coefficient, but B filter, with 14bit width

the Least significant Byte is sent first. In the Most

Significant Byte the first two bits must be stuffed

with 0.

0

1

0

1

Replies the SOP * command

received by COFISLIC, followed

by two bytes: CR1, CR2

Registers

For B Filter the 14 bytes are the result of the con-

catenation of the 8 coefficients of 14 bits

Replies the SOP * command

received by COFISLIC, followed

by twelve bytes: CR1, CR2

CR12 Registers

4.7.1.3 SOP Command

Reading and writing of CR and SOP register is

performed via SOP commands. Configuration,

operation and test data can be set and updated

by this command. As for every Monitor channel

Not available

SOP *: during the on going SOP command SOP* is

the previously processed SOP command.

Table 10:

COD5

COD4

COD3

COD1

COD0

ADDRESS

Filter B

Following Bytes

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

14

8

Filter R

Filter X

8

Filter GR

Filter GX

Filter KA, KD

Filter Z

1

2

6

Filters coefficients must be evaluated using a proper ST simulation software.

18/49

STLC3040

XVA OKTON OKTTX OKRNG TMN NOSL IO1 IO2

Reset value: 00h

4.8 Configuration Registers

As already mentioned, Configuration Registers

are set and read by SOP command.

XVA Internal measurement results shown in the

following three bits are or not valid (read only)

CR1 sets SLIC kit operating features and some

test features.

= 0 the following 3 ok-bits are not valid

= 1 the following 3 ok-bits are valid

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

PD N/BB LB

TON HIA

HIB DHP COR

OKTON Test Tone meaurement information (read

only), see test mode 7

Reset value = 00 h.

PD sets the kit either in Stand By or External Indi-

cation/Loop open (for further details please see

table 13 pag. 45)

= 0 Test tone level out of defined range

= 1 Test tone level in defined range

= 0 SLIC kit (STLC3040/HV (L3000N, L3000S,

STLC3170)) in External Indication Mode

= 1 SLIC kit (STLC3040/HV (L3000N, L3000S,

STLC3170)) in Stand By Mode

OKTTX Test teletax metering information (read

only), see Test Mode D and E

= 0 Test teletax metering different from the

defined value

= 1 Test teletax metering equal to the

defined value

N/BB sets COFISLIC Battery Mode

= 0 Normal Battery

OKRNG Test Ring tone information (read only),

see Test Mode C

= 1 Boosted Battery

= 0 Ring tone level out of defined range

= 1 Ring tone level within the defined range.

LB enables Loop Back functions for on chip test

= 0 normal function (no loop back)

= 1 Loop Back as defined in CR4 register

TMN Enables or disables COFISLIC testmodes

(see chapter 6)

= 0 stops the assigned tests (normal mode)

= 1 starts the assigned tests selected by Regis-

ter CR5

TON enables 1KHz test tone generator

= 0 Test Tone Generator Off

= 1 Test Tone Generator On

HIA and HIB set tip and ring status in active and

standby mode

NOSL Defines if the shaping of teletax signal is

switched On or Off

= 0 Teletax shaping is on

Standby

Active

HIA

0

HIB

0

TIP

RING

normal

Hiz

TIP

RING

normal

Hiz

= 1 Hard switch of Teletax signal

normal

0

1

normal

IO1 Selection for programmable I/O pin IO1

= 0 sets pin IO1 as input

= 1 sets pin IO1 as output

negative

1

0

1

Hiz

normal

Hiz

normal

DHP enables High-Pass filter for test purpose

= 0 High Pass filter On

= 1 High Pass filter Off

IO2 Selection for programmable I/O pin IO2

= 0 sets pin IO2 as input

= 1 sets pin IO2 as output

COR cuts off Receive Path for test purpose

= 0 Receive Path transmission is enabled

= 1 Receive Path is disable

CR3 sets Persistence Check for upstream signal-

ling: Off-Hook and Ground-Key.

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

DUP3 DUP2 DUP1 DUP0 DUB3 DUB2 DUB1 DUB0

CR2 enables or disables Test Mode, Teletax Sig-

nal Shaping Mode and sets the I/O pin direction.

The high nibble is only readable and defines test

mode results.

Reset value: A5 h

Persistence Reset value is 10 ms both for Off-

Hook and I1 input pin. 20ms for Ground-Key.

BIT7 BIT6

BIT5

BIT4 BIT3 BIT2 BIT1 BIT0

19/49

STLC3040

Figure 9.

I1

I1 AFTER PERSISTENCE

CHECK ON UPSTREAM

0

N-1ms

Nms

I1

I1 AFTER PERSISTENCE

CHECK ON UPSTREAM

N-1

N

D96TL264

0

(HX) is defined by programmed filter

coefficients (COP command)

R represents R-filter

= 0 R-filter is Off, Related Transfer Function

(HR = 1) is one

= 1 R-filter is On, Related Transfer Function

(HR) is defined by programmed filter

coefficients (COP command)

GX/GR represents GX/GR-filter

= 0 GX/GR-filter is Off, Related Transfer

Function (HGX/GR = 1) is one

= 1 GX/GR-filter is On, Related Transfer

Function (HGX/GR) is defined by

programmed filter coefficients

(COP command)

DUP3-DUP0 Persistence check for signalling up-

stream Off-Hook and I1. New status information

will be transmitted upstream, after it has been sta-

ble for from (N-1) to N millisecond (see fig. 9).

N is programmable in range of 1 to 15 ms in steps

of 1 ms. DUP3-DUP0 = 0000 means no persist-

ence check.

DUB3-DUB0 Persistence check for signalling up-

stream Ground-Key. New status information will

be transmitted upstream, after it has been stable

for N millisecond. N is programmable in range

from 0 to 60 ms in steps of 4 ms. DUB3-DUB0 =

0000 means no persistence check.

CR4 enables internal filters B, Z, X, R, GX/GR. It

also programs the Loop Back and sets the codifi-

µ

cation law: A-law or -law.

LOOP1-LOOP0 select the loop back (see Block

Diagram fig. 3 and paragraph 4.42)

BIT7 BIT6 BIT5 BIT4 BIT3

BIT2

BIT1 BIT0

= 00 No loop-Back

B

Z

X

R

GX/GR LOOP1 LOOP0 A/U

= 01 Loop-Back only GCI interface (LB1 on).

= 10 Loop-Back the digital part (Digital

Sigma-Delta converter is included, LB2 on).

Reset value: F9h

B represents B-filter

= 0 B-filter is Off, Related Transfer Function

is zero (HB = 0)

= 11 Loop-Back the Analog part (Analog

Sigma-Delta converter is included, LB3 on).

= 1 B-filter is On, Related Transfer Function

(HB) is defined by programmed filter

coefficients (COP command)

A/U chooses coding law

µ

= 0 -law coding

= 1 A-law coding

Z represents Z-filter

= 0 Z-filter is Off, Related Transfer Function is

zero (HZ = 0)

CR5 sets ring-trip thresholds and test modes

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

RTV3 RTV2 RTV1 RTV0 TESM3 TESM2 TESM1 TESM0

= 1 Z-filter is On, Related Transfer Function

(HZ) is defined by programmed filter

coefficients (COP command)

Reset value: 60h.

X represents X-filter

RTV3-RTV0 set Ring-Trip Threshold Value. This

value is programmable in the range from 9.6/16

mA to 9.6 mA in steps of 9.6/16 mA.

= 0 X-filter is Off, Related Transfer Function

(HX = 1) is one

= 1 X-filter is On, Related Transfer Function

20/49

STLC3040

threshold in Stand-by mode.

Programmable range is from 0mA to 69.3mA in

steps of 1.1mA.

= 0h corresponds to 9.6/16 mA

= Fh corresponds to 9.6 mA

For further details please see parameters I^RNGGTH

(pag 34)

= 0000 corresponds to 0mA

= 1111 corresponds to 69.3mA

At reset the value will be 7.7mA.

TESM3-TESM0 select the testmode.

PDDIS used for state setting as per table 14 (pag

45)

RTEN enables Ring-trip in test mode TST-IRING

= 0 Ring-trip disabled

= 0h

= 1h

= 2h

= 4h

= 5h

= 7h

= 8h

= 9h

= Ah

= Ch

= Dh

= Eh

= Fh

No-Test

TST-LEAK [CR8.1 = 0, CR5(3:0) = 01h]

TST-LKA [CR8.1 = 0, CR5(3:0) = 02h]

TST-800Hz

= 1 Ring-trip enabled

TST-TONE-CAL

TST-ALB

CR8 sets synthesized feeding resistance, TTX

frequencies. The least significant bit sets the ring-

ing source: internal or external.

DON’T USED

TST-LINE-IMPDC

TST-LINE-IMPAC

TST-IRING

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

RFED2 RFED1 RFED0 TTX12 TTXNO SOREV XRNG TMM

TST-PTTX

Reset Value: 00h

TST-TTXFILT

RFED2-RFED0 Values of the synthesized feeding

resistance‘.

TST-ILIM

Every test will be described in Chapter 6

Ω

DC Synthesis Value = 2 Rp + 2 50

[RFED [2:0] + 1]

TTX12 selects Teletax frequencies

= 0 16KHz teletax

= 1 12KHz teletax

CR6 sets current limitation values and off-hook

threshold in Active mode.

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

ILIM5 ILIM4 ILIM3 ILIM2 ILIM1 ILIM0 ITHR FIXC

TTXNO sets Battery Reversal for metering in-

stead of 16/12KHz pulse

=0 Metering with Teletax pulse

=1 Metering with Battery reversal

SOREV selects hard or soft Battery Reversal

= 0 Hard Battery Reversal

Reset Value: 51h

ILIM5-ILIM0 Set Current Limit in Active mode.

Current Limit is programmable in range of 0mA to

69.3mA in steps of 1.1mA.

= 000000 corresponds to 0mA

= 1 Soft Battery Reversal

= 111111 correspondso to 69.3mA

ITHR Defines Off-Hook threshold value in Active

mode

= 0 Threshold at 10mA

= 1 Threshold at 13mA

XRNG selects ringing source: internal or external

= 0 Internal Ring

= 1 Ring signal from EXT pin

TMM enables sign modulation at 1kHz square

wave of measurement carried out during test mode

Loop indication is set if a loop current greater

than 10mA or 13mA is detected.

FIXC, COFISLIC uses either fixed coefficients or

programmed ones.

= 0 No Modulation

= 1 Modulation enabled

CR9 programs Ring frequency and amplitude.

= 0 Programmed coefficients used

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

RVR RNGF2 RNGF1 RNGF0 RNGV3 RNGV2 RNGV1 RNGV0

= 1 Fixed coefficients used (see paragraph

4.5.2)

CR7 sets current-limit value and Off-Hook thresh-

old in Stand-By mode.

Reset Value: 2F h

RVR fixes Ring Voltage Range

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

PDSV5 PDSV4 PDSV3 PDSV2 PDSV1 PDSV0 PDDIS RTEN

= 0 Ring Amplitude = 34.4Vrms + RNGV [3:0] x

2.039Vrms

= 1 Ring Amplitude = 45Vrms + RNGV [3:0] x

2.66Vrms

Reset Value is 65 V^rms

Reset Value: 1Ch

PDSV5-PDSV0 Set Current Limit and Off-hook

21/49

STLC3040

cleared and two things could happen. If the con-

tents of the shadow register differ from the en-

abled SR (meaning there was at least one toggle

of the enabled SR bits between the time when the

interrupt bit is set and the TOP READ command),

then the SR byte will be latched into the shadow

register while the interrupt bit (SLCX) will remain

cleared (low) for 2 frames and then will be set

high. On the other hand, if the contents of the

shadow-register are equal to the enabled SR,

then the interrupt bit remains cleared and will be

set only by the next event. At reset, the shadow

register content mirrors that of SR register. A

mask-bit change causes SR to be latched in the

shadow-Register, nevertheless the SCLX bit is

cleared

RNGF2-RNGF0 select Ring frequency value

= 0h

= 1h

= 2h

= 3h

= 4h

= 5h

= 6h

= 7h

16.6Hz Ringing Frequency

20Hz Ringing Frequency

25Hz Ringing Frequency

50Hz Ringing Frequency

60Hz Ringing Frequency

Ringing Frequency not used

Ring Reset Value is 25 Hz

RNGV3-RNGV0 fix Ring Voltage programmation

step.

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1

BIT0

CR10 sets Teletax Voltage Level.

HOOK GNDK VB_2M ILIM TEMP CLKF COMRX COMTX

Reset Value: FFh

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

TTXV7 TTXV6 TTXV5 TTXV4 TTXV3 TTXV2 TTXV1 TTXV0

HOOK Mask bit for Hook information in the sig-

nalling register

Reset Value: FF h

TTXV7-TTXV0

Teletax Amplitude [V] = TTXV (7:0) 10V_rms/255.

A dc drop (TTXV [7:3] 15mV 40)is applied as

indicated in electric specification section.

= 1 No influence on SLCX bit (Upstream C/I.5)

= 0 Each change of the HOOK bit sets SLCX bit

(Upstream C/I.5)

GNDK Mask bit for Ground Key information in the

signalling register

= 1 No influence on SLCX bit (Upstream C/I.5)

= 0 Each change of the GNDK bit sets SLCX bit

(Upstream C/I.5)

CR11 Bit (7:4) set External-indication threshold

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

ETHR3 ETHR2 ETHR1 ETHR0 STRES3 TXONEDHPRX

X

VB_2M Mask bit for half-battery information in the

signalling register

= 1 No influence on SLCX bit (Upstream C/I.5)

R^ESETvalue = 10 h

ETHR [3:0] set the External-indication threshold:

for ETHR[3:0] = 0h, threshold = 0V;

for ETHR[3:0] > 0h:

= 0 Each change of the VB_2 bit sets SLCX bit

(Upstream C/I.5)

ILIM Mask bit for current limit information in the

signalling register

Threshold = 8V + ETHR [3 : 0] 1V

TXONE and STRES3 must be always pro-

grammed to 0

DHPRX = 1 disable the Rx high pass filter

= 1 No influence on SLCX bit (Upstream C/I.5)

= 0 Each change of current limit bit sets

SLCX bit (Upstream C/I.5)

TEMP Mask bit for temperature information in the

signalling register

= 1 No influence on SLCX bit (Upstream C/I.5)

= 0 Each change of the temperature bit sets

SLCX bit (Upstream C/I.5)

CLKF Mask bit for clock-fail information in the sig-

nalling register

CR12 can mask the effect on SLCX of the six most

significant bits of Signalling Register. If a bit is

masked it will not affect the SLCX bit of upstream

C/I channel. The unmasked SR bits are used to

trigger an event-detect circuit and will latch the SR

signals into a shadow register whenever an event

occurs. An event is defined as a toggling of one or

more of the enabled SR bits. Once the interrupt is

set and the shadow registers are latched, any fur-

ther event does not influence the interrupt or the

shadow registers.

= 1 No influence on SLCX bit (Upstream C/I.5)

= 0 Each change of the clock-fail bit sets SLCX

bit (Upstream C/I.5)

With the SR TOP READ command, the byte repre-

senting the SR will be sent out to the DU depend-

ing on the values of the MASK bits. For unmasked

SR bit its shadow register bit is sent out; otherwise

the value of SR bit is sent out. At the end of the

readout of the above byte, the interrupt bit is

COMRX = 0 Linear code in Rx is enabled

= 1 PCM in Rx is Enabled

COMTX = 0 Linear code Tx is enabled

= 1 PCM in Tx is enabled

22/49

STLC3040

4.9. COFSLIC PROGRAMMING PROCEDURE

SOP - Write Commands

DD

Address

SOP-Write 0 Byte

7

1

6

0

5

0

4

0

3

0

2

0

1

0

1

0

Bit

7

6

5

4

3

2

1

0

DU

Idle

DD

Address

SOP-Write 2 Bytes

7

1

6

0

5

0

4

0

3

0

2

0

1

0

1

Idle

CR1

CR2

Data

DD

Address

SOP-Write 12 Bytes

7

1

6

0

5

0

4

0

3

0

2

0

1

0

1

0

1

0

Bit

7

6

5

4

3

2

1

0

DU

Idle

:

CR1

:

Data

:

CR12

Data

Idle

COP - Write Commands

DD

7

1

X

6

0

5

0

4

3

0

2

0

1

0

1

0

1

Bit

7

6

5

4

3

2

1

0

DU

Address

0

Idle

:

COP-Write 8 Bytes

Coeff. 1

:

Data

:

Coeff. 8

Data

Idle

23/49

STLC3040

SOP - Read Commands

DD

7

1

X

6

0

1

5

0

X

4

0

X

3

0

2

0

1

0

1

0

Bit

7

6

5

0

4

0

3

Idle

0

2

1

0

DU

Address

SOP-Read

Idle

1

0

1

0

1

Address

SOPK-1

Idle

0

(*)

LSEL1 LSEL0

Idle

DD

7

1

X

6

0

1

5

0

X

4

0

3

0

2

0

1

0

1

Bit

7

1

6

0

5

0

4

0

3

Idle

0

2

1

0

DU

Address

SOP-Read

X

Idle

0

1

0

1

Address

SOPK-1

Idle

0

(*)

LSEL1 LSEL0

Idle

Data

CR1

CR2

DD

7

1

6

0

1

5

0

4

0

3

0

2

0

1

0

1

0

1

0

Bit

7

1

6

0

5

0

4

0

3

Idle

0

2

1

0

DU

Address

SOP-Read 12 Bytes

Idle

0

1

0

1

Address

SOPK-1

0

(*)

LSEL1 LSEL0

Idle

:

Data

:

CR1

:

Idle

Data

CR12

(*) LSEL1, LSEL0 of previous SOP processed command, SOPK-1 is former SOP command

24/49

STLC3040


型号：	STLC3040-TR
厂家：	ST
描述：	STLC3040-TR PC 电信信息通信管理电信集成电路
文件：	总49页 (文件大小：442K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STLC3040-TR [STMICROELECTRONICS]

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