MN3646 [PANASONIC]
CCD Sensor, 0.80-1.20V, Rectangular, Through Hole Mount, DIP-22;
| 型号： | MN3646 |
| 厂家： | 
PANASONIC |
| 描述： | CCD Sensor, 0.80-1.20V, Rectangular, Through Hole Mount, DIP-22 CD 传感器 换能器 |
| 文件： | 总6页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CCD Linear Image Sensor
MN3646
2880-Bit High-Responsivity CCD Linear Image Sensor
■ Overview
■ Pin Assignments
The MN3646 is a 2880-pixel high sensitivity CCD linear image
sensor combining photo-sites using low dark output floating
photodiodes and CCD analog shift registers for read out. It provides
large output at a high S/N ratio for visible light inputs over a wide
range of wavelength.
1
OS
DS
VSSD
RS
BT
NC
NC
NC
ø1
1
2
3
4
5
6
7
8
9
22
21
20
19
18
17
16
15
14
13
12
VSSA
VDD
VOD
RD
NC
NC
NC
NC
NC
ø 2
■ Features
• 2880 floating photodiodes and n-channel buried type CCD shift
registers for read out are integrated in a single chip.
• Operates on +5V single power supply and can driven by 5V CMOS
logic.
• Use of photodiodes with a new structure has made the dark output
voltage very low.
øSG
NC
10
11
NC
• Has a smooth spectral response that is close to the sensitivity of the
human eye in the entire visible region.
2880
• Large signal output of typically 1200mV at saturation can be
obtained.
(Top View)
• Since a compensation output pin (DS) is provided in addition to the
signal output pin (OS), it is possible to obtain a signal with a high
S/N ratio by carrying out differential amplification of the OS and
DS outputs.
C20
WDIP022-G-0470
■ Application
• Barcode readers
• Measurement of position and dimensions of
objects.
■ Block Diagram
ø 2
13
V
VDD
21
RD
19
V
20
SSA
OD
22
RD power
supply voltage
rise circuit
2 1 2 2 1 2 1 21 2 1 2 1
1 2 1 2 1 21 2 1 2 1
1
2
2
1
1 2 1 1 2 1 2 1 2 1 2 1 2
2 1 2 1 2 1 2 1 2 1 2
Reset pulse
voltage
rise circuit
B1 to B13 : Black reference pixels
D1 to D 6 : Dummy invalid pixels
3
1
2
4
5
9
10
OS DS
V
SSD
RS BT
ø1 ø SG
MN3646
CCD Linear Image Sensor
■ Absolute Maximum Ratings (Ta=25˚C, VSSA=VSSD=0V)
Parameter
Symbol
VDD
VOD
VI
Rating
Unit
V
V
– 0.3 to +8.0
– 0.3 to +8.0
– 0.3 to +8.0
– 0.3 to +8.0
–20 to + 60
–40 to +100
Power supply voltage
Input pin voltage
Output pin voltage
V
VO
V
Topr
Tstg
Operating temperature range
Storage temperature range
˚C
˚C
■ Operating Conditions
Voltage conditions (Ta=–20 to +60˚C, VSSA=VSSD=0V)
•
Parameter
Symbol
VDD
Condition
min
typ
5.0
5.0
5.0
0.2
5.0
0.2
5.0
0.2
5.0
0.2
max
Unit
V
Internal digital circuit power supply voltage
CCD output circuit power supply voltage
CCD shift register clock High level
CCD shift register clock Low level
Shift gate clock High level
4.5
4.5
4.5
0
5.5
5.5
5.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
VDD=VOD
VOD
Vø H
Vø L
VSH
VSL
VRH
VRL
VBH
VBL
V
V
V
4.5
0
V
V
Shift gate clock Low level
V
Reset gate clock High level
Reset gate clock Low level
Boot gate clock High level
4.5
0
V
V
4.5
0
V
Boot gate clock Low level
Timing conditions (Ta=–20 to +60˚C)
•
Parameter
Symbol
fC
Condition
min
40
80
0
typ
250
500
60
max
Unit
kHz
kHz
ns
fC =1/2T, fR=1/T=data rate
See timing diagram. Note 1
1000
Shift register clock frequency
Reset clock frequency
Shift register clock rise time
Shift regisster clock fall time
Shift clock rise time
fR
2000
100
tø r
tø f
tSr
See timing diagram
0
60
100
ns
0
50
100
ns
Shift clock fall time
0
50
100
ns
tSf
See timing diagram
Note 2
tSs
Shift clock set up time
Shift clock pulse width
Shift clock hold time
Reset clock rise time
Reset clock fall time
0
100
1000
ns
tSw
tSh
µs
100
0
200
1.0
20
500
10
50
50
—
—
—
50
50
—
—
—
µs
tRr
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
tRf
0
20
tRs
Reset clock set up time
Reset clock pulse width
Reset clock hold time
Boost clock rise time
Boost clock fall time
Boosst clock set up time
Reseet active period
See timing diagram
50
60
20
0
100
250
—
tRw
tRh
tBr
tBf
tBs
20
0
20
See timing diagram
Note 3
20
100
200
30
tRBw
tBh
—
Boost clock hold time
—
Note 1) Since the dark output of the CCD shift register region increases and the dynamic range decreases as the shift register clock
frequency fC becomes lower, use the device in the range of fC at which the required dynamic range can be obtained.
Note 2) Care should be taken because making the shift clock pulse width tSw smaller has the tendency to increase the lag (= the
image left over from the signal scanned during the previous period).
Note 3) A step will be present in the reset pulse waveform if the boost clock set up time tBs becomes too long.
MN3646
CCD Linear Image Sensor
■ Electrical Characteristics
Clock input capacitance
•
Parameter
Symbol
Cø
Condition
min
—
typ
550
150
15
max
Unit
pF
Shift register clock input capacitance
Shift gate clock input capacitance
Reset gate clock input capacitance
Boost gate clock input capacitance
650
200
30
—
pF
CS
CR
CB
=1MHz
f
—
pF
20
30
pF
—
DC characteristics (Ta=–20 to +60˚C, VSSA=VSSD=0V)
•
Parameter
Symbol
IDD
Condition
min
—
typ
0.5
1.5
max
1.0
Unit
mA
mA
VDD =VOD =+5V
fR=500kHz
Digital power supply current
Analog power supply current
IOD
—
3.0
■ Optical Characteristics
<Inspection conditions>
• Ta=25˚C, VDD=VOD=5V, VøH=VSH=VRH=VBH=5V (pulse), fC=250kHz, fR=500kHz, Tint (accumulation time)=10ms
• Light source: Red-color LED (Peak wavelength: 660nm±10nm)
• Optical system: A slit with an aperture dimensions of 20mm × 20mm is used at a distance of 200mm from the sensor (equivalent
to F=10).
• Load resistance = 100k Ohms
• These specifications apply to the 2880 valid pixels excluding the dummy pixels D1 to D6.
Parameter
Responsivity
Symbol
R
Condition
min
170
—
typ
210
—
max
250
10
Unit
V/lx· s
%
PRNU
O/E
Photo response non-uniformity
Odd/even bit non-uniformity
Saturation output voltage
Saturation exposure
Note 1
Note 2
Note 3
Note 3
%
—
—
3
mV
mlx·s
mV
mV
800
3.2
—
1200
5.7
0.2
0.1
—
VSAT
SE
—
—
VDRK
DSNU
STTE
ZO
Dark signal output voltage
Dark signal output non-uniformity
Shift register total transfer efficiency
Output impedance
Dark condition, see Note 4
Dark condition, see Note 4
1.0
2.0
—
—
92
%
—
1.0
6000
2.5
2.5
30
1.5
—
kΩ
DR
Dynamic range
Note 5
Note 6
Note 6
Note 6
—
VOS
Signal output pin DC level
Compensation output pin DC level
Signal and compensation output pin DC level difference
3.5
3.5
100
1.5
1.5
—
V
V
VDS
OS – VDS
V
|
|
mV
Note 1) The photo response non-uniformity (PRNU) is defined by the following equation, where Xave is the average output voltage
of the 2880 valid pixels and ∆x is the absolute value of the difference between Xave and the voltage of the maximum (or
minimum) output pixel, when the surface of the photo-sites is illuminated with light having a uniform distribution over the
entire surface.
x
Xave
×100 (%)
PRNU=
The incident light intensity shall be 50% of the standard saturation light intensity.
Note 2) The odd/even bit non-uniformity (O/E) is defined by the following equation, where Xave is the average output voltage of
the 2880 valid pixels and Xn is the output voltage of the ‘n’th pixel, when the surface of the photo-sites is illuminated with
light having a uniform distribution over the entire surface.
2879
∑ | Xn–Xn+1 |
n=1
O/E=
×100 (%)
2879 × Xave
In other words, this is the value obtained by dividing the average of the output difference between the odd and even pixels
by the average output voltage of all the valid pixels. The incident light intensity shall be 50% of the standard saturation
light intensity.
MN3646
CCD Linear Image Sensor
■ Optical Characteristics (continued)
Note 3) The Saturation output voltage (VSAT) is defined as the output voltage at the point when the linearity of the photoelectric
characteristics cannot be maintained as the incident light intensity is increased. (The light intensity of exposure at this
point is called the saturation exposure.)
Note 4) The dark signal output voltage (VDRK) is defined as the average output voltage of the 2880 pixels in the dark condition at
Ta=25˚C and Tint=10ms. Normally, the dark output voltage doubles for every 8 to 10˚C rise in Ta, and is proportional to
Tint.
The dark signal output non-uniformity (DSNU) is defined as the difference between the maximum output voltage among
all the valid pixels and VDRK in the dark condition at Ta=25˚C and Tint=10ms.
V
DRK
DSNU
Note 5) The dynamic range is defined by the following equation.
VSAT
DR=
VDRK
Since the dark signal voltage is proportional to the accumulation time, the dynamic range becomes wider when the
accumulation time is shorter.
Note 6) The signal output pin DC level (VOS) and the compensation output pin DC level (VDS) are the voltage values shown in the
following figure.
Reset feed
through level
DS
OS
VDS
VOS
VSS
VSS
■ Pin Descriptions
Pin No.
1
Symbol
Pin name
Condition
OS
DS
VSSD
RS
Signal output
2
Compensation output
Digital ground
3
Ground pin for the internal digital circuit.
4
Reset clock
5
BT
NC
NC
NC
ø1
Boost clock
6
Non connection
Non connection
Non connection
Transfer clock (Phase 1)
Shift clock
7
8
9
ø
10
11
12
13
14
15
16
17
18
19
20
21
22
SG
NC
NC
ø2
Non connection
Non connection
Transfer clock (Phase 2)
Non connection
Non connection
Non connection
Non connection
Non connection
Reset drain
NC
NC
NC
NC
NC
RD
Apply capacitance of 3,300pF externally.
Ground pin for the internal analog circuit.
V
Analog power supply
Digital power supply
Analog ground
OD
VDD
VSSA
Note 1) It is possible to expect improvement in the S/N ratio by connecting separately the analog power supply pins (VOD, VSSA
)
and the digital power supply pins (VDD, VSSD) respectively to the analog side pattern and the digital side pattern on the
circuit board for driving the CCD.
Note 2) Connect all NC pins externally to VSSA
.
MN3646
CCD Linear Image Sensor
■ Construction of the Image Sensor
The MN3646 can be made up of the three sections of—a) photo
detector region, b) CCD transfer region (shift register), and c)
output region.
transferred to the CCD transfer for each odd and even pixel
at the timing of the shift clock (øSG). The optical signal
electric charge transferred to this analog shift register is
successively transferred out and guided to the output region.
• A buried type CCD that can be driven by a two phase clock
(ø1, ø2) is used for the analog shift register.
a) Photo detector region
• The photoelectric conversion device consists of a 7µm
floating photodiode and a 3µm channel stopper for each
pixel, and 2880 of these devices are linearly arranged side by
side at a pitch of 10µm.
c) Output region
• The signal charge that is transferred to the output region is
sent to the detector where impedance transformation is done
using two source follower stages.
• The photo detector's windows are 10µm × 200µm rectangle
and light incident on areas other than these windows is
optically shut out.
• The DC level component and the clock noise component not
containing optical signals are output from the DS pin.
• By carrying out differential amplification of the two outputs
OS and DS externally, it is possible to obtain an output signal
with a high S/N ratio by reducing the clock noise, etc.
• The photo detector is provided with 13 optically shielded
pixels (black reference pixels) which serve as the black
reference.
b) CCD Transfer region (shift register)
• The light output that has been photoelectrically converted is
■ Timing Diagram
(1) I/O timing
Integration Time (Tint.)
ø SG
ø1
ø2
2911 2913
2915
RS
1
2 3 4
13 14 15 16 17 18 26 27 28 29 30 31 32 33 34 2910 2912 2914
BT
DS
OS
0
1
2
3
4
13 14 15
B1 B2 B11 B12 B13
Note)
Repeat the transfer
pulses (ø1) for
more than 1460
periods.
2879
2880
D D D
D D D
4 5 6
1
2 3
1
2
3
Black reference
pixel signal
(for 13 pixels)
Blank feed
(for 16 pixels)
Valid pixel signal
(for 2880 pixels)
Invalid pixel signal
(for 3 pixels)
Invalid pixel signal
(for 3 pixels)
MN3646
CCD Linear Image Sensor
(2) Drive timing
90%
10%
tCf
90%
ø 1
tCr
tSr
tSf
ø 2
90%
10%
10%
tRw
tBs
tRh
tRr
tRs
10%
tRf
90%
10%
tBh
ø SG
RS
BT
90%
tRBw
tBr
90%
T
tBf
ø 1
tSs
tSW
tSh
DS
OS
tOS
Reference level
90%
Signal output voltage
■ Graphs and Characteristics
Photoelectric Conversion Characteristics
Spectral Response Characteristics
100
80
60
40
20
0
Under standard
operating condition
10 3
10 2
Characteristics under standard
operating condition
Light source: Red LED
10
–4
10
10 –3
10 –2
500
600
700
800
400
Exposure (lx·s)
Wavelength (nm)
相关型号：
MN3674
Color CCD Linear Image Sensor with 512 Pixels for R and B Colors/1024 Pixels for G Color
PANASONIC
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