MN3673RE [PANASONIC]
CCD Sensor, 0.90-1.20V, Rectangular, Through Hole Mount, DIP-22;
| 型号： | MN3673RE |
| 厂家： | 
PANASONIC |
| 描述： | CCD Sensor, 0.90-1.20V, Rectangular, Through Hole Mount, DIP-22 CD 传感器 换能器 |
| 文件： | 总5页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CCD Linear Image Sensor
MN3673RE
Color CCD Linear Image Sensor
with 2592 Bits each for R, G, and B Colors
■ Overview
■ Pin Assignments
The MN3673RE is a 2592-pixel high sensitivity CCD linear image
sensor combining photo-sites using low dark output floating
photodiodes and CCD analog shift registers for read out. It provides
large output at a high S/N ratio for visible light inputs over a wide
range of wavelength.
1
OS1
VDD
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
14
13
12
OS3
OS2
VSS
V
SS
■ Features
ø R
ø 1D
NC
NC
ø 1A
ø 2A
ø 1B
VSS
ø
R
• 7776 (2592 × R, G, B) floating photodiodes and n-channel buried
type CCD shift registers for read out are integrated in a single chip.
• Since the spacing between the photodiode lines of different colors
is small, it is possible to greatly reduce the memory for
compensation between lines. (1 line between R-B, 10 lines between
B-G)
ø 1D
NC
NC
ø 1C
ø 2C
ø 2B
ø SG
9
10
11
The configuration of the signal processing circuits such as the
preamplifier, sample and hold circuit, etc., becomes simpler since
the separate signal output pins are provided for the pixels of each of
the colors R, G, an B.
•
2592
(Top View)
RGB primary colors type on-chip color filters are used for color
separation.
•
•
C25
WDIP022-C-0440B
The dark signal output voltage has been suppressed to a very low
level due to the use of photodiodes with a new structure. (0.2mV
(typ.) at an accumulation time of 10ms.)
■ Application
• Operation with a single +12V positive power supply.
• Color graphic read out in color copying machines,
color scanners, and color fax machines.
■ Block Diagram
OS3 OS2
22 21
VSS øR
20 19
ø ID
18
ø1C ø2C
15 14
ø2B øSG
13 12
2
2
2
2
2
2
2
2
2
2 2 2 2
1 1 1 1
1
1
1
1
1
1
1
1
1
1
1
1
R
2592
B
BR1 BR2
BB1 BB2
B 24 D 1 D 2 D 3
D 4 D 5 D 6
R R R
R1 R2
B1 B2
R
R
R
R
B 24 D 1 D 2 D 3
D 4 D 5 D 6
B
B
B
B
B
B
B
2592
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
G
2592
BG1 BG2
B 24 D 1 D 2 D 3
D 4 D 5 D 6
G1 G2
G
G
G
G
G
G
G
2
2
2
2
2
2
2
2
2
2
2
2
1
5
1
1
1
1
1
1
1
1
1
1
1
1
1
BR ,BB ,BG : Black reference pixels (24 for each color)
DR ,DB,DG : Dummy invalid pixels (6 for each color)
11
1
2
3
4
8
9
10
øR
øID
OS1
V
DD
V
SS
VSS
ø1A ø 2A
ø1B
MN3673RE
CCD Linear Image Sensor
■ Absolute Maximum Ratings (Ta=25˚C, VSS=0V)
Parameter
Symbol
VDD
Rating
Unit
V
– 0.3 to +17
– 0.3 to +17
– 0.3 to +17
0 to + 60
Power supply voltage
Input pin voltage
V
I
V
Output pin voltage
VO
Topr
Tstg
V
Operating temperature range
Storage temperature range
˚C
˚C
–25 to + 85
■ Operating Conditions
Voltage conditions (Ta=–20 to + 60˚C, VSS=0V)
•
Parameter
Symbol
VDD
Condition
min
11.4
typ
max
13.0
VDD
0.8
Unit
V
Power supply voltage
12.0
CCD shift register clock High level
CCD shift register clock Low level
Shift gate clock High level
Shift gate clock Low level
Reset gate clock High level
Reset gate clock Low level
Vø H
V
(ø1A ~ ø1D, ø2A~ ø2C)
(ø1A ~ ø1D, ø2A~ ø2C)
V
DD -1 VDD
0.5
DD -1 VDD
0.5
VDD -1 VDD
0
Vø L
VSH
VSL
VRH
VRL
V
V
(øSG
(øSG
(øR)
(øR)
)
V
VDD
0.8
)
0
V
V
VDD
0.8
V
0
0.5
Timing conditions (Ta=–20 to + 60˚C)
•
Parameter
Symbol
fC
Condition
min
0.1
0.1
0
typ
—
max
5
Unit
MHz
MHz
ns
Shift register clock frequency
Reset clock frequency
Shift register clock rise time
Shift register clock fall time
Shift clock rise time
fC =fR =1/2T
fR
—
5
tCr
20
50
See timing diagram
See timing diagram
0
20
50
ns
tCf
tSr
0
15
50
ns
0
15
50
ns
tSf
Shift clock fall time
tSs
250
400
1000
ns
Shift clock set up time
Shift clock pulse width
Shift clock hold time
tSw
tSh
tRr
1.0
0
1.8
—
10
10
—
30
10
10
1
µs
µs
ns
ns
ns
ns
ns
Reset clock rise time
0
20
20
—
—
—
tRf
Reset clock fall time
0
tRs
Reset clock set up time
Reset clock pulse width
Reset clock hold time
See timing diagram
0.7T
20
5
tRw
tRh
■ Electrical Characteristics
Clock input capacitance (Ta=0 to + 60˚C)
•
Parameter
Symbol
Condition
min
—
typ
max
—
Unit
pF
C1A, C1B
C1C, C2A
C2B, C2C
300
Shift register clock input capacitance
C1D
CRS
CSG
VIN =12V, f=1MHz
—
—
—
10
10
—
—
—
pF
pF
pF
Shift register final stage clock input capacitance
Reset clock input capacitance
Shift clock input capacitance
250
DC characteristics
•
Parameter
Symbol
IDD
Condition
min
—
typ
10
max
—
Unit
mA
Power supply current
VDD = +12V
CCD Linear Image Sensor
MN3673RE
■ Electrical Characteristics (continued)
AC characteristics
•
Parameter
Symbol
tOS
Condition
min
—
typ
50
max
—
Unit
ns
Signal output delay time
■ Optical Characteristics
<Inspection conditions>
• Ta=25˚C, VDD=12V, VøH=VSH=VRH=12V (pulse), fC=fR=1MHz, Tint (accumulation time)=10ms
• Light source: Daylight type fluorescent lamp with IR/UV cutting filter
•
Optical system: A slit with an aperture dimensions of 20mm
• Load resistance = 100k Ohms
• These specifications apply to the 2592 valid pixels for each color excluding the dummy pixels D1 to D6.
× 20mm is used with a slit to sensor spacing of 200mm (equivalent to F=10).
Parameter
Symbol
RR
Condition
min
0.7
1.4
1.0
—
typ
1.0
2.0
1.4
7
max
1.3
2.6
1.8
15
Unit
RG
Responsivity
V/lx·s
RB
%
V
Photo response non-uniformity
Saturation output voltage
PRNU
Note 1
Note 2
Note 2
Note 2
Note 2
0.9
0.69
0.35
0.50
—
1.2
1.20
0.60
0.86
0.2
0.1
—
—
VSAT
SER
—
SEG
Saturation exposure
—
lx·s
SEB
—
VDRK
DSNU
STTE
ZO
Dark signal output voltage
Dark signal output non-uniformity
Shift register total transfer efficiency
Output impedance
Dark condition, see Note 3
Dark condition, see Note 3
2.0
1.0
—
mV
mV
%
—
92
1
—
—
kΩ
Note 4
—
Dynamic range
DR
—
6000
4.0
50
Signal output pin DC level
Signal output pin DC level difference
Absolute DC level of OS1, OS2, OS3, see Note 5
Relative DC difference between OS1, OS2, OS3, see Note 5
5.5
200
V
V
OS
2.5
—
VOS
mV
Note 1) The photo response non-uniformity (PRNU) is defined by the following equation, where Xave is the average output voltage
of the 2592 valid pixels and ∆x is the absolute value of the difference between Xave and the voltage of the maximum (or
minimum) output pixel, when the surface of the photo-sites is illuminated with light having a uniform distribution over the
entire surface.
x
Xave
×100 (%)
PRNU=
The incident light intensity shall be 50% of the standard saturation.
Note 2) The Saturation output voltage (VSAT) is defined as the output voltage at the point when the linearity of the photoelectric
characteristics cannot be maintained as the incident light intensity is increased. (The light intensity of exposure at this
point is called the saturation exposure.)
Note 3) The dark signal output voltage (VDRK) is defined as the average output voltage of the 2592 pixels in the dark condition at
Ta=25˚C and Tint=10ms. Normally, the dark output voltage doubles for every 8 to 10˚C rise in Ta, and is proportional to
Tint.
VDRK
The dark signal output non-uniformity (DSNU) is defined as the
DSNU
difference between the maximum output voltage among all the valid
pixels and VDRK in the dark condition at Ta=25˚C and Tint=10ms.
Note 4) The dynamic range is defined by the following equation.
V
SAT
VDRK
DR=
Since the dark signal voltage is proportional to the accumulation time, the dynamic range becomes wider when the
accumulation time is shorter.
Note 5) The signal output pin DC level (VOS
) and the
OS1
Reset feed
through level
compensation output pin DC level (VDS) are the voltage
values shown in the following figure.
OS2
OS3
waveform
VOS
VSS
MN3673RE
CCD Linear Image Sensor
■ Pin Descriptions
Pin No.
1
Symbol
Pin name
Signal output 1 (Green)
Power supply
Condition
OS1
VDD
VSS
2
3
Ground
Internally connected to pin 19.
4
Reset clock
øR
Internally connected to pin 18.
5
CCD final stage clock (Phase 1)
Non connection
ø1D
NC
NC
ø1A
6
7
Non connection
8
CCD clock (Phase 1)
CCD clock (Phase 2)
CCD clock (Phase 1)
Ground
9
ø2A
ø1B
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
Shift clock gate
øSG
ø2B
ø2C
ø1C
NC
NC
ø1D
øR
CCD clock (Phase 2)
CCD clock (Phase 2)
CCD clock (Phase 1)
Non connection
Non connection
CCD final stage clock (Phase 1)
Reset clock
Ground
V
SS
Signal output 2 (Red)
Signal output 3 (Blue)
OS2
OS3
Note) Connect all NC pins externally to VSS (GND).
■ Construction of the Image Sensor
charge transferred to this analog shift register is successively
transferred out and guided to the output.
The MN3673RE can be made up of the three sections of—a)
photo detector region, b) CCD transfer region (shift register),
and c) output region.
• A buried type CCD that can be driven by a two phase clock
(ø1, ø2) is used for the analog shift register.
a) Photo detector region
The last gate of the CCD transfer region is connected
•
to an
• The photoelectric conversion device consists of an 11µm
floating photodiode and a 3µm channel stopper (isolation
region) per pixel, and such 2592 pixels per color are arranged
in a linear row with a pitch of 14µm along the main scanning
direction with the pixel rows of different colors being placed
parallel to each other.
independent pin (ø1D). By driving this pin independent of the
other pins by a clock driver, it is possible to speed up the flow
of signal charge into the charge to voltage conversion region
thereby making the output waveform rise sharply. This
makes it easy to obtain margin of the signal processing time
during high speed drive operation.
There is a spacing of one line between R-B in the
•
sideways
c) Output region
scanning direction (center to center spacing of 14µm) and a
10 line spacing between B-G in the sideways scanning
direction (center to center spacing of 140µm).
• The signal charge transferred to the output region is first sent
to the charge to voltage conversion region where it is
converted into a voltage level corresponding to the amount of
the signal charge, and then output after impedance conversion
in a two stage source follower amplifier.
• The photo detector's windows are 14µm × 14µm squares and
light incident on areas other than these windows is optically
shut out.
• The photo detector is provided with 24 optically shielded
pixels (black reference pixels) which serve as the black
reference.
b) CCD Transfer region (shift register)
• The light output that has been photoelectrically converted is
transferred to the CCD transfer for each odd and even pixel
at the timing of the shift clock (øSG). The optical signal
CCD Linear Image Sensor
MN3673RE
■ Timing Diagram
(1) I/O timing
Integration Time (Tint.)
øSG
ø1A
ø1B
2622 2624
2626
0
1
2
2
3
3
4
4
5
5
6
26 27 28 29 30 31 32 33 2621 2623 2625
ø1C
ø1D
ø2A
ø2B
ø2C
2623 2625 2627
27 28 29 30 31 32 33 34 2622 2624 2626
1
6
7
øR
OS
OS23
B1 B2
B23 B24 D1 D2 D3
1
2
2591 2592 D D5 D6
4
OS1
Blank feed
(for 4 pixels)
Black reference
pixels
(for 24 pixels)
Dummy Valid pixel signal Invalid pixel
invalid
pixels
(for 2592 pixels)
signal
(for 3 pixels)
(for 3 pixels)
(2) Drive timing
90%
10%
tCf
90%
50%
10%
tRW
ø2
(ø 1)
ø1
tCr
(ø 2)
tRS
tRh
90%
50%
10%
tSr
tSf
90%
50%
10%
øR1
(øR2)
tRr
tRf
tOh
ø SG
2T
tOS
50%
Reference level
OS1
(OS2)
(OS3)
ø 1
50%
tSs
tSh
tSW
Effective signal
output period
■ Graphs and Characteristics
Spectral Response Characteristics
100
80
60
40
20
0
Green
Red
Blue
500
600
700
800
400
Wavelength (nm)
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