MN3674 [PANASONIC]

Color CCD Linear Image Sensor with 512 Pixels for R and B Colors/1024 Pixels for G Color; 有512个像素的R,B颜色/ 1024像素的G色色线性CCD图像传感器
MN3674
型号: MN3674
厂家: PANASONIC    PANASONIC
描述:

Color CCD Linear Image Sensor with 512 Pixels for R and B Colors/1024 Pixels for G Color
有512个像素的R,B颜色/ 1024像素的G色色线性CCD图像传感器

传感器 图像传感器 CD
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CCD Linear Image Sensor  
MN3674  
Color CCD Linear Image Sensor  
with 512 Pixels for R and B Colors/1024 Pixels for G Color  
Overview  
Pin Assignments  
The MN3674 is a high responsivity CCD color linear image sensor  
with 512 pixels each for R and B and 1024 G pixels, and having low  
dark output floating photodiodes in the photodetector region and  
CCD analog shift registers for read out.  
1
NC  
NC  
OS1  
DS1  
1
2
3
4
5
6
7
8
9
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
NC  
NC  
OS2  
DS2  
VDD  
NC  
ø 2  
ø SG2  
ø V  
NC  
NC  
It can read a 64mm-width color document with a high quality and a  
maximum pseudo resolution of 400dpi. In addition to being used as a  
color sensor, this device can also be used as a black and white sensor  
if only the G row is used, and in this case, it is possible to read a  
64mm-width document with a full resolution of 400dpi. Since a one  
line delay analog memory is built in so as to compensate for the  
difference in the positions of reading out between the R, B rows and  
the G row, the configuration of the signal processing circuit becomes  
simpler.  
V
SS  
ø R  
ø 1  
ø SG1  
V
SS  
V
10  
11  
SS  
NC  
Features  
1024  
2048 floating photodiodes and n-channel buried type CCD shift  
registers for read out are integrated in a single chip.  
RGB primary colors type on chip color filters are used for color  
separation.  
(Top View)  
C26  
WDIP022-G-0470B  
In order to compensate for the distance between the photodiode  
rows for the R, B colors and the G color, the device has a built in  
analog memory that can store the signals of one line of the R-B  
colors row.  
All clock inputs can be driven by 5V CMOS logic.  
Use of photodiodes with a new structure has made the dark output  
voltage very low.  
Large signal output of typically 0.8V at saturation can be obtained.  
Application  
Color graphic read out in color image scanners, color fax machines,  
etc.  
CCD Linear Image Sensor  
MN3674  
Block Diagram  
OS2 DS2  
20 19  
VDD  
18  
ø2 øSG2 øV  
16 15  
14  
1
2
2
2
2
2
2
2
2
2
2 2 2 2  
1 1 1 1 1  
1
1
1
1
1
1
1
1
1
1-line delay analog memory  
R
B
B2  
B32 D2 D4 R1 B1 R2  
512 D6 D8  
B4  
512  
G
G
B1 B3  
B31 D1 D3 G1 G2 G3  
D7  
1023 1024 D5  
2
2
2
2
2
2
2
2
2
2
2 2 2  
1 1 1  
1
1
1
1
1
1
1
1
1
1
1
B1 to B32 : Black reference pixels  
D1 to D8 : Dummy invalid pixels  
1
D
10  
3
4
5
6
7
8
9
OS1 DS1 V  
øR  
ø1 øSG1 VSS VSS  
SS  
Absolute Maximum Ratings (Ta=25˚C, VSS=0V)  
Parameter  
Symbol  
VDD  
Rating  
Unit  
Power supply voltage  
– 0.3 to + 15  
– 0.3 to + 15  
V
V
Input pulse voltage  
VI  
Topr  
Operating temperature range  
Storage temperature range  
˚C  
˚C  
0 to + 60  
Tstg  
25 to + 85  
Operating Conditions  
Voltage conditions (Ta=0 to + 60˚C, VSS=0V)  
Parameter  
Symbol  
VDD  
Condition  
min  
typ  
12.0  
5.0  
0.2  
5.0  
0.2  
5.0  
0.2  
5.0  
0.2  
max  
13.0  
Unit  
V
Power supply voltage  
11.4  
4.5  
0
Vø H  
Vø L  
VVH  
VVL  
VSH  
VSL  
VRH  
VRL  
V
CCD shift register clock High level  
CCD shift register clock Low level  
Vertical transfer clock High level  
Vertical transfer clock Low level  
Shift gate clock High level  
Shift gate clock Low level  
V
DD  
1, ø2)  
V)  
0.5  
V
V
4.5  
0
V
DD  
V
0.5  
V
4.5  
0
V
DD  
SG1, øSG2  
)
V
0.5  
V
Reset gate clock High level  
Reset gate clock Low level  
4.5  
0
V
DD  
R)  
0.5  
V
MN3674  
CCD Linear Image Sensor  
Timing conditions (without 1-line delay operation) (Ta=0 to + 60˚C)  
Parameter  
Symbol  
fC  
Condition  
min  
0.1  
0.1  
0
typ  
1.0  
1.0  
20  
20  
15  
15  
10  
max  
3.0  
3.0  
50  
Unit  
MHz  
MHz  
ns  
Shift register clock frequency  
Reset clock frequency (=data rate)  
Shift register clock rise time  
Shift register clock fall time  
Vertical transfer clock rise time  
Vertical transfer clock fall time  
Vertical transfer clock pulse width  
Shift clock 1 rise time  
See drive timing diagram (3) fC=1/2T  
See drive timing diagram (3) fR=1/2T  
fR  
tCr  
See drive timing diagram (3)  
0
50  
ns  
tCf  
tVr  
0
50  
ns  
øSG1 and øV should be the same timing.  
See drive timing diagram (1)  
0
50  
tVf  
ns  
5
50  
µs  
tVW  
tSG1r  
tSG1f  
tSG1s  
tSG1w  
tSG2r  
tSG2f  
tSG2s  
tSG2w  
tSG2h  
tRr  
ns  
0
0
15  
15  
1.0  
10  
15  
15  
1.0  
10  
1
50  
50  
2.0  
50  
50  
50  
2.0  
50  
2
ns  
Shift clock 1 fall time  
See drive timing diagram (1)  
See drive timing diagram (1)  
µs  
Shift clock 1 set up time  
Shift clock 1 pulse width  
Shift clock 2 rise time  
0.5  
5
µs  
0
ns  
ns  
µs  
µs  
µs  
Shift clock 2 fall time  
0
Shift clock 2 set up time  
Shift clock 2 pulse width  
Shift clock 2 hold time  
0.5  
5
0
0
10  
10  
200  
125  
ns  
ns  
ns  
ns  
ns  
Reset clock rise time  
20  
20  
tRf  
0
Reset clock fall time  
tRs  
See drive timing diagram (3)  
0.7T  
100  
10  
Reset clock set up time  
tRw  
Reset clock pulse width  
Reset clock hold time  
tRh  
Timing conditions (during 1-line delay operation) (Ta=0 to + 60˚C)  
Parameter  
Symbol  
fC  
Condition  
min  
0.1  
0.1  
0
typ  
1.0  
1.0  
20  
max  
3.0  
3.0  
50  
Unit  
MHz  
MHz  
ns  
Shift register clock frequency  
Reset clock frequency (=data rate)  
Shift register clock rise time  
Shift register clock fall time  
Vertical transfer clock rise time  
Vertical transfer clock fall time  
Vertical transfer clock set up time  
Vertical transfer clock pulse width  
Vertical transfer clock hold time  
Shift clock 1 rise time  
See drive timing diagram (3) fC=1/2T  
See drive timing diagram (3) fR=1/2T  
fR  
tCr  
See drive timing diagram (3)  
0
20  
50  
ns  
tCf  
tVr  
0
15  
50  
ns  
0
15  
50  
tVf  
ns  
ø SG1 and øV should be the same timing.  
See drive timing diagram (2)  
0.5  
1.0  
2.0  
µs  
tVs  
tVw  
tVh  
tSG1r  
tSG1f  
µs  
5
0
10  
1
50  
2
µs  
ns  
0
15  
15  
10  
15  
15  
1.0  
10  
10  
10  
50  
50  
50  
50  
50  
2.0  
50  
20  
20  
See drive timing diagram (2)  
See drive timing diagram (2)  
0
ns  
Shift clock 1 fall time  
tSG1w  
tSG2r  
tSG2f  
tSG2s  
tSG2w  
µs  
5
Shift clock 1 pulse width  
Shift clock 2 rise time  
ns  
0
ns  
Shift clock 2 fall time  
0
µs  
0.5  
5
Shift clock 2 set up time  
Shift clock 2 pulse width  
Reset clock rise time  
µs  
0
ns  
ns  
ns  
ns  
ns  
tRr  
tRf  
0
Reset clock fall time  
tRs  
tRw  
tRh  
See drive timing diagram (3)  
0.7T  
100  
100  
Reset clock set up time  
200  
125  
Reset clock pulse width  
Reset clock hold time  
CCD Linear Image Sensor  
MN3674  
Electrical Characteristics  
Clock input capacitance (Ta=–20 to + 60˚C)  
Parameter  
Symbol  
C1 , C2  
CV  
Condition  
min  
typ  
200  
100  
20  
max  
Unit  
pF  
CCD Shift register clock input capacitance  
Vertical transfer clock input capacitance  
Reset clock input capacitance  
Shift clock input capacitance  
pF  
pF  
pF  
VIN =5V  
f=1MHz  
CRS  
CSG1, CSG2  
100  
DC characteristics  
Parameter  
Symbol  
IDD  
Condition  
Condition  
min  
typ  
10  
max  
20  
Unit  
mA  
Power supply current  
VDD = +12V  
AC characteristics  
Parameter  
Symbol  
tOS  
min  
typ  
50  
max  
Unit  
ns  
Signal output delay time  
(a reference value)  
Optical Characteristics  
<Inspection conditions>  
Ta=25˚C, VDD=12V, VøH=VVH=VSH=VRH=5V (pulse), fC=fR=1MHz, Tint (accumulation time)=10ms  
Light source: Daylight fluorescent lamp with IR/UV cutting filter  
Optical system: A slit with an aperture dimensions of 20mm × 20mm is used at a distance of 200mm from the sensor (equivalent  
to F=10).  
Load resistance = 100k Ohms  
These specifications apply to the 512 valid R and G pixels and the 1024 valid G pixels excluding the dummy pixels D1 to D8.  
Parameter  
Symbol  
RR  
Condition  
min  
0.70  
1.40  
0.90  
typ  
0.95  
1.80  
1.20  
6
max  
1.20  
Unit  
Note 1  
Note 1  
Note 1  
Note 2  
Note 3  
Note 4  
Note 4  
Note 4  
2.20 V/lx · s  
1.50  
Responsivity  
RG  
RB  
Photo response non-uniformity  
Saturation output voltage  
PRNU  
VSAT  
SER  
15  
%
mV  
650  
0.67  
0.36  
0.53  
800  
0.84  
0.44  
0.67  
0.5  
lx · s  
mV  
SEG  
Saturation exposure  
SEB  
VDRK1  
VDRK2  
OS1, Dark condition, see Note 5  
OS2, Dark condition, see Note 5  
OS1, Dark condition, see Note 6  
OS2, Dark condition, see Note 6  
1.0  
2.0  
2.0  
4.0  
Dark signal output voltage  
1.0  
0.1  
DSNU1  
DSNU2  
STTE  
DR  
Dark signal output non-uniformity  
mV  
%
0.2  
92  
99  
Shift register total transfer efficiency  
Dynamic range  
Note 7  
800  
Note 1) Responsivity (R)  
This is the value obtained by dividing the average output voltage (V) of the all pixels by the exposure (lx· s).  
The exposure (lx· s) is the product of the illumination intensity (lx) and the accumulation time (s).  
Since the responsivity changes with the spectral distribution of the light source used, care should be taken when using a  
light source other than the daylight type fluorescent lamp specified in the inspection conditions.  
Note 2) Photo response non-uniformity (PRNU)  
This is defined by the following equation where Xave is the average output voltage of the valid pixels of each of the colors  
R, G, and B, and x is the difference between the output voltage of the maximum (or minimum) output pixel and Xave  
,
when the photodetector region is illuminated with light of a uniform illumination intensity distribution.  
x
Xave  
×100 (%)  
PRNU=  
The incident light intensity shall be 50% of the standard saturation llight intensity.  
MN3674  
CCD Linear Image Sensor  
Optical Characteristics (continued)  
Note 3) Saturation output voltage:  
This is the output voltage at the point beyond which it is not possible to maintain the linearity of the photoelectric  
conversion characteristics as the exposure is increased. (The exposure at this point is called the saturation exposure.)  
Note 4) Saturation Exposure (SE)  
This is the exposure beyond which it is not possible to maintain the linearity of the output voltage as the exposure is  
increased. When designing the equipment using these devices, make sure that the incident light exposure is set with  
sufficient margin so that the CCD never gets saturated.  
Note 5) Dark signal output voltage (VDRK  
)
This is defined as the average of the output from all the valid pixels in the dark condition at Ta=25˚C, T =10ms.  
int  
Normally, the dark signal output voltage gets doubled for every 8 to 10˚C increase in Ta and is proportional to Tint. The  
dark signal output voltage (VDRK2) on the OS2 side will be larger than the dark signal output voltage (VDRK1) on the OS1  
side because there is a delay memory on the OS2 side.  
Note 6) Dark signal non-uniformity (DSNU)  
This is defined as the difference between the maximum value among the output voltages of the all valid pixels at  
Ta=25˚Cand Tint=10ms and VDRK  
.
VDRK  
DSNU  
Note 7) Dynamic range (DR)  
This is defined by the following equation.  
V
SAT  
VDRK  
DR=  
Since the dark signal output voltage is proportional to the accumulation time, the dynamic range becomes wider when the  
accumulation time is shorter.  
Pin Descriptions  
Pin No.  
1
Symbol  
NC  
Pin name  
Condition  
Non connection  
Non connection  
Signal output 1  
2
NC  
3
OS1  
Green pixel output  
4
DS1  
Compensation output 1  
Ground  
5
V
SS  
6
øR  
ø1  
Reset clock  
7
CCD clock (Phase 1)  
CCD shift register clock 1  
Ground  
8
ø
SG1  
9
V
SS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
V
Ground  
SS  
Non connection  
Non connection  
Non connection  
Vertical transfer clock  
Shift clock gate 2  
CCD clock (Phase 2)  
Non connection  
Power supply  
NC  
NC  
NC  
øV  
øSG2  
ø2  
NC  
VDD  
DS2  
OS2  
NC  
NC  
Compensation output 2  
Signal output 2  
Non connection  
Non connection  
Red and Blue pixel output  
Note) Connect all NC pins externally to VSS (GND).  
CCD Linear Image Sensor  
MN3674  
Construction of the Image Sensor  
The MN3674 can be made up of the three sections of—a) photo detector region, b) CCD transfer region (shift register), and c)  
output region.  
a) Photo detector region  
The photoelectric conversion device consists of an 11µm floating photodiode and a 3µm channel stopper (isolation region) per  
pixel, and such pixels are arranged in a linear row with a pitch of 14µm along the main scanning direction.  
The R-B row has 512 pixels each of the red and blue colors arranged alternatingly, and the G row has1024 pixels. The R-B row  
and G row are placed with a spacing of one line (14µm) along the sideways scanning direction. The pixels of the G row are  
displaced by half the pixel pitch (7µm) relative to the pixels of the R-B row in the main scanning direction.  
1
R
1
B
2
R
2·  
B
· · · · · · 512 512  
R
B
·
·
·
·
·
·
·
14µm  
G G G G  
4 ·  
·
·
·
·
·
G G  
1
2
3
·
·
·
·
· 1023 1024  
14µm  
14µm 14µm  
A one line analog delay memory is built in the chip in order to compensate for the difference in the positions of the R-B and G  
rows in the sideways scanning direction.  
The photodetector window is a rectangle of dimensions 9 m  
µ
(Horizontal) × 11µm (Vertical), and the areas other than the  
photodetector window are optically shielded.  
The photodetector region has a total of 32 optically  
with 16 pixels each for the R-B row and the G row.  
shielded (black reference) pixels that can be used as the black level reference,  
b) CCD Transfer region (shift register)  
The signal charges obtained by photoelectric conversion are transferred to the CCD transfer regions of the respective colors  
during the period when the shift gate (øSG) is at the High level. The signal charges transferred to this analog shift register are  
successively transferred to the output region.  
A buried type CCD that can be driven by a two phase clock (ø1, ø2) is used for the analog shift register.  
c) Output region  
The signal charge transferred to the output region is first sent to the charge to voltage conversion region where it is converted  
into a voltage level corresponding to the amount of the signal charge, and then output after impedance conversion in a two stage  
source follower amplifier.  
The DC level component not containing the optical signal and the clock noise component are output at the DS pin.  
It is possible to obtain a signal with a high S/N ratio  
the OS and DS outputs externally.  
with reduced clock noise, etc., by carrying out differential amplification of  
1-Line delay analog memory  
In order to compensate for the distance between the photodiode rows for the R, B colors and the G color, the device has a built in  
analog memory that can store the signals of one line. It is possible to select either to use or not use the delay memory by the  
timings of the pulses øV, øSG1, and øSG2, and the two types of read out operation of 512 pixel operation and pseudo 1024 pixel  
operation can be obtained accordingly.  
(1) 512-pixel operation (no delay memory)  
is taken as one pixel thereby making this device a 512-pixel color CCD.  
R
B
G G  
(Each pixel of the color sensor will be a parallelogram of 28µm (horizontal) × 28µm (vertical).)  
(2) Pseudo 1024-pixel operaation (delay memory is used)  
1022  
1023  
2
4
A 1-line delay operation and interpolation signal processing  
shown in the figure at left are made for the R-B colors.  
1
3
5
· · · · · ·  
B · · · B  
· · ·  
R
B
R
B
R
R
B
B
R
R B  
G G G G G G  
G G G  
G
or  
G
becomes one pixel during color sensing operation.  
1
2 3 4 5  
6 · · · 1022 1024  
1023  
* Since the signal from the R-B row gets delayed, configure the optical system and mechanisms so that the sideways scanning is  
done first from the R-B row. The R-B row and the G row of the same line will be read out due to the one line delay.  
The weighted center of one color pixel can be considered to be at the position of the G pixel.  
MN3674  
CCD Linear Image Sensor  
Timing Diagram  
I/O timing (1) (without 1-line delay operation)  
øSG1  
øV  
øSG2  
ø1  
ø2  
øR  
0
1
2
17 18 19 20 21 22  
1041  
1043 1045  
1042 1044 1046  
DS1  
OS1  
B
1
B
29 B  
31  
D
1
D
5
D
3
D7  
G1024  
G1022  
G1 G2 G3 G1021  
Blank feed level  
G1023  
DS2  
OS2  
B
2
B30 B  
32  
D
2
D
4
D6  
D8  
Note)  
Repeat the transfer  
pulses (ø1 , ø2) for  
more than 1046  
periods.  
B512  
R1 B1 R2 R511 R512  
B511  
B1 to B32 : Black reference pixels  
D to D8 : Dummy invalid pixels  
1
I/O timing (2) (during 1-line delay operation)  
øSG1  
øV  
øSG2  
ø1  
ø2  
øR  
0
1
2
17 18 19 20 21 22  
1041  
1043 1045  
1042 1044 1046  
DS1  
OS1  
B
1
B29 B  
31  
D1  
D
D
D
5
3
7
G1024  
G1023  
G1022  
Blank feed level  
G1 G2 G3 G1021  
DS2  
OS2  
B2  
B30 B  
32  
D
2
D
4
D
6
D8  
B512  
R1 B1 R2 R511 R512  
B511  
B1 to B32 : Black reference pixels  
Note)  
Repeat the transfer  
pulses (ø1 , ø2) for  
more than 1046  
periods.  
D to D8 : Dummy invalid pixels  
1
* OS2 outputs the previous line signal.  
CCD Linear Image Sensor  
MN3674  
Drive timing (1) (read-out during no 1-line delay operation)  
tSG1r  
tSG1f  
90%  
50%  
10%  
øSG1  
tSG1w  
tVr  
tVf  
90%  
50%  
10%  
tSG2r  
tSG2f  
øV  
tVw  
tSG2s  
90%  
50%  
10%  
tSG2w  
øSG2  
50%  
50%  
ø1  
tSG1s  
tSG2h  
Note) Make sure that the timings of øSG and øV are identical.  
(If these are not identical, the accumulation time gets shifted and hence the data on  
the same line cannot be obtained.)  
Drive timing (2) (read-out during 1-line delay operation)  
tSG1r  
tSG1f  
90%  
50%  
10%  
øSG1  
tSG1w  
tVr  
tVf  
90%  
50%  
10%  
tSG2r  
tSG2f  
øV  
tVs  
tVw  
90%  
50%  
10%  
øSG2  
50%  
50%  
ø1  
tSG2s  
tSG2w  
tVh  
Note) Make sure that the timings of øSG and øV are identical.  
(If these are not identical, the accumulation time gets shifted and hence the data on  
the same line cannot be obtained.)  
MN3674  
CCD Linear Image Sensor  
Drive timing (3) (during repeated pattern)  
90%  
10%  
ø2  
tCr  
tCf  
90%  
50%  
10%  
ø1  
tRS  
tRW  
tRh  
90%  
50%  
10%  
øR  
tRr  
tRf  
DS1  
(DS2)  
tOh  
2T  
tOS  
Reference level  
OS1  
50%  
(OS2)  
Effective signal  
output period  
Graphs and Characteristics  
Spectral Response Characteristics  
100  
80  
60  
40  
20  
0
Green  
Red  
Blue  
500  
600  
700  
800  
400  
Wavelength (nm)  

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D/A Converter, 1 Func, Parallel, Word Input Loading, 50us Settling Time, CDIP18, HERMETIC SEALED, CERAMIC, DIP-18
SPECTRUM

MN370H/B

D/A Converter, 1 Func, Parallel, Word Input Loading, 50us Settling Time, CDIP18, HERMETIC SEALED, CERAMIC, DIP-18
SPECTRUM

MN37110FP

CCD Sensor, 0.65V, Square, 0.400 INCH, WINDOWED, PLASTIC, DIP-14
PANASONIC

MN371121FT

CCD Sensor, 0.65V, Square, Through Hole Mount, 0.400 INCH, WINDOWED, PLASTIC, DIP-14
PANASONIC

MN371132FT

CCD Sensor, 537 Horiz pixels, 505 Vert pixels, 0.65V, Square, Through Hole Mount, DIP-14
PANASONIC

MN3711AE

CCD Sensor, 1V, Rectangular, 0.500 INCH, WINDOWED, CERAMIC, DIP-16
PANASONIC

MN3711CFP

Analog Circuit, 1 Func, PDIP14, DIP-14
PANASONIC

MN3711FE

CCD Sensor, 1V, Rectangular, 0.500 INCH, WINDOWED, CERAMIC, DIP-16
PANASONIC

MN3713AE(EIS)

CCD Sensor, 1V, Rectangular, 0.500 INCH, WINDOWED, CERAMIC, DIP-16
PANASONIC

MN3713FE

CCD Sensor, 858 Horiz pixels, 614 Vert pixels, 15.60-16.80V, Rectangular, Through Hole Mount, DIP-16
PANASONIC