MN3665A [PANASONIC]
CCD Sensor, 1-1.60V, Rectangular, Through Hole Mount, DIP-22;
| 型号： | MN3665A |
| 厂家： | 
PANASONIC |
| 描述： | CCD Sensor, 1-1.60V, Rectangular, Through Hole Mount, DIP-22 CD 传感器 换能器 |
| 文件： | 总7页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CCD Linear Image Sensor
MN3665A
10000-Bit High-Resolution CCD Linear Image Sensor
■ Overview
■ Pin Assignments
The MN3665A is a high-speed high-resolution CCD linear image
sensor having low dark output floating photodiodes in the
photodetector region and CCD analog shift registers for read out.
It provides large output at a high S/N ratio for visible light inputs over
a wide range of wavelength.
1
OS1
DS1
OG
ø R1
ø 2D
ø 1D
VSS
ø 1A
ø 2A
TG
OS2
DS2
VDD
ø R2
ø 2C
ø 1C
VSUB
ø 1B
ø 2B
IS
1
2
22
21
20
19
18
17
16
15
14
13
12
3
■ Features
4
• 10000 floating photodiodes and n-channel buried type CCD shift
registers for read out are integrated in a single chip.
5
6
An A3 size document can be read with a high resolution of 800dpi.
Permits high speed scanning of a data rate of 6MHz.
High blue responsivity of a maximum responsivity ratio of 60%
(typ.) at 400nm, and smooth spectral response over the entire
visible region.
•
•
•
7
8
9
10
11
PG
ø SG
Large signal output of 1.6V (typ.) at saturation can be obtained.
•
10000
• Since a compensation output pin (DS) is provided in addition to the
signal output pin (OS), it is possible to obtain a signal with a high
S/N ratio by carrying out differential amplification of the OS and
DS outputs.
(Top View)
C23
WDIP022-C-0400D
• Operation with a single +12V positive power supply.
■ Application
• Graphic and character read out in fax machines,
image scanners, etc.
■ Block Diagram
OS2 DS2
22 21
IS
øSG
13 12
VDD
20
ø R2 ø2C ø1C
VSUB ø1B ø2B
19
18 17
16
14
15
2
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
1
2
11
1
2
3
4
5
6
7
8
9
10
OS1 DS1
OG
øR1 ø2D ø1D
VSS ø1A ø2A TG PG
B1 to B32 : Black reference pixels
D1 to D 4 : Dummy invalid pixels
MN3665A
CCD Linear Image Sensor
■ Absolute Maximum Ratings (Ta=25˚C, VSS=0V)
Parameter
Symbol
VDD
Rating
Unit
– 0.3 to +17
– 0.3 to +17
– 0.3 to +17
– 0.3 to +17
– 0.3 to +17
– 0.3 to +17
– 0.3 to +17
–20 to + 60
–40 to +100
V
V
VSUB
VIS
Power supply voltage
V
VOG
V
V
PG
V
Input pin voltage
VI
V
Output pin voltage
VO
V
Operating temperature range
Storage temperature range
Topr
Tstg
˚C
˚C
■ Operating Conditions
Voltage conditions (Ta=–20 to + 60˚C, VSS=0V)
•
Parameter
Symbol
VDD
Condition
min
typ
max
12.5
12.5
12.5
Unit
V
Power supply voltage
IS test pin voltage
Substrate voltage
11.5
11.5
11.5
12.0
12.0
12.0
VIS
V =V
IS DD
V
VSUB
VOG
VPG
V
SUB =V
V
DD
Output gate voltage
VDD=12V
PG =VOG
4.2
4.2
0
4.5
4.5
0
4.8
4.8
0.3
VDD
0.8
VDD
0.8
VDD
0.8
V
V
V
V
V
V
V
V
V
V
Photo storage gate voltage
TG test pin voltage
VTG=VSS
VTG
Vø H
9.0
0
10.0
0.5
CCD shift register clock High level
CCD shift register clock Low level
Shift gate clock High level
Shift gate clock Low level
Reset gate clock High level
Reset gate clock Low level
Vø L
VSH
VSL
VRH
VRL
VDD –1 VDD
0
VDD –1
0
0.5
VDD
0.5
Timing conditions (Ta=–20 to + 60˚C)
•
Parameter
Symbol
fC
Condition
min
0.1
0.1
0
typ
1.0
1.0
20
max
3.0
3.0
50
Unit
MHz
MHz
ns
Shift register clock frequency
Reset clock frequency
Shift register clock rise time
Shift register clock fall time
Shift clock rise time
fC=fR=1/2T
fR
tCr
See timing diagram
See timing diagram
0
20
50
ns
tCf
tSr
0
15
50
ns
0
15
50
ns
tSf
Shift clock fall time
tSs
250
400
1000
ns
Shift clock set up time
Shift clock pulse width
Shift clock hold time
tSw
tSh
tRr
µs
1.0
0
1.8
0.5
10
10
—
30
10
10
1
µs
Reset clock rise time
0
20
20
—
—
—
ns
ns
ns
ns
ns
tRf
Reset clock fall time
0
tRs
Reset clock set up time
Reset clock pulse width
Reset clock hold time
See timing diagram
0.7T
20
5
tRw
tRh
MN3665A
CCD Linear Image Sensor
■ Electrical Characteristics
Clock input capacitance (Ta=–20 to + 60˚C)
•
Parameter
Symbol
C1A, C2A
C1B, C2B
Condition
min
—
typ
max
750
Unit
pF
600
Shift register clock input capacitance
VIN =12V
f=1MHz
—
—
15
30
pF
pF
CR
CS
Reset clock input capacitance
Shift clock input capacitance
250
300
*ø1A, ø2A, ø1B, and ø2B are respectively connected to ø1D, ø2D, ø1C, and ø2C internally.
DC characteristics
•
Parameter
Symbol
IDD
Condition
min
—
typ
20
0.1
5
max
50
1
Unit
mA
mA
µA
Power supply current
=+12V
=+5V
VDD
VDD
IIS
IS test pin leak current
—
IPG
Photo storage gate leak current
Output gate pin leak current
—
50
50
IOG
µA
—
5
AC characteristics
•
Parameter
Symbol
tOS
Condition
See timing diagram
min
—
typ
30
30
max
—
Unit
ns
Signal output set up time *
Signal output hold time
tOW
ns
—
—
* OS output level: =500mV
■ Optical Characteristics
<Inspection conditions>
• Ta=25˚C, standard operating condition, fC=fR=1MHz, Tint (accumulation time)=10ms
• Light source: Daylight type fluorescent lamp
• Optical system: A slit with an aperture dimensions of 20mm × 20mm is used at a distance of 200mm from the sensor (equivalent
to F=10).
• This parameters are inspected by signal multiplex with channels 1 and 2 which correspond to the output of both OS1 and DS1
(channel 1) and the output of both OS2 and DS2 (channel 2) respectively. Before multiplex the channels 1 and 2, the OS and DS
signals should be respectively through unity gain differential amplifiers with input impedances of 100k Ohms or more, carrying
out zero level DC clamping of each channel.
• These specifications apply to the 10000 valid pixels excluding the dummy pixels D1 to D4.
Parameter
Responsivity
Symbol
R
Condition
min
1.3
—
typ
1.8
—
max
2.3
10
Unit
V/lx· s
%
Note 1
Note 2
Note 3
Note 4
Note 5
PRNU
BNU
VSAT
Photo response non-uniformity
Bit non-uniformity
—
—
±8
—
%
Saturation output voltage
Saturation exposure
1.60
0.89
0.5
0.2
—
V
1.00
0.43
—
SE
lx· s
—
VDRK
DSNU
STTE
DR
Dark signal output voltage
Dark signal output non-uniformity
Shift register total transfer efficiency
Dynamic range
Dark condition, see Note 6
Dark condition, see Note 7
Note 8
3.0
2.0
—
mV
mV
%
—
92
Note 9
—
3200
65
—
MTFR
Modulation transfer function
Note 10
—
—
%
* The definitions of the parameters are given in Note 1) to Note 10) on the following page.
MN3665A
CCD Linear Image Sensor
■ Optical Characteristics (continued)
Note 1) Responsivity (R)
This is the value obtained by dividing the average output voltage (V) of the 10000 valid pixels by the exposure (lx·s).
The exposure (lx·s) is the product of the illumination intensity (lx) and the accumulation time (s).
Since the responsivity changes with the spectral distribution of the light source used, care should be taken when using a
light source other than the daylight type fluorescent lamp specified in the inspection conditions.
Note 2) Photo response non-uniformity (PRNU)
The photo response non-uniformity (PRNU) is defined by the following equation, where Xave is the average output voltage
of the valid 10000 pixels and ∆x is the absolute value of the difference between the maximum and minimum voltage, when
the surface of the photo-sites is illuminated with light having a uniform distribution over the entire surface.
x
×100 (%)
PRNU=
Xave
The incident light intensity shall be 50% of the standard saturation llight intensity.
Note 3) Bit non-uniformity (BNU)
This is defined by the following equation where the output voltage of each pixel among the 10000 pixels is denoted by Xi
(i = 1 to 10000) when the photodetector region is illuminated by a light of uniform illumination intensity distribution, and
the average output voltage of the pixels near the ith pixel is denoted by Xlocal-ave. (a total of 20 pixels with 10 pixels before
and 10 pixels after that pixel). Here, the max. operation consists of comparing with the absolute value and assigning the
sign of the numerator.
Xi – Xlocal-ave.
Xlocal-ave.
BNU=max. (
)
×100 (%)
The incident light intensity shall be 50% of the standard saturation llight intensity.
Note 4) Saturation output voltage (VSAT
)
This is the output voltage at the point beyond which it is not possible to maintain the linearity of the photoelectric
conversion characteristics as the exposure is increased. (The exposure at this point is called the saturation exposure.)
Note 5) Saturation Exposure (SE)
This is the exposure beyond which it is not possible to maintain the linearity of the output voltage as the exposure is
increased. When designing the equipment using these devices, make sure that the incident light exposure is set with
sufficient margin so that the CCD never gets saturated.
Note 6) Dark signal output voltage (VDRK
)
This is defined as the average of the output from the 10000 active pixels in the dark condition at Ta=25˚C, Tint=10ms.
Since normally the dark signal output voltage gets doubled for every 8 to 10˚C increase in Ta and is proportional to Tint, it
is necessary to convert the value if Ta andTint are different from the inspection conditions given above. (See the figure
below.)
Note 7) Dark signal non-uniformity (DSNU)
This is defined as the difference between the maximum value among the output voltages from the 10000 valid pixels at
Ta=25˚C and Tint=10ms and VDRK. (See the figure below.)
V
DRK
DSNU
Note 8) Shift register total transfer efficiency (STTE)
This is given by the following equation where the average output voltage of all the 10000 pixels is denoted by Xave. and the
larger of the output voltages of the 2 dummy pixels following the dummy pixel D4 is denoted by Xr when the
photodetector region is illuminated by a light of uniform illumination intensity distribution.
Xave. – Xr
Xave.
STTE=
×100 (%)
Note 9) Dynamic range (DR)
This is defined by the following equation.
V
SAT
VDRK
DR=
Since the dark signal output voltage is proportional to the accumulation time, the dynamic range becomes wider when the
accumulation time is shorter. This value is not a guaranteed value, but is merely a reference value.
Note 10) Modulation transfer function (MTFR)
This is defined by the following equation where the average output voltages of the pixels with the white pattern and the
pixels with the black pattern are respectively denoted by VW and VB when a black and white stripe pattern (in which the
black and white patterns alternate at every pixel) is projected on the photodetector region in phase (equivalent to the
Nyquist spatial frequency).
V –V
V +V
W
W
B
B
Pattern on
photodetector
MTFR =
×100 (%)
This value is a measure of resolution of the sensor.
This parameter is not a guaranteed value but is
merely a reference value.
Zero
level
Output waveform
of CCD
V
B
V
W
MN3665A
CCD Linear Image Sensor
■ Pin Descriptions
Pin No.
1
Symbol
OS1
DS1
OG
Pin name
Condition
Odd-number pixel output
Signal output 1
2
Compensation output 1
Output gate
3
4
øR1
Reset clock
5
ø2D
CCD shift register clock
CCD shift register clock
Ground
6
ø1D
7
V
SS
8
ø1A
ø2A
TG
PG
øSG
IS
CCD shift register clock
CCD shift register clock
Test pin
Internally connected to ø1D
Internally connected to ø2D
Connect externally to VSS.
.
.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Photo storage gate
Shift clock gate
Connect externally to VDD
.
Test pin
Internally connected to ø2C
Internally connected to ø1C
.
.
ø2B
ø1B
ø SUB
CCD shift register clock
CCD shift register clock
Substrate
Connect externally to VDD
.
V
CCD shift register clock
CCD shift register clock
Reset clock
1C
ø2C
øR2
VDD
DS2
OS2
Power supply
Compensation output 2
Signal output 2
Even-number pixel output
■ Construction of the Image Sensor
c) Output region
The MN3665A can made up of into the three sections of—a)
photo detector region, b) CCD transfer region (shift register),
and c) output region.
• The signal charge that is transferred to the output region is
sent to the detector where impedance transformation is done
using two source follower stages.
a) Photo detector region
• The DC level component and the clock noise component not
containing optical signals are output from the DS pin.
• By carrying out differential amplification of the two outputs
OS and DS externally, it is possible to obtain an output signal
with a high S/N ratio by reducing the clock noise, etc.
• The photoelectric conversion device consists of a 5µm
floating photodiode and a 2µm channel stopper for each
pixel, and 10000 of these devices are linearly arranged side
by side at a pitch of 7µm.
• The photo detector's windows are 7µm × 7µm squares and
light incident on areas other than these windows is optically
shut out.
• The photo detector is provided with 32 optically shielded
pixels which serve as the black reference.
b) CCD Transfer region (shift register)
• The light output that has been photoelectrically converted is
transferred to the CCD transfer for each odd and even pixel at
the timing of the shift clock (øSG). The optical signal electric
charge transferred to this analog shift register is successively
transferred out and guided to the output region.
• A buried type CCD that can be driven by a two phase clock
(ø1, ø2) is used for the analog shift register.
MN3665A
CCD Linear Image Sensor
■ Timing Diagram
(1) I/O timing
Integration Time (Tint.)
ø SG
ø 1
ø 2
ø R1
1
3
31 33 35 37 39 41
10033 10037
10035 10039
ø R2
2
4
30 32 34 36 38 40 42 10032 10036 10040
10034 10038
DS1
OS1
B
1
B
3
B29 B
31
D
1
D
3
1
3
5
9995 9997 9999
Blank feed level
DS2
OS2
B
2
B30 B
32
Note)
Repeat the transfer
pulses (ø1 , ø2) for
more than 5020
periods.
D
4
D
2
B1 to B32 :Black referrence pixels
2
4
9996 9998 10000
D1 to D4 :Dummy invalid pixels
90%
ø2
(ø1)
ø1
(2) Drive timing
10%
tCf
tCr
90%
50%
10%
(ø2)
tRS
tRW
tRh
90%
50%
10%
ø R1
(øR2)
tRr
tRf
tSr
tSf
90%
50%
10%
DS1
(DS2)
tOh
2T
tOS
øSG
Reference level
OS1
Effective signal
output period
50%
50%
(OS2)
ø1
tSs
tSh
tSW
■ Graphs and Characteristics
Photoelectric Conversion Characteristics
Spectral Response Characteristics
100
80
60
40
20
0
Characteristics under standard
operating condition
Light source: Daylight
Under standard
operating condition
10 3
fluorescent lamp
10 2
10
–1
10 –2
10
1
500
600
700
800
400
Wavelength (nm)
Exposure (lx· s)
MN3665A
CCD Linear Image Sensor
■ Drive Circuit Diagram (Digital Section)
R12
330Ω
DS0026CN × 6
D1D2 D3
Q8 LS37
+12V
A
R1 1kΩ × 7
EXT
3
3
3
6
1
10DI × 3
3
2
1
7
7
2
ø2A
Q10
11
10
9
6
2
Q 15
Q1
1/2-
INT
4
1
100pF
× 7
C1
C2
C3
14
1
8
7
Q1 Q
Q8
Q8
R2
R3
8
12
11
8
1/2-
LS76
Q
C16
0.01µF
A
6
13
9
16 LS76
12
4
1
5
ø2B
ø1A
ø1B
Q11
3
8
Xtal-0SC.
6MHz
8
10 Q8
R4
R5
R6
4
A
6
6
6
2
1
5
Q7
LS04
Q7
5
C4
Q12
Q9
8
R13
330Ω
7
1
3
9
6
A
3
Q6
1/2
EXT
2
4
1
7
Q7
C5
C6
Q9
Q9
7
6
12
Q13
11
12 LS76
10
8
Q
13
11
INT
3
4
10
8
A
3
3
6
6
1
2
8
R9 10Ω
C
Q7
9
Q9
7
Q7
9
øR2
øR1
8
Q14
5
2200pF
4
10
R7
C7
10Ω
R10
A
2
1
3
7
Q7
øSG
R11 10Ω
14
2
1
3
2
1
3
9
6
9
6
1
3
2
9
1
2
9
Q15
15 R8
15
10
7
15
10
15 10
7
10
Q2
LS161
Q4
LS161
Q3
Q5
LS161
330Ω
R22
7
7
TRIGGER
+5V
LS161
R15
R18 R19
6
5
4
5
6
3
5
4
4
5
4
C18
470pF
15µF
C17
0.01µF
C
8
R14
330Ω
R17 R20
R16
R21
4
1
2
3
1
2
3
4
Connect a 0.01µF capacitor between the VCC
and GND pins of each TTL IC (C19 to C27).
4.7kΩ
× 2
4.7kΩ × 2
4.7kΩ
× 4
stands for the following circuit.
A
Q17
Q16
(R23 to R28)
10Ω
15µF (C62 to C67)
0.01µF
(C to C15)
11
■ Drive Circuit Diagram (Analog Section)
15µF
R43
C
100Ω
C43
38
15µF
C44
0.01µF
R36
100Ω
Q18
R29
R30
7.5kΩ
+12V
GND
C39
R47
100Ω
0.01µF
2SC828A
R40
+ 10Ω
C29
15µF
+
C
15
µF
R31
4.7kΩ
+
33
R34
C
C45
0.2081µF
C31
15µF
1kΩ
R45
6.8kΩ
100Ω
C32
0.01µF
C30
0.01µF
R37
1kΩ
1
Q21
C42
R41
–
7
8
9
2SC828A
R46
11
øR1
ø1A
ø1A
R38
1kΩ
Q19
LH0032CG
3
VIDEO
OUTPUT2
6.8kΩ
R42
100Ω
+
2
C46
5p
R35
1kΩ
R48
1kΩ
11 10
9 8 7 6 5 4 3 2 1
R1
2SC828A
C40
C47
100Ω
PG
2A 1A SS 1D 2D ø OG DS1 OS1
TG
C
48
+
R39
100Ω
15µF
0.01µF
MN3665A
ø R2
C49
R44
100Ω
GND
0.01µF
SG IS 2B 1B SUB1C 2C
12 13 14 15 16 17 18 19 20 21 22
DD DS2 OS2
C41
15µF
øSG
ø2B
ø1B
øR2
R 32
The circuit configuration of this part is
the same as the OS1 side amplifier.
+
VIDEO
OUTPUT2
C35
15µF
10Ω
C34
0.01µF
R33
–12V
(R49—R63,C50—C61,Q22—Q25)
+
C37
15µF
10Ω
C36
0.01µF
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