MN3671RE [PANASONIC]
CCD Sensor, 0.80-1.20V, Rectangular, Through Hole Mount, DIP-22;
| 型号： | MN3671RE |
| 厂家： | 
PANASONIC |
| 描述： | CCD Sensor, 0.80-1.20V, Rectangular, Through Hole Mount, DIP-22 CD 传感器 换能器 |
| 文件： | 总6页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CCD Linear Image Sensor
MN3671RE
Color CCD Linear Image Sensor
with 1024 Pixels for R and B Colors/2048 Pixels for G Color
■ Overview
■ Pin Assignments
The MN3671RE is a high responsivity CCD color linear image
sensor with 1024 pixels each for R and B and 2048 G pixels, and
having low dark output floating photodiodes in the photodetector
region and CCD analog shift registers for read out.
◆ identifies
the pin 1 position.
1
It can read a B4 size color document with a high quality and a
maximum pseudo resolution of 200dpi. In addition to being used as a
color sensor, this device can also be used as a black and white sensor
if only the G row is used, and in this case, it is possible to read a B4
size document with a full resolution of 200dpi. Since a one line delay
analog memory is built in so as to compensate for the difference in
the positions of reading out between the R, B rows and the G row, the
configuration of the signal processing circuit becomes simpler.
OS1
DS1
VSS
ø R
NC
NC
VSUB
ø 1
1
2
3
4
5
6
7
8
9
22
21
20
19
18
17
16
15
14
13
12
OS2
DS2
OG
VDD
NC
NC
VSUB
ø 2
ø SG1
VSS
V
SS
ø SG2
ø V
V
SS
10
11
■ Features
• 4096 floating photodiodes and n-channel buried type CCD shift
registers for read out are integrated in a single chip.
2048
It is possible to read a B4 size color document with a high pseudo
resolution of 200dpi.
•
•
•
(Top View)
RGB primary colors type on chip color filters are used for color
separation.
C21
WDIP022-G-0450
In order to compensate for the distance between the photodiode
rows for the R, B colors and the G color, the device has a built-in
analog memory that can store the signals of one line of the R-B
colors row.
■ Application
• Graphic and character read out in fax machines,
image scanners, etc.
• Use of photodiodes with a new structure has made the dark output
voltage very low.
• Large signal output of typically 1.2V at saturation can be obtained.
MN3671RE
CCD Linear Image Sensor
■ Block Diagram
OS2 DS2
22 21
VSS
ø2 øSG2 øV
OG VDD
20 19
VSUB
16
15 14
13 12
1
2
2
2
2
2
2
2
2
2
2 2 2 2
1 1 1 1 1
1
1
1
1
1
1
1
1
1
1-line delay analog memory
R
B
B2
B32 D2 D4 R1 B1 R2
B31 D1 D3 G1 G2 G3
1024 1024 D6 D8
B4
G
G
B1 B3
D7
2047 2048 D5
2
2
2
2
2
2
2
2
2
2
2 2 2
1 1 1
1
1
1
1
1
1
1
1
1
1
1
B1 to B32 : Black reference pixels
D1 to D 8 : Dummy invalid pixels
1
11
1
2
3
4
7
8
9
10
OS1 DS1 V
øR
VSUB
ø1 øSG1 VSS VSS
SS
■ Absolute Maximum Ratings (Ta=25˚C, VSS=0V)
Parameter
Symbol
VDD
Rating
Unit
– 0.3 to +17
– 0.3 to +17
– 0.3 to +17
– 0.3 to +17
0 to + 60
V
V
Power supply voltage
VOG
VI
Input voltage
V
Output voltage
VO
Topr
Tstg
V
Operating temperature range
Storage temperature range
˚C
˚C
–25 to + 85
■ Operating Conditions
Voltage conditions (Ta=0 to + 60˚C)
•
Parameter
Symbol
VDD
Condition
min
typ
12.0
12.0
4.5
max
13.0
13.0
4.8
Unit
V
Power supply voltage
Substrate voltage
11.5
11.5
4.2
Vsub
VOG
VVH
VVL
Vø H
Vø L
VSH
VSL
VRH
VRL
V
sub =VDD
V
Output gate voltage
VDD
øV
=
12.0V
V
VDD –1 VDD
0.5
VDD –1 VDD
0.5
VDD –1 VDD
0.5
VDD –1 VDD
0.5
VDD
0.8
Vertical transfer clock High level
Vertical transfer clock Low level
CCD shift register clock High level
CCD shift register clock Low level
Shift gate clock High level
V
V
V
V
V
V
V
V
øV
0
ø1 , ø2
VDD
0.8
0
ø1 , ø2
VDD
0.8
øSG1, øSG2
Shift gate clock Low level
0
øSG1, øSG2
øR
Reset gate clock High level
VDD
0.8
Reset gate clock Low level
0
øR
MN3671RE
CCD Linear Image Sensor
■ Operating Conditions (continued)
Timing conditions (Ta=0 to + 60˚C)
•
Parameter
Symbol
fC
Condition
min
0.1
0.1
0
typ
1.0
1.0
20
20
15
15
10
max
3.0
3.0
50
Unit
MHz
MHz
ns
Shift register clock frequency
Reset clock frequency
fC =1/2T
fR =1/2T
fR
tCr
Shift register clock rise time
Shift register clock fall time
Shift clock 1 rise time
0
50
ns
tCf
tSG1r
tSG1f
tSG1w
tVr
0
50
ns
0
50
Shift clock 1 fall time
ns
5
50
µs
Shift clock 1 pulse width
Vertical transfer clock rise time
Vertical transfer clock fall time
Vertical transfer clock set up time
Vertical transfer clock pulse width
Vertical transfer clock hold time
Shift clock 2 rise time
ns
0
0
15
15
50
50
2.0
50
2.0
50
50
2.0
50
20
20
—
tVf
ns
µs
tVs
øSG1 and øV should be the same timing.
0.5
5
1.0
10
tVw
µs
tVh
µs
0
1.0
15
tSG2r
tSG2f
tSG2s
tSG2w
ns
0
ns
Shift clock 2 fall time
0
15
µs
Shift clock 2 set up time
Shift clock 2 pulse width
Reset clock rise time
0.5
5
1.0
10
µs
0
10
ns
ns
ns
ns
ns
tRr
tRf
0
10
Reset clock fall time
tRs
tRw
tRh
0.7T
50
10
—
Reset clock set up time
Reset clock pulse width
Reset clock hold time
100
20
—
—
■ Electrical Characteristics
Clock input capacitance (Ta=0 to + 60˚C)
•
Parameter
Symbol
C1 , C2
Condition
min
—
typ
max
—
Unit
pF
CCD Shift register clock input capacitance
400
VIN =12V
f=1MHz
CV
CRS
Vertical transfer clock input capacitance
Reset clock input capacitance
Shift clock input capacitance
100
20
pF
pF
pF
—
—
—
—
—
—
CSG1, CSG2
150
DC characteristics
•
Parameter
Symbol
IDD
Condition
Condition
min
—
typ
20
max
50
Unit
mA
Power supply current
VDD = +12V
AC characteristics
•
Parameter
Symbol
tOS
min
—
typ
50
max
—
Unit
ns
Signal output delay time
■ Optical Characteristics
<Inspection conditions>
• Ta=25˚C, VDD=12V, VøH=VVH=VSH=VRH=12V (pulse), fC=fR=1MHz, Tint (accumulation time)=10ms
• Light source: Daylight type fluorescent lamp with IR/UV cutting filter
•
Optical system: A slit with an aperture dimensions of 20mm
• Load resistance = 100k Ohms
• These specifications apply to the 1024 valid R and B pixels and the 2048 valid G pixels excluding the dummy pixels D1 to D8.
× 20mm is used at a distance of 200mm from the sensor (equivalent to F=10).
MN3671RE
CCD Linear Image Sensor
■ Optical Characteristics (continued)
Parameter
Symbol
RR
Condition
min
0.5
0.9
0.5
—
typ
0.7
1.2
0.8
5
max
0.9
Unit
Note 1
Note 1
Note 1
Note 2
Note 3
Note 4
Note 4
Note 4
RG
Responsivity
1.5 V/lx · s
1.1
RB
%
PRNU
Photo response non-uniformity
Saturation output voltage
15
0.8
0.89
0.53
0.73
—
1.2
1.71
1.00
1.50
0.5
1.0
0.1
0.2
—
V
VSAT
SER
—
—
SEG
lx · s
—
Saturation exposure
SEB
—
VDRK1
VDRK2
DSNU1
DSNU2
STTE
DR
OS1 , Dark condition, see Note 5
OS2 , Dark condition, see Note 5
OS1 , Dark condition, see Note 6
OS2 , Dark condition, see Note 6
1.0
mV
Dark signal output voltage
—
2.0
—
2.0
mV
Dark signal output non-uniformity
—
4.0
%
Shift register total transfer efficiency
Dynamic range
92
—
Note 7
—
1200
—
Note 1) Responsivity (R)
This is the value obtained by dividing the average output voltage (V) of the all pixels by the exposure (lx·s).
The exposure (lx·s) is the product of the illumination intensity (lx) and the accumulation time (s).
Since the responsivity changes with the spectral distribution of the light source used, care should be taken when using a
light source other than the daylight type fluorescent lamp specified in the inspection conditions.
Note 2) Photo response non-uniformity (PRNU)
This is defined by the following equation where Xave is the average output voltage of the valid pixels of each of the colors
R, G, and B, and ∆x is the difference between the output voltage of the maximum (or minimum) output pixel and Xave
,
when the photodetector region is illuminated with light of a uniform illumination intensity distribution.
x
Xave
×100 (%)
PRNU=
The incident light intensity shall be 50% of the standard saturation llight intensity.
Note 3) Saturation output voltage (VSAT
)
This is the output voltage at the point beyond which it is not possible to maintain the linearity of the photoelectric
conversion characteristics as the exposure is increased. (The exposure at this point is called the saturation exposure.)
Note 4) Saturation Exposure (SE)
This is the exposure beyond which it is not possible to maintain the linearity of the output voltage as the exposure is
increased. When designing the equipment using these devices, make sure that the incident light exposure is set with
sufficient margin so that the CCD never gets saturated.
Note 5) Dark signal output voltage (VDRK
)
This is defined as the average of the output from all the valid pixels in the dark condition at Ta=25˚C, T =10ms.
int
Normally, the dark signal output voltage gets doubled for every 8 to 10˚C increase in Ta and is proportional to Tint. The
dark signal output voltage (VDRK2) on the OS2 side will be larger than the dark signal output voltage (VDRK1) on the OS1
side because there is a delay memory on the OS2 side.
Note 6) Dark signal non-uniformity (DSNU)
This is defined as the difference between the maximum value among the output voltages from the all active pixels at
Ta=25˚C and Tint=10ms and VDRK
.
V
DRK
DSNU
Note 7) Dynamic range (DR)
This is defined by the following equation.
V
SAT
VDRK
DR=
Since the dark signal output voltage is proportional to the accumulation time, the dynamic range becomes wider when the
accumulation time is shorter.
MN3671RE
CCD Linear Image Sensor
■ Pin Descriptions
Pin No.
1
Symbol
OS1
DS1
VSS
Pin name
Signal output 1 (for G)
Compensation output 1 (for G)
Ground
Condition
2
3
4
øR
Reset clock
5
NC
Non connection
Connect externally to VSS.
Connect externally to VSS.
Should be left open or connected to VDD voltage.
6
NC
Non connection
7
V
Substrate
SUB
8
ø1
CCD shift register clock
Shift clock gate 1
Ground
9
øSG1
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
V
Ground
SS
V
Ground
SS
øV
Vertical transfer clock
Shift clock gate 2
CCD shift register clock
Subustrate
øSG2
ø2
VSUB
NC
NC
Should be left open or connected to VDD voltage.
Non connection
Connect externally to VSS.
Connect externally to VSS.
Non connection
Power supply
V
DD
OG
DS2
OS2
Output gate
Compensation output 2 (for R and B)
Signal output 2 (for R and B)
■ Construction of the Image Sensor
The MN3671RE can be made up of the three sections of—a)
photo detector region, b) CCD transfer region (shift register),
and c) output region.
photodetector window are optically shielded.
The photodetector region has a total of 32 optically
•
shielded
(black reference) pixels that can be used as the black level
reference, with 16 pixels each for the R-B row and the G
row.
a) Photo detector region
• The photoelectric conversion device consists of an 11µm
floating photodiode and a 3µm channel stopper (isolation
region) per pixel, and such pixels are arranged in a linear row
with a pitch of 14µm along the main scanning direction.
• The R-B row has 1024 pixels each of the red and blue colors
arranged alternatingly, and the G row has 2048 pixels. The
R-B row and G row are placed with a spacing of one line
(14µm) along the sideways scanning direction. The pixels of
the G row are displaced by half the pixel pitch (7µm) relative
to the pixels of the R-B row in the main scanning direction.
b) CCD Transfer region (shift register)
• The signal charges obtained by photoelectric conversion are
transferred to the CCD transfer regions of the respective
colors during the period when the shift gate (øSG) is at the
High level. The signal charges transferred to this analog shift
register are successively transferred to the output region.
• A buried type CCD that can be driven by a two phase clock
(ø1, ø2) is used for the analog shift register.
c) Output region
• The signal charge transferred to the output region is first sent
to the charge to voltage conversion region where it is
converted into a voltage level corresponding to the amount of
the signal charge, and then output after impedance
conversion in a two stage source follower amplifier.
1
1
2
2 · · · · · · 1024 1024
R
B
R
B
R
B
14µm
G G G G
G G
1
2
3
4 · · · · · · 2047 2048
The DC level component not containing the optical signal
and the clock noise component are output at the DS pin.
•
14µm
14µm 14µm
• A one line analog delay memory is built in the chip in order
to compensate for the difference in the positions of the R-B
and G rows in the sideways scanning direction.
It is possible to obtain a signal with a high S/N ratio
with
•
reduced clock noise, etc., by carrying out differential
amplification of the OS and DS outputs externally.
The photodetector window is a rectangle of dimensions 8 m
µ
•
(Horizontal) × 11µm (Vertical), and the areas other than the
MN3671RE
CCD Linear Image Sensor
■ Timing Diagram
(1) I/O timing
øSG1
øV
øSG2
ø1
ø2
øR
0
1
2
17 18 19 20 21 22
2065
2067 2069
2066 2028 2070
DS1
OS1
B1 B29 B31
D
1
D5
D7
D
3
G2048
G2 G3 G2045 G2047
G2046
Blank feed level
G
1
DS2
OS2
B
2
B30 B32
D2
D
4
D
D
8
6
B
B1024
R1024
1023
R1 B1 R2
R
1023
B to B32 : Black reference pixels
Note)
Repeat the transfer
pulses(ø1 , ø2) for
more than 2070
periods.
1
D to D8 : Dummy invalid pixels
1
* OS2 outputs the previous line signal.
(2) Drive timing
90%
10%
ø 2
tCr
ø 1
tCf
90%
50%
10%
tRS
tRW
tRh
90%
50%
10%
ø R
tRr
tRf
DS1
(DS2)
tOS
tOh
2T
Reference level
50%
OS1
(OS2)
Effecitve signal
output period
■ Graphs and Characteristics
Spectral Response Characteristics
100
80
60
40
20
0
Green
Red
Blue
500
600
700
800
400
Wavelength (nm)
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