SAA4992H [NXP]
Field and line rate converter with noise reduction; 场和线路速率转换器降噪
| 型号： | SAA4992H |
| 厂家： | 
NXP |
| 描述： | Field and line rate converter with noise reduction |
| 文件： | 总36页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA4992H
Field and line rate converter with
noise reduction
Product specification
2000 Feb 04
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAMS
3
4
5
6
PINNING
7
FUNCTIONAL DESCRIPTION
CONTROL REGISTER DESCRIPTION
LIMITING VALUES
8
9
10
11
12
13
13.1
THERMAL CHARACTERISTICS
CHARACTERISTICS
PACKAGE OUTLINE
SOLDERING
Introduction to soldering surface mount
packages
13.2
13.3
13.4
13.5
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
14
15
DEFINITIONS
LIFE SUPPORT APPLICATIONS
2000 Feb 04
2
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
1
FEATURES
2
GENERAL DESCRIPTION
• Upconversion of all 1fH film and video standards up to
292 active input lines per field
The SAA4992H is a completely digital monolithic
integrated circuit which can be used for field and line rate
conversion of all global TV standards.
• 100/120 Hz 2 : 1, 50/60 Hz 1 : 1 and 100/120 Hz 1 : 1
output formats
It features improved ‘Natural Motion’ performance and full
film upconversion for all 50 and 60 Hz film material.
• 4 : 1 : 1, 4 : 2 : 2 and 4 : 2 : 2 Differential Pulse Code
Modulation (DPCM) input colour formats; 4 : 1 : 1 and
4 : 2 : 2 output colour formats
It can be configured to emulate the SAA4990H as well as
the SAA4991WP. For demonstration purposes a split
screen mode to show the Dynamic Noise Reduction
(DNR) function and a colour vector overlay is available.
• Full 8-bit accuracy
• Scalable performance by applying 1, 2 or 3 external
field memories
The SAA4992H supports a Boundary Scan Test (BST)
circuit in accordance with IEEE 1149.
• Improved recursive de-interlacing
• Film (25 Hz, 30 Hz) upconversion to 100/120
movement phases per second
• Variable vertical sharpness enhancement
• Motion compensated 3D dynamic noise reduction
• High quality vertical zoom
• 2 Mbaud serial interface (SNERT).
3
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
3.0
TYP. MAX. UNIT
VDD
IDD
supply voltage
3.3
400
32
−
3.6
550
33.3
70
V
supply current
−
−
0
mA
MHz
°C
fCLK
operating clock frequency
ambient temperature
Tamb
4
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
SAA4992H
QFP160
plastic quad flat package; 160 leads (lead length 1.6 mm);
SOT322-2
body 28 × 28 × 3.4 mm; high stand-off height
2000 Feb 04
3
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a
FIELD MEMORY 2
YB7 to YB0
FIELD MEMORY 3
YD7 to YD0
YC0 to YC7
2 to 9
YE0 to YE7
122 to 129
151, 152,
111, 112,
154 to 159
114 to 119
COMPRESS
DECOMPRESS
45 to 52
DYNAMIC
NOISE
YA0 to YA7
REDUCTION
SEQUENCER
27
26
MUX
MUX
SNCL
SNDA
SNERT
INTERFACE
25
SAA4992H
SNRST
DE-INTERLACER
vectors
61 to 68
82 to 89
CONTROL
YF7 to YF0
YG7 to YG0
MPR
LEFT
VERTICAL
ZOOM
VERTICAL
MPR
PEAKING
RIGHT
35
34
33
32
31
30
SPM
TPM
ESM
TCK
TDO
TDI
MOTION ESTIMATOR
vectors
BST/TEST
TMS
TRST
TEST
UPCONVERSION
79
CLK32
MHB645
The solid lines represent pixel data; the broken lines represent controls.
Fig.1 Block diagram of the luminance part.
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g
FIELD MEMORY 2
FIELD MEMORY 3
UVB3 to UVB0
147 to 150
UVC0 to UVC3
10 to 13
UVD3 to UVD0
107 to 110
UVE0 to UVE3
130 to 133
COMPRESS/
FORMAT
DECOMPRESS/
REFORMAT
37 to 44
DECOMPRESS/
REFORMAT
UVA0 to UVA7
DNR
SAA4992H
vectors
MPR
LEFT
MPR
RIGHT
70 to 77
91 to 98
UPCONVERSION
FORMAT
UVF7 to YVF0
UVG7 to YVG0
VERTICAL
ZOOM
MHB646
The solid lines represent pixel data; the broken lines represent controls.
Fig.2 Block diagram of the chrominance part.
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
6
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION(1)(2)
VSSE
YC0
1
2
ground ground of output pads
input
input
input
input
input
input
input
input
input
input
input
input
bus C luminance input from field memory 2 bit 0 (LSB)
bus C luminance input from field memory 2 bit 1
bus C luminance input from field memory 2 bit 2
bus C luminance input from field memory 2 bit 3
bus C luminance input from field memory 2 bit 4
bus C luminance input from field memory 2 bit 5
bus C luminance input from field memory 2 bit 6
bus C luminance input from field memory 2 bit 7 (MSB)
bus C chrominance input from field memory 2 bit 0 (LSB)
bus C chrominance input from field memory 2 bit 1
bus C chrominance input from field memory 2 bit 2
bus C chrominance input from field memory 2 bit 3 (MSB)
YC1
3
YC2
4
YC3
5
YC4
6
YC5
7
YC6
8
YC7
9
UVC0
UVC1
UVC2
UVC3
REC
VSSE
VDDE
VSSI
10
11
12
13
14
15
16
17
18
19
output read enable output for bus C
ground ground of output pads
supply supply voltage of output pads
ground core ground
VDDI
supply core supply voltage
JUMP0
input
configuration pin 0; will be stored in register 0B3 e.g. to indicate presence of 3rd field
memory; should be connected to ground or to VDDI via pull-up resistor; note 3
JUMP1
20
input
configuration pin 1; will be stored in register 0B5 e.g. to indicate presence of 16-bit
1st field memory for full 4 : 2 : 2; should be connected to ground or to VDDI via
pull-up resistor; note 3
VDDE
21
22
23
24
25
26
27
28
29
30
31
supply supply voltage of output pads
supply core supply voltage
ground core ground
VDDI
VSSI
RAMTST1
SNRST
SNDA
SNCL
VSSE
input
input
I/O
test pin 1 for internal RAM testing; connect to ground for normal operation
SNERT bus reset
SNERT bus data
SNERT bus clock
input
ground ground of output pads
RAMTST2
TEST
input
input
input
test pin 2 for internal RAM testing; connect to ground for normal operation
test mode input; if not used it has to be connected to ground
TRST
boundary scan test: reset input signal; if not used it has to be connected to ground via
pull-down resistor; note 3
TMS
TDI
32
33
34
input
input
boundary scan test: test mode select; if not used it has to be connected to VDDI via
pull-up resistor; note 3
boundary scan test: data input signal; if not used it has to be connected to VDDI via
pull-up resistor; note 3
TDO
output boundary scan test: data output signal
2000 Feb 04
6
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
SYMBOL
PIN
TYPE
DESCRIPTION(1)(2)
TCK
35
input
boundary scan test: clock input signal; if not used it has to be connected to VDDI via
pull-up resistor; note 3
VSSE
UVA0
UVA1
UVA2
UVA3
UVA4
UVA5
UVA6
UVA7
YA0
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
ground ground of output pads
bus A chrominance input from field memory 1 bit 0 (LSB)
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
bus A chrominance input from field memory 1 bit 1
bus A chrominance input from field memory 1 bit 2
bus A chrominance input from field memory 1 bit 3
bus A chrominance input from field memory 1 bit 4
bus A chrominance input from field memory 1 bit 5
bus A chrominance input from field memory 1 bit 6
bus A chrominance input from field memory 1 bit 7 (MSB)
bus A luminance input from field memory 1 bit 0 (LSB)
bus A luminance input from field memory 1 bit 1
bus A luminance input from field memory 1 bit 2
bus A luminance input from field memory 1 bit 3
bus A luminance input from field memory 1 bit 4
bus A luminance input from field memory 1 bit 5
bus A luminance input from field memory 1 bit 6
bus A luminance input from field memory 1 bit 7 (MSB)
YA1
YA2
YA3
YA4
YA5
YA6
YA7
REA
VSSE
VSSI
output read enable output for bus A
ground ground of output pads
ground core ground
VDDI
VDDI
VSSI
supply core supply voltage
supply core supply voltage
ground core ground
VSSE
REF
YF7
ground ground of output pads
input
read enable input for bus F and G
output bus F luminance output bit 7 (MSB)
output bus F luminance output bit 6
output bus F luminance output bit 5
output bus F luminance output bit 4
output bus F luminance output bit 3
output bus F luminance output bit 2
output bus F luminance output bit 1
output bus F luminance output bit 0 (LSB)
supply supply voltage of output pads
output bus F chrominance output bit 7 (MSB)
output bus F chrominance output bit 6
output bus F chrominance output bit 5
output bus F chrominance output bit 4
output bus F chrominance output bit 3
YF6
YF5
YF4
YF3
YF2
YF1
YF0
VDDE
UVF7
UVF6
UVF5
UVF4
UVF3
2000 Feb 04
7
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
SYMBOL
PIN
TYPE
DESCRIPTION(1)(2)
UVF2
UVF1
UVF0
VSSE
CLK32
VSSI
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
output bus F chrominance output bit 2
output bus F chrominance output bit 1
output bus F chrominance output bit 0 (LSB)
ground ground of output pads
input
system clock input
ground core ground
VSSE
YG7
ground ground of output pads
output bus G luminance output bit 7 (MSB)
output bus G luminance output bit 6
output bus G luminance output bit 5
output bus G luminance output bit 4
output bus G luminance output bit 3
output bus G luminance output bit 2
output bus G luminance output bit 1
output bus G luminance output bit 0 (LSB)
supply supply voltage of output pads
output bus G chrominance output bit 7 (MSB)
output bus G chrominance output bit 6
output bus G chrominance output bit 5
output bus G chrominance output bit 4
output bus G chrominance output bit 3
output bus G chrominance output bit 2
output bus G chrominance output bit 1
output bus G chrominance output bit 0 (LSB)
ground ground of output pads
YG6
YG5
YG4
YG3
YG2
YG1
YG0
VDDE
UVG7
UVG6
UVG5
UVG4
UVG3
UVG2
UVG1
UVG0
VSSE
VSSI
100 ground core ground
VDDI
101 supply core supply voltage
VDDE
VDDI
102 supply supply voltage of output pads
103 supply core supply voltage
VSSI
104 ground core ground
VSSE
WED
UVD3
UVD2
UVD1
UVD0
YD7
105 ground ground of output pads
106 output write enable output for bus D
107 output bus D chrominance output to field memory 3 bit 3 (MSB)
108 output bus D chrominance output to field memory 3 bit 2
109 output bus D chrominance output to field memory 3 bit 1
110 output bus D chrominance output to field memory 3 bit 0 (LSB)
111 output bus D luminance output to field memory 3 bit 7 (MSB)
112 output bus D luminance output to field memory 3 bit 6
113 supply supply voltage of output pads
YD6
VDDE
YD5
114 output bus D luminance output to field memory 3 bit 5
115 output bus D luminance output to field memory 3 bit 4
YD4
2000 Feb 04
8
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
SYMBOL
PIN
TYPE
DESCRIPTION(1)(2)
YD3
YD2
YD1
YD0
VSSE
VSSE
YE0
YE1
YE2
YE3
YE4
YE5
YE6
YE7
UVE0
UVE1
UVE2
UVE3
REE
VSSE
n.c.
116 output bus D luminance output to field memory 3 bit 3
117 output bus D luminance output to field memory 3 bit 2
118 output bus D luminance output to field memory 3 bit 1
119 output bus D luminance output to field memory 3 bit 0 (LSB)
120 ground ground of output pads
121 ground ground of output pads
122 input
123 input
124 input
125 input
126 input
127 input
128 input
129 input
130 input
131 input
132 input
133 input
bus E luminance input from field memory 3 bit 0 (LSB)
bus E luminance input from field memory 3 bit 1
bus E luminance input from field memory 3 bit 2
bus E luminance input from field memory 3 bit 3
bus E luminance input from field memory 3 bit 4
bus E luminance input from field memory 3 bit 5
bus E luminance input from field memory 3 bit 6
bus E luminance input from field memory 3 bit 7 (MSB)
bus E chrominance input from field memory 3 bit 0 (LSB)
bus E chrominance input from field memory 3 bit 1
bus E chrominance input from field memory 3 bit 2
bus E chrominance input from field memory 3 bit 3 (MSB)
134 output read enable output for bus E
135 ground ground of output pads
136
−
not connected
VSSI
137 ground core ground
VDDI
n.c.
138 supply core supply voltage
139
140
−
−
not connected
not connected
n.c.
VDDE
VDDI
VSSI
141 supply supply voltage of output pads
142 supply core supply voltage
143 ground core ground
n.c.
144
−
not connected
VSSE
WEB
UVB3
UVB2
UVB1
UVB0
YB7
YB6
VDDE
YB5
YB4
YB3
145 ground ground of output pads
146 output write enable output for bus B
147 output bus B chrominance output to field memory 2 bit 3 (MSB)
148 output bus B chrominance output to field memory 2 bit 2
149 output bus B chrominance output to field memory 2 bit 1
150 output bus B chrominance output to field memory 2 bit 0 (LSB)
151 output bus B luminance output to field memory 2 bit 7 (MSB)
152 output bus B luminance output to field memory 2 bit 6
153 supply supply voltage of output pads
154 output bus B luminance output to field memory 2 bit 5
155 output bus B luminance output to field memory 2 bit 4
156 output bus B luminance output to field memory 2 bit 3
2000 Feb 04
9
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
SYMBOL
PIN
TYPE
DESCRIPTION(1)(2)
YB2
YB1
YB0
VSSE
157 output bus B luminance output to field memory 2 bit 2
158 output bus B luminance output to field memory 2 bit 1
159 output bus B luminance output to field memory 2 bit 0 (LSB)
160 ground ground of output pads
Notes
1. Not used input pins (e.g. bus E) should be connected to ground.
2. Because of the noisy characteristic of the output pad supply it is recommended not to connect the core supply and
the output pad supply directly at the device. The output pad supply should be buffered as close as possible to the
device.
3. The external pull-up resistor should be 47 kΩ.
2000 Feb 04
10
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
V
V
SSE
1
2
3
4
5
6
7
8
9
120
SSE
YC0
119 YD0
118 YD1
117 YD2
116 YD3
115 YD4
114 YD5
YC1
YC2
YC3
YC4
YC5
YC6
YC7
V
113
DDE
112 YD6
UVC0 10
UVC1 11
UVC2 12
UVC3 13
REC 14
111 YD7
110 UVD0
109 UVD1
108 UVD2
107 UVD3
106 WED
V
V
15
16
17
18
SSE
V
V
V
V
V
V
V
105
104
103
102
101
100
99
DDE
SSE
SSI
V
SSI
DDI
V
DDI
DDE
DDI
SSI
JUMP0 19
JUMP1 20
SAA4992H
V
21
22
23
DDE
V
DDI
SSE
V
98 UVG0
97 UVG1
96 UVG2
95 UVG3
94 UVG4
93 UVG5
92 UVG6
91 UVG7
SSI
RAMTST1 24
SNRST 25
SNDA 26
SNCL 27
V
28
SSE
RAMTST2 29
TEST 30
TRST 31
TMS 32
TDI 33
V
90
DDE
89 YG0
88 YG1
87 YG2
86 YG3
85 YG4
84 YG5
83 YG6
82 YG7
TDO 34
TCK 35
V
36
SSE
UVA0 37
UVA1 38
UVA2 39
UVA3 40
V
81
SSE
MHB647
Fig.3 Pin configuration.
2000 Feb 04
11
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
7
FUNCTIONAL DESCRIPTION
Table 1 Clock cycle references
The FAL (fal_top) module builds the functional top level of
the SAA4992H. It connects the luminance data path (KER,
kernel), the chrominance data path (COL, colour) and the
luminance (de)compression (YDP, Y-DPCM) with
SAA4992H inputs and outputs as well as controlling logic
(LSE, line sequencer; SNE, SNERT interface). Outside of
fal_top there are only the pad cells, boundary scan test
cells, the boundary scan test controller, the clock tree, the
test enable tree and the input port registers.
SIGNAL
LATENCY
RE_F
0
RE_C and
RE_E
63 cycles + REceShift
YC, YE, UVC
and UVE
63 cycles
RE_A
94 cycles + REaShift
94 cycles
YA and UVA
Figure 4 shows a simplified block diagram of fal_top. It
displays the flow of pixel data (solid lines) and controls
(broken lines) between the modules inside.
YF, YG, UVF
and UVG
148 cycles + 3 input lines
WE_B and
WE_D
160 cycles + 4 input lines + WEbdShift
160 cycles + 4 input lines
Basic functionality of the modules in fal_top is as follows:
• KER (kernel): Y (luminance) data path
YB, YD, UVB
and UVD
• COL (colour): UV (chrominance) data path
• YDP (Y-DPCM): compression (and decompression) of
luminance output (and input) data by Differential Pulse
Code Modulation (DPCM)
There is an algorithmic delay of 3 lines between input and
output data. Therefore, the main data output on the
F and G bus begins while the fourth input line is read.
Writing to the B and D bus starts one input line later.
The read and write enable signals RE_A, WE_B, RE_C,
WE_D and RE_E can be shifted by control registers
REaShift, WEbdShift and REceShift, which are
implemented in the line sequencer.
• LSE (line sequencer): generate line frequent control
signals
• SNE: Synchronous No parity Eight bit Reception and
Transmission (SNERT) interface to a microcontroller.
The SNERT interface operates in a slave receive and
transmit mode for communication with a microprocessor,
which resides on peripheral circuits (e.g. SAA4978H)
together with a SNERT master. The SNERT interface
transforms serial data from the microprocessor (via the
SNERT bus) into parallel data to be written into the
SAA4992Hs write registers and parallel data from
SAA4992Hs read registers into serial data to be sent to the
microprocessor. The SNERT bus consists of 3 signals:
The fal_top module itself reads the following control
register bits(addresses):
• NrofFMs (017)
• MatrixOn (026)
• MemComp and MemDecom (026).
NrofFMs and MatrixOn are used to enable the D and G
output bus, respectively. MemComp and MemDecom are
connected to YDP to control luminance data compression
and decompression. These control register signals are not
displayed in Fig.4. Further information on the control
registers is given in Chapter 8.
1. SNCL: used as serial clock signal, generated by the
master
2. SNDA: used as bidirectional data line
3. SNRST: used as a reset signal, generated by the
microprocessor to indicate the start of a transmission.
The processing of a video field begins on the rising edge
of the RE_F input signal. As indicated in Fig.4, the
SAA4992H expects its inputs and generates its outputs at
the following clock cycles after RE_F (see Table 1).
2000 Feb 04
12
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
external field memories
WE_B,
WE_D
RE_C,
RE_W
UVB,
UVD
UVC,
UVE
YB,
YD
YC,
YE
160
cycles
63
cycles
160
63
160
63
cycles cycles cycles cycles
fal_top
UVA
94 cycles
YDP
COL
UVF, UVG
148 cycles
SNDA
SNE
LSE
RE_A
RE_F
94 cycles
0 cycles
YF, YG
148 cycles
KER
YA
94 cycles
MHB648
The solid lines represent pixel data; the broken lines represent controls.
Fig.4 Block diagram of fal_top.
2000 Feb 04
13
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8
CONTROL REGISTER DESCRIPTION
SNERT
ADDRESS
HEX
READ/
WRITE(1)
NAME
7
6
5
4
3
2
1
0
DESCRIPTION(2)
DNR/peaking/colour
Kstep10
Kstep0
Kstep1
Kstep32
Kstep2
Kstep3
Kstep54
Kstep4
Kstep5
Kstep76
Kstep6
010
011
012
013
write; S
write; S
write; S
write; S
X X X X set LUT value: k = 1⁄16 if difference below (0 to 15)
set LUT value: k = 1⁄8 if difference below (0 to 15)
X X X X
X X X X
X X X X
X X X X set LUT value: k = 2⁄8 if difference below (0 to 30 in multiples of 2)
set LUT value: k = 3⁄8 if difference below (0 to 30 in multiples of 2)
X X X X set LUT value: k = 4⁄8 if difference below (0 to 60 in multiples of 4)
set LUT value: k = 5⁄8 if difference below (0 to 60 in multiples of 4)
X X X X set LUT value: k = 6⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,
64, 72, 80, 88, 96, 104, 112 or 120)
Kstep7
X X X X
set LUT value: k = 7⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,
64, 72, 80, 88, 96, 104, 112 or 120)
Gain_fix_y
014
015
016
write; S
write; S
write; S
FixvalY
X X X X set fixed Y value; used when FixY = 1 or in left part of split screen
(0, 1⁄16 to 14 16 or 16⁄16)
⁄
GainY
FixY
X X X
X
set gain in difference signal for adaptive DNR Y (1⁄8, 1⁄4, 1⁄2, 1, 2 or 4)
select fixed Y (adaptive or fixed) (full screen)
Gain_fix_uv
FixvalUV
X X X X set fixed UV value; used when FixUV = 1 or in left part of split screen
(0, 1⁄16 to 14 16 or 16⁄16)
⁄
GainUV
FixUV
X X X
X
set gain in difference signal for adaptive DNR UV (1⁄8, 1⁄4, 1⁄2, 1, 2 or 4)
select fixed UV (adaptive or fixed) (full screen)
Peak_Vcomp
VecComp
X X X set degree of horizontal vector compensation in Y DNR:
(0, 1⁄8, 2⁄8, 3⁄8, 4⁄8, 5⁄8, 6⁄8 or 7⁄8) of the vector
PeakCoef
X X X X
set vertical peaking level: (0, +2, +3.5, +5, +6, x, x, x, x, x, x, x, x,
−12, −6 or −2.5) dB
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NAME
ADDRESS
HEX
7
6
5
4
3
2
1
0
DESCRIPTION(2)
WRITE(1)
DNR_Colour_mode
017
write; S
ColourIn
X X select colour input format: (4 : 1 : 1, 4 : 2 : 2, 4 : 2 : 2 DPCM or
4 : 2 : 2)
ColourOut
NrofFMs
ColOvl
X
select colour output format: (4 : 1 : 1 or 4 : 2 : 2)
set number of field memories connected: (1 or 2/3)
X
X
select vector overlay on colour output: (vector overlay or colour
from video path)
SlaveUVtoY
DnrSplit
X
slave UV noise reduction to K factor of Y: (separate or slaved)
select split screen mode for DNR: (normal or split screen)
X
DnrHpon
X
switch DNR high-pass on (DNR only active on low frequent spectrum:
(all through DNR or high bypassed)
Vertical zoom
Zoom1
018
write; F
ZoomSt98
X X zoom line step bits 9 and 8; line step = vertical distance between
successive output lines; usable range = 0 to 2 frame lines;
resolution 1⁄256 frame line
ZoomPo98
X X
zoom start position bits 9 and 8; start position = vertical position of the
top display line; usable range = 1 to 3 frame lines; resolution 1⁄256
frame line
Zoom2
019
01A
01B
write; F
write; F
write; F
ZoomSt70
Zoom3
X X X X X X X X zoom line step bits 7 to 0 (see above)
X X X X X X X X zoom start position bits 7 to 0 (see above)
ZoomPo70
Zoom4
ZoomEnVal
X X X X zoom run in value = number of lines without zoom active
(0 to 15 lines)
ZoomDiVal
X X X X
zoom run out value = number of lines without zoom active
(−8 to +7 lines)
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NAME
ADDRESS
HEX
7
6
5
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0
DESCRIPTION(2)
WRITE(1)
De-interlacer
Proscan1
01C
write; S
KlfLim
X X X X limitation of recursion factor in calculation of original line positions:
(1 to 16); 1 limits to almost full recursion, 16 limits to no recursion
KlfOfs
X X X X
The transfer curve of the de-interlacing filter coefficient is determined
by the difference (Diff) between a line in the input field and the
counterpart in the previous field shifted over the estimated motion
vector. KlfOfs determines the bias of the transfer curve for the original
input line, such that coefficient = KlfOfs + F(Diff), where the function F
is calculated in the SAA4992H. The bias can take a value in the range
(0 to 15), representing decreasing filter strength.
Proscan2
01D
01E
write; S
write; S
PlfLim
X X X X limitation of recursion factor in calculation of interpolated line
positions: (1 to 16); 1 limits to almost full recursion, 16 limits to no
recursion
PlfOfs
Proscan3
PeakLim
X X X X
see KlfOfs; this offset applies to interpolated lines
X X X X Maximum that the peaked pixel is allowed to deviate from original pixel
value: deviation (0 to 30 in steps of 2). Above this deviation, the
peaked pixel is clipped to (original pixel + or − PeakLim).
PenInd
X X X X
index to PenMed table (−256, −128, −64, −32, −16, −8, −4, 0, 4, 8, 16,
24, 32, 64, 128 or 255); penalty for applying (vertical/temporal)
median, in favour of applying vertical average within new field
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NAME
Proscan4
ADDRESS
HEX
7
6
5
4
3
2
1
0
DESCRIPTION(2)
WRITE(1)
01F
write; F
PlfThr
X X X Multiplier threshold at which to switch the lower limit of the filter
coefficient for interpolated lines. Above this threshold, the differences
corresponding to the two neighbouring lines are used as clipping
parameters, below this threshold, the interpolated line difference is
used as clipping level. This parameter can be used to optimize the
de-interlacing quality in slowly moving edges; it is not likely to have
effect if PlfLim is high.
ProDiv
X X
Scaling factor to control the strength of the filtering for the interpolated
lines. A value 0 means no scaling (normal filtering), while 3 means
scaling by factor 8 (very strong filtering). This parameter can be used
to adjust the de-interlacing to varying level of noise in the input picture;
use higher scaling for higher noise.
UseVec
KplOff
X
Enables use of estimated vectors to shift pixels from previous frame to
the current time (null vector or estimated vectors). It is best
switched to ‘null vector’, if vectors are unreliable.
X
disable all recursion in calculating pixels for frame memory (recursive
or non recursive); to be true SAA4991WP and digital scan emulation
modes
General
NrBlks
NrBlks
020
write; S
X X X X X X number of blocks in active video (6 to 53, corresponds to
96 to 848 pixels), to be set as 1⁄16 (number of active pixels per
line + 15); take remarks on TotalPxDiv8 into consideration
TotalLnsAct98
TotalLnsAct70
TotalPxDiv8
X X
total number of output lines (bits 9 and 8)
021
022
write; S
write; S
X X X X X X X X total number of output lines (bits 7 to 0)
X X X X X X X X Total number of pixels per line divided-by-8 (80 to 128, corresponds to
640 to 1024 pixels). The horizontal blanking interval is calculated as
TotalPxDiv8 − 2 × NrBlks and has to be in the range from 12 to 124
(corresponds to 96 to 992 pixels). Conclusion: TotalPxDiv8 has to be
set to 12 + 2 × NrBlks < TotalPxDiv8 < 124 + 2 × NrBlks and NrBlks
TotalPxDiv8 – 124
-----------------------------------------------
2
TotalPxDiv8 – 12
--------------------------------------------
2
has to be set to
< NrBlks <
REaShift
023
write; S
X X X shift of REa signal in number of pixels (0, +1, +2, +3, −4, −3, −2 or −1)
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NAME
ADDRESS
HEX
7
6
5
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0
DESCRIPTION(2)
WRITE(1)
WEbdREceShift
024
write; S
WEbdShift
X X X shift of WEb and WEd signal in number of pixels
(0, +1, +2, +3, −4, −3, −2 or −1)
REceShift
X X X
shift of REc and REe signal in number of pixels
(0, +1, +2, +3, −4, −3, −2 or −1)
POR
025
026
write; S
write; F
X power-on reset command, to be set high temporarily during start-up
(normal or reset); note 3
Mode control
Control1
EstMode
X Set estimator mode; 0 = line alternating use of left and right estimator:
use in progressive scan except with vertical compress. 1 = field
alternating use of left and right estimator: use in field doubling and
progressive scan with vertical compress.
FilmMode
UpcMode
X
set film mode; 0 = video camera mode; 1 = film mode
X X
select upconversion quality; 00 = full, 01 = economy (DPCM),
10 = SAA4991WP, 11 = SAA4990H
MatrixOn
X
set matrix output mode; 1 = double output, disabling vertical peaking;
0 = normal single output mode
EmbraceOn
X
Master enable for embrace mode (off or on); SwapMpr in control2
should be at ‘swap’ position to really cross-switch FM1 and FM3 field
outputs. Should be set to logic 0 except in film mode and FM3 is
present, or in SAA4991WP film mode and MemComp bit is active.
MemComp
X
set memory compression (luminance DPCM) (off or on)
set memory decompression (luminance DPCM) (off or on)
MemDecom
X
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Control2
ADDRESS
HEX
7
6
5
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3
2
1
0
DESCRIPTION(2)
WRITE(1)
027
write; F
QQcurr
X Quincunx phase of current field (in TPM) (phase0 or phase1); this
needs to toggle each time a new field comes from FM1. In phase0 the
estimator operates on a checker-board pattern that starts with the left
upper block; in phase1 the other blocks are estimated.
QQprev
FldStat
X
quincunx phase of previous field (in TPM) (phase0 or phase1); this is
the value of QQcur during the last estimate written into the temporal
prediction memory
X
Field status (same input field or new input field); reflects whether
the output of FM1 is a new or a repeated field. This bit will toggle field
by field in field doubling mode and is continuously HIGH in progressive
output mode.
FieldWeYUV
X
enable writing FM2 and FM3 for both luminance and chrominance
(recirculation of data for luminance alone can be controlled with
OrigFmEnY and IntpFmEnY in Control3) (off or on)
OddFM1
SwapMpr
X
odd input field (even or odd), this is to be set equal to the detected
field interlace for the field that comes out of FM1
X
Swap multi port RAMs (normal or swap); this bit needs to be set to
get real frame data at the temporal position from FM1. If swapped, the
current field (FM1) will be stored in the right line memory tree, while
the original lines from the stored frame (FM2/3) are stored in the left
memory tree. Should be set only in film mode if FM3 is present;
EmbraceOn must be set as well.
VecOffs
X X
Set vertical vector offset (0, +1, − or −1) frame lines; vertical offset of
the right line memory tree with respect to the left line memory tree.
A higher offset value means: on the right memory tree access to less
delayed video lines is taken; in interlaced video operation, the vertical
offset will be −1 with an odd field on the left side and +1 with an even
field on the left. With non-interlaced input, vertical offset should be
constantly 0. In film mode, vertical offset is dynamically switched
between +1, 0 and −1.
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NAME
Control3
ADDRESS
HEX
7
6
5
4
3
2
1
0
DESCRIPTION(2)
WRITE(1)
028
write; F
OddLeft
X interlace (even or odd) phase of the field which is written to the left
line memory tree (left MPRAM)
OrigFmEnY
X
enables writing luminance from de-interlacer in original field memory
(FM2), otherwise recirculation of luminance that is just read from FM2
(recirculate or update)
IntpFmEnY
FillTPM
X
enables writing luminance from de-interlacer in interpolated field
memory (FM3), otherwise recirculation of luminance that is just read
from FM3 (recirculate or update)
X
Enables writing in temporal prediction memory (keep or update);
FillTPM should be set to ‘keep’ in SAA4991WP/film mode, in those
output fields where FM1 and FM2 contain the same motion phase.
FillTPM should be set to ‘update’ in all other situations.
VertOffsDNR
X X
Set vertical vector offset of DNR (0, +1, − or −1) frame lines; vertical
offset of the right line memory tree with respect to the left line memory
tree, before the swap action. A higher offset value means: on the right
memory tree access to less delayed video lines is taken; in interlaced
video operation, the vertical offset will be −1 with an odd field on the
left side and +1 with an even field on the left. With non-interlaced
input, vertical offset should be constantly logic 0; in film mode, vertical
offset is dynamically switched between +1, 0 and −1. It should be
noted that the signal OddFM1 is used to determine this offset.
Upconversion
Upconv1
029
02A
write; F
UpcShFac
X X X X X X temporal interpolation factor used in luminance upconverter; value
ranges from 0 (for current field position) to 32 (for previous field
position)
Upconv2
write
S
YVecClip
X X X value used for coring the vertical vector component before application
in the upconverter; range: 0 to 3.5 in steps of 0.5 line; should remain
at logic 0 in normal operation
RollBack
F
X X X X X
roll back factor ranging from 0 (use 0% of estimated vectors) to 16
(use 100% of estimated vectors)
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NAME
Upconv3
ADDRESS
HEX
7
6
5
4
3
2
1
0
DESCRIPTION(2)
WRITE(1)
02B
write; S
MelzLfbm
X SAA4991WP type local fallback method instead of more robust local
fallback (complex or SAA4991WP type fallback)
Melzmemc
X
SAA4991WP film mode memory control (normal or SAA4991WP
type); should be set in SAA4991WP film mode to ensure that only
original lines are selected as output when UpcShFac is 0 or 32
MelDeint
MixCtrl
X
use (as in SAA4991WP) horizontal motion compensated median for
upconverter de-interlacing (normal or SAA4991WP type
de-interlacing)
X X X
Upconverter sensitivity:
0 to 3: smoothness dependent weighting between vector shifted
pixels and static pixels. 0 = sensitive to unsmoothness for taking more
of the static pixels ‘conservative’, up to 3 = hardly sensitive to
unsmoothness for taking more of static pixels ‘confident in vector
shifting’.
4 to 7: static weighting between vector shifted pixels and static pixels.
4 = take most of vector shifted pixels ‘confident in vector shifting’, up to
7 = take most of the static pixels ‘conservative’.
UpcColShiFac
0C4
02C
write; F
write; S
X X X X X X temporal interpolation factor used in chrominance upconverter; value
ranges from 0 (for current field position) to 32 (for previous field
position)
Motion estimator
Motest1
PenOdd
X X X additional penalty on vector candidates with odd vertical component
(0, 8, 16, 32, 64, 128, 256 or 511)
SpcThr
BmsThr
X X X
Active when EstMode = 0; replace the spatial prediction of one
estimator (left or right) by that of the other if the match error of the
former exceeds that of the latter by more than (0, 8, 16, 32, 64, 128,
256 or 511). A higher threshold means the two estimators are very
independent.
X X
Active when EstMode = 0; select as estimated vector the output of the
right estimator unless its match error exceeds that of the left estimator
by more than (0, 8, 16 or 32). This parameter should normally be set
to logic 0.
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ADDRESS
HEX
7
6
5
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DESCRIPTION(2)
WRITE(1)
Motest2
02D
write; S
TavLow
X If the difference between the current vector and the previous one in
the same spatial location is within a small window, then the two
vectors are averaged to improve temporal consistency. TavLow is the
lower threshold of this window (1 or 2).
TavUpp
MedEns
X X
see above; TavUpp is the upper threshold (0, 4, 8 or 16)
X X
scaling factor to reduce all sizes of update vectors in the ensemble
with medium sized vector templates (1, 1⁄2, 1⁄4 or 1⁄8)
LarEns
X X
scaling factor to reduce all sizes of update vectors in the ensemble
with large sized vector templates (1, 1⁄2, 1⁄4 or 1⁄8)
Motest3
02E
write; F
MotShiFac
X X X X X X Motion estimator shift factor, being the temporal position used in the
estimator at which the matching is done; value 32 for matching at
previous field position down to 0 for matching at current field position.
Keeping MotShiFac equal to UpShiFac in the next upconverted output
field estimates for minimum matching errors (minimum Halo’s).
MotShiFac at value 16 gives the largest natural vector range (twice as
large as with value 0 or 32). Going above the range with
MotShiFac ≠ 16 is dealt with in SAA4992H by shifting towards 16, but
for the horizontal and vertical component separately (consequence is
that vector candidates tend to rotate towards the diagonal directions).
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NAME
ADDRESS
HEX
7
6
5
4
3
2
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DESCRIPTION(2)
WRITE(1)
Motest4
02F
write; S
PenRng
X Penalty for vectors estimated on the first row and the first column (if
left estimator is used) or the right column (if right estimator is used),
whenever the spatial prediction candidate is selected (16 or 64).
For noisy pictures, this register could be set to logic 1 to improve
border processing in the estimator.
CndSet
X
choice of candidate set (left or right) for which data (Candidate1 to
Candidate8) is written in this field (becomes active in next field); see
note 3
ErrThr
ErrHbl
X X X
threshold on block match error for considering a block to be bad
(16, 32, 64, 128, 256, 512, 1024 or 2032)
X X
number of horizontally adjacent blocks that have to be all bad before
considering an occurrence of a burst error (1, 2, 4 or 8) (counting of
burst errors is read out with BlockErrCnt, address 0A8)
TstMod
Candidate1
Candidat1
X
to be kept to logic 1 for normal operation
090
091
092
write; S
write; S
write; S
X X X selection Candidate1 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update1
X X
X X
X X
update for Candidate1 (zero update, medium update, large update
or zero update)
Penalty1
Candidate2
Candidat2
X X X
X X X
X X X
penalty for Candidate1 (0, 8, 16, 32, 64, 128, 256 or 511)
X X X selection Candidate2 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update2
update for Candidate2 (zero update, medium update, large update
or zero update)
Penalty2
Candidate3
Candidat3
penalty for Candidate2 (0, 8, 16, 32, 64, 128, 256 or 511)
X X X selection Candidate3 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update3
Penalty3
update for Candidate3 (zero update, medium update, large update
or zero update)
penalty for Candidate3 (0, 8, 16, 32, 64, 128, 256 or 511)
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NAME
Candidate4
ADDRESS
HEX
7
6
5
4
3
2
1
0
DESCRIPTION(2)
WRITE(1)
093
094
095
096
097
098
write; S
Candidat4
X X X selection Candidate4 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update4
X X
X X
X X
X X
X X
update for Candidate4 (zero update, medium update, large update
or zero update)
Penalty4
Candidate5
Candidat5
X X X
X X X
X X X
X X X
X X X
penalty for Candidate4 (0, 8, 16, 32, 64, 128, 256 or 511)
write; S
write; S
write; S
write; S
write; S
X X X selection Candidate5 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update5
update for Candidate5 (zero update, medium update, large update
or zero update)
Penalty5
Candidate6
Candidat6
penalty for Candidate5 (0, 8, 16, 32, 64, 128, 256 or 511)
X X X selection Candidate6 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update6
update for Candidate6 (zero update, medium update, large update
or zero update)
Penalty6
Candidate7
Candidat7
penalty for Candidate6 (0, 8, 16, 32, 64, 128, 256 or 511)
X X X selection Candidate7 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update7
update for Candidate7 (zero update, medium update, large update
or zero update)
Penalty7
Candidate8
Candidat8
penalty for Candidate7 (0, 8, 16, 32, 64, 128, 256 or 511)
X X X selection Candidate8 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update8
update for Candidate8 (zero update, medium update, large update
or zero update)
Penalty8
penalty for Candidate8 (0, 8, 16, 32, 64, 128, 256 or 511)
PZpositionLeftUppX
X X X X X X X position of LeftUpp measurement point for pan-zoom calculations
(resolution: 16 pixels)
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NAME
ADDRESS
HEX
7
6
5
4
3
2
1
0
DESCRIPTION(2)
WRITE(1)
PZpositionLeftUppY
099
write; S
X X X X X X X Y position of LeftUpp measurement point for pan-zoom calculations
(resolution: 4 lines)
PZpositionRightLowX 09A
PZpositionRightLowY 09B
write; S
write; S
X X X X X X X position of RightLow measurement point for pan-zoom calculations
(resolution: 16 pixels)
X X X X X X X Y position of RightLow measurement point for pan-zoom calculations
(resolution: 4 lines)
PZvectorStartX
PZvectorDeltaX
PZvectorStartY
PZvectorDeltaY
09C
09D
09E
09F
write; F
write; F
write; F
write; F
X X X X X X X X X start value of pan-zoom vectors
X X X X X X X X X delta value of pan-zoom vectors
X X X X X X X X Y start value of pan-zoom vectors
X X X X X X X X Y delta value of pan-zoom vectors
Read data; note 3
GlobalMSEmsb
GlobalMSElsb
0A0
0A1
read; F
read; F
X X X X X X X X Global Mean Square Error (MSE) = summation within a field period of
squared differences in comparing vector shifted video from frame
X X X X X X X X
memory (FM2/3) with new field input (FM1) in those lines coinciding
with new field lines. The window for the measurement is kept at
40 pixels horizontal and 20 field lines vertical from the border of the
video. Measurements is only done in fields where the de-interlacer is
active, otherwise reading is zero. In field doubling mode, MSE is zero
at the end of every new input field.
GlobalMTImsb
GlobalMTIlsb
0A2
0A3
read; F
read; F
X X X X X X X X Global Motion Trajectory Inconsistency (MTI) = summation within a
field period of squared differences comparing shifted video from frame
X X X X X X X X
memory (FM2/3 output) with filtered data that is rewritten to the frame
memory (FM2/3 input) in those lines coinciding with new field lines.
The window for the measurement is kept at 40 pixels horizontal and
20 field lines vertical from the border of the video. Measurement is
done only in fields where de-interlacer is active, otherwise reading is
zero; in field doubling mode, MTI is zero at the end of every new input
field.
GlobalACTmsb
GlobalACTlsb
VectTempCons
0A4
0A5
0A6
read; F
read; F
read; F
X X X X X X X X global activity (ACT) = summation over a field period of the horizontal
plus the vertical components of the vectors of all blocks
X X X X X X X X
X X X X X X X X Vector temporal consistency = summation over a field period of
absolute differences of horizontal plus vertical components of vectors
newly estimated for each block compared with those vectors
estimated in the previous run at the same spatial block position.
It should be noted that a lower figure implies better consistency.
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SNERT
READ/
NAME
ADDRESS
HEX
7
6
5
4
3
2
1
0
DESCRIPTION(2)
WRITE(1)
VectSpatCons
0A7
read; F
X X X X X X X X Vector spatial consistency = summation over a field period of absolute
differences of horizontal and vertical components of vectors compared
with those of the neighbour blocks (L, R, U and D); in the comparison,
all vector data is used from the previous estimator run. It should be
noted that a lower figure implies better consistency
BlockErrCnt
LeastErrSum
0A8
0A9
read; F
read; F
X X X X X X X X burst error count (number of burst errors)
X X X X X X X X least error sum (summation over a field period of the smallest match
error that the estimator has found for each block: indicates reliability of
the estimation process)
YvecRangeErrCntmsb 0AA
read; F
X X X X X X X X Y vector range error count (number of vectors that have a vertical
component that is out of range for upconversion at the chosen
temporal position) (15 to 8)
YvecRangeErrCntlsb 0AB
read; F
read; F
write; F
X X X X X X X X Y vector range error count (7 to 0)
RefLineCountPrev
RefLineCountNew
0AC
0AD
X X X X X X X X read out of (number of input (run-) lines − 40) used in previous field
X X X X X X X X Write of [number of input (run-) lines − 40] to be used in new field
(actual maximum number of input lines in normal operation: 292;
register value 252). Nominally this is to be set as an exact copy of the
value read from RefLineCountPrev before a new field starts. In case
the effective number of input (run-) lines has increased,
RefLineCountNew should, for one field, be set to 255. This will occur
e.g. with decreasing vertical zoom magnification or changing from
525 lines video standard to 625 lines standard. If this is not done, a
deadlock will occur with too few lines processed correctly by the
motion estimator.
PanZoomVec0-X
PanZoomVec0-Y
FalconIdent
0B0
0B1
read; F
read
S
X X X X X X X X pan-zoom vector 0 (8-bit X value)
0
SAA4992H identification: fixed bit, reading this bit as zero means
SAA4992H is present
PanZoomVec0-Y
PanZoomVec1-X
PanZoomVec1-Y
StatusJump0
F
X X X X X X X pan-zoom vector 0 (7-bit Y value)
X X X X X X X X pan-zoom vector 1 (8-bit X value)
0B2
0B3
read; F
read
S
X
read out of configuration pin JUMP0
PanZoomVec1-Y
PanZoomVec2-X
F
X X X X X X X pan-zoom vector 1 (7-bit Y value)
0B4
read; F
X X X X X X X X pan-zoom vector 2 (8-bit X value)
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SNERT
READ/
NAME
ADDRESS
HEX
7
6
5
4
3
2
1
0
DESCRIPTION(2)
WRITE(1)
PanZoomVec2-Y
StatusJump1
0B5
read
S
X
read out of configuration pin JUMP1
X X X X X X X pan-zoom vector 2 (7-bit Y value)
PanZoomVec2-Y
PanZoomVec3-X
PanZoomVec3-Y
PanZoomVec4-X
PanZoomVec4-Y
PanZoomVec5-X
PanZoomVec5-Y
PanZoomVec6-X
PanZoomVec6-Y
PanZoomVec7-X
PanZoomVec7-Y
PanZoomVec8-X
PanZoomVec8-Y
EggSliceRgtMSB
EggSliceRgtLSB
EggSliceMixMSB
EggSliceMixLSB
F
0B6
0B7
0B8
0B9
0BA
0BB
0BC
0BD
0BE
0BF
0AE
0AF
0C0
0C1
0C2
0C3
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
read; F
X X X X X X X X pan-zoom vector 2 (8-bit X value)
X X X X X X X pan-zoom vector 3 (7-bit Y value)
X X X X X X X X pan-zoom vector 4 (8-bit X value)
X X X X X X X pan-zoom vector 4 (7-bit Y value)
X X X X X X X X pan-zoom vector 5 (8-bit X value)
X X X X X X X pan-zoom vector 5 (7-bit Y value)
X X X X X X X X pan-zoom vector 6 (8-bit X value)
X X X X X X X pan-zoom vector 6 (7-bit Y value)
X X X X X X X X pan-zoom vector 7 (8-bit X value)
X X X X X X X pan-zoom vector 7 (7-bit Y value)
X X X X X X X X pan-zoom vector 8 (8-bit X value)
X X X X X X X pan-zoom vector 8 (7-bit Y value)
X X X X X X X X result of right pixels egg-slice detector (15 to 8)
X X X X X X X X result of right pixels egg-slice detector (7 to 0)
X X X X X X X X result of mixed pixels egg-slice detector (15 to 8)
X X X X X X X X result of mixed pixels egg-slice detector (7 to 0)
Notes
1. S means semi static, used at initialization or mode changes; F means field frequent, in general updated in each display field.
2. Selectable items are marked bold.
3. Almost all of the R(ead) and W(rite) registers of SAA4992H are double buffered. The Write registers are latched by a signal called New_field.
New_field gets set, when RE_f rises after RSTR (New_field is effectively at the start of active video). The Read registers are latched by a signal
called Reg_upd. Reg_upd gets set, when half the number of active pixels of the fourth line of vertical blanking have entered the SAA4992H
(Reg_upd will effectively be active 3 and a halve lines after the RE_a, RE_c and RE_e have ended). The only exceptional registers, which are not
double buffered, are:
a) Write register 025: power_on_reset
b) Write register 02F, bit 1: CndSet
c) Read register 0B0 to 0BF, 0AE and 0AF: pan_zoom_vectors, including FalconIdent (= 0), jump0 and jump1.
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
9
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER
VDD
IDD
Io
MIN.
MAX.
UNIT
supply voltage
supply current
output current
−0.5
−
+3.6
600
2.0
V
mA
mA
V
−
Vi
input voltage for all I/O pins
storage temperature
−0.5
−55
0
+3.6
+150
125
Tstg
Tj
°C
°C
junction temperature
10 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
Rth(j-c)
PARAMETER
thermal resistance from junction to ambient in free air
thermal resistance from junction to case
CONDITIONS
VALUE
UNIT
27
K/W
K/W
2.9
11 CHARACTERISTICS
DD = 3.0 to 3.6 V; Tamb = 0 to 70 °C; unless otherwise specified.
V
SYMBOL PARAMETER
General
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
IDD
VOH
VOL
VIH
VIL
supply voltage
supply current
3.0
3.3
3.6
V
−
400
−
550
−
mA
V
HIGH-level output voltage
LOW-level output voltage
HIGH-level input voltage
LOW-level input voltage
LOW-level output current
output load capacitance
input capacitance
2.4
−
−
0.4
3.6
0.8
2
V
2.0
0
−
V
−
V
IOL
−
−
mA
pF
pF
µA
Co(L)
Ci
−
−
50
8
−
−
ILI
input leakage current
−
−
1
Outputs; note 1; see Fig.5
IOZ
output current in 3-state mode
−0.5 < Vo < 3.6
−
−
−
−
−
1
µA
td(o)
th(o)
SR
output delay time
output hold time
slew rate
−
21
−
ns
4
ns
300
700
mV/ns
Inputs; note 2; see Fig.5
tsu(i) input set-up time
th(i) input hold time
8
2
−
−
−
−
ns
ns
2000 Feb 04
28
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input CLK32; see Fig.5
tr
rise time
fall time
−
−
−
−
−
−
4
ns
tf
4
ns
%
δ
duty factor
cycle time
40
30
60
39
Tcy
ns
SNERT interface; see Fig.7
tSNRSTH
td(SNRST-SNCL
Tcy(SNCL)
tsu(i)(SNCL)
th(i)(SNCL)
th(o)
SNRST pulse HIGH time
500
200
0.5
53
−
−
−
−
−
−
−
−
−
ns
ns
µs
ns
ns
ns
ns
ns
)
delay SNRST pulse to SNCL LOW time
SNCL cycle time
−
1
input set-up time to SNCL
input hold time to SNCL
output hold time
−
10
−
30
−
td(o)
output delay time
−
330
−
to(en)
output enable time
210
BST interface; see Fig.6
Tcy(BST)
tsu(i)(BST)
th(i)(BST)
th(o)(BST)
td(o)(BST)
BST cycle time
−
3
6
4
−
1
−
−
−
−
−
µs
ns
ns
ns
ns
input set-up time
input hold time
output hold time
output delay time
−
−
−
30
Notes
1. Timing characteristics are measured with CL = 15 pF; IOL = 2 mA; RL = 2 kΩ.
2. All inputs except SNERT, CLK32 and BST.
2000 Feb 04
29
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
t
t
r
f
90%
10%
90%
10%
CLOCK
1.5 V
INPUT
DATA
MHB175
t
t
su(i)
h(i)
OUTPUT
DATA
data
valid
data transition
period
t
h(o)
t
d(o)
Fig.5 Data input/output timing diagram.
T
cy(BST)
TCK
TDI, TMS
TDO
MHB649
t
t
su(i)(BST)
h(o)(BST)
h(i)(BST)
t
t
d(o)(BST)
Fig.6 Boundary scan test interface timing diagram.
30
2000 Feb 04
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
SNCL
write sequence:
SNDA
a0
a0
a1
a1
a2
a2
a3
a3
a4
a4
a5
a5
a6
a6
a7
a7
w0
w1
w2
w3
w4
w5
w6
w7
read sequence:
SNDA
driven by
master
r0
r1
r2
r3
r4
r5
r6
r7
SNDA
driven by
SAA4992H
SNCL
50%
50%
50%
t
t
h(i)(SNCL)
su(i)(SNCL)
a6
write sequence:
SNDA
a7
w0
w1
read sequence:
SNDA
driven by
master
a6
a7
t
t
h(o)
o(en)
SNDA
driven by
SAA4992H
r0
r1
t
t
d(o)
MHB650
d(o)
Fig.7 SNERT interface timing diagram.
2000 Feb 04
31
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
Table 2 YUV formats; note 1
4 : 2 : 2 DPCM
FORMAT(2)
I/O PIN(1)
4 : 1 : 1 FORMAT(2)
4 : 2 : 2 FORMAT
YX7
YX6
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
U07
U06
V07
V06
X
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
U05
U04
V05
V04
X
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
U03
U02
V03
V02
X
Y37
Y36
Y35
Y34
Y33
Y32
Y31
Y30
U01
U00
V01
V00
X
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
U07
U06
U05
U04
U03
U02
U01
U00
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
V07
V06
V05
V04
V03
V02
V01
V00
Y07
Y06
Y05
Y04
Y03
Y02
Y01
Y00
UC03
UC02
UC01
UC00
X
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
VC03
VC02
VC01
VC00
X
YX5
YX4
YX3
YX2
YX1
YX0
UVX7
UVX6
UVX5
UVX4
UVX3
UVX2
UVX1
UVX0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Notes
1. Index X refers to different I/O buses:
a) X = A: input from 1st field memory
b) X = B: output to 2nd field memory
c) X = C: input from 2nd field memory
d) X = D: output to 3rd field memory
e) X = E: input from 3rd field memory
f) X = F: main output
g) X = G: 2nd output for matrix purposes.
The first index digit defines the sample number, the second defines the bit number.
2. X = don’t care or not available.
2000 Feb 04
32
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
12 PACKAGE OUTLINE
QFP160: plastic quad flat package;
160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height
SOT322-2
y
X
A
120
121
81
80
Z
E
e
A
2
H
A
E
E
A
(A )
3
1
θ
w M
p
L
p
b
L
pin 1 index
detail X
41
160
1
40
Z
w M
D
v M
A
b
p
e
D
B
H
v M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
7o
0o
0.50 3.60
0.25 3.20
0.38 0.23 28.1 28.1
0.22 0.13 27.9 27.9
31.45 31.45
30.95 30.95
1.03
0.73
1.5
1.1
1.5
1.1
mm
4.07
0.25
0.13 0.1
0.65
1.6
0.3
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
99-11-03
00-01-19
SOT322-2
135E12
MS-022
2000 Feb 04
33
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
13 SOLDERING
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
13.1 Introduction to soldering surface mount
packages
• For packages with leads on two sides and a pitch (e):
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
13.4 Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
13.3 Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
2000 Feb 04
34
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction
SAA4992H
13.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
14 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
15 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Feb 04
35
Philips Semiconductors – a worldwide company
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Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
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Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
69
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/01/pp36
Date of release: 2000 Feb 04
Document order number: 9397 750 06587
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