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SAA4993H [NXP]

Field and line rate converter with noise reduction; 场和线路速率转换器降噪
SAA4993H
型号： SAA4993H
厂家： NXP    NXP
描述：

Field and line rate converter with noise reduction
场和线路速率转换器降噪

转换器
文件： 总40页 (文件大小：149K)
中文：  中文翻译
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INTEGRATED CIRCUITS  
DATA SHEET  
SAA4993H  
Field and line rate converter  
with noise reduction  
Product specification  
2001 Nov 23  
File under Integrated Circuits, IC02  
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
CONTENTS  
12  
PACKAGE OUTLINE  
SOLDERING  
13  
1
FEATURES  
13.1  
Introduction to soldering surface mount  
packages  
Reflow soldering  
Wave soldering  
Manual soldering  
2
GENERAL DESCRIPTION  
Patent notice  
2.1  
3
13.2  
13.3  
13.4  
13.5  
QUICK REFERENCE DATA  
ORDERING INFORMATION  
BLOCK DIAGRAMS  
4
Suitability of surface mount IC packages for  
wave and reflow soldering methods  
5
6
PINNING  
14  
15  
16  
DATA SHEET STATUS  
DEFINITIONS  
7
FUNCTIONAL DESCRIPTION  
CONTROL REGISTER DESCRIPTION  
LIMITING VALUES  
8
DISCLAIMERS  
9
10  
11  
THERMAL CHARACTERISTICS  
CHARACTERISTICS  
2001 Nov 23  
2
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
1
FEATURES  
2
GENERAL DESCRIPTION  
• Upconversion of all 1fH film and video standards up to  
292 active input lines per field  
The SAA4993H is a completely digital monolithic  
integrated circuit which can be used for field and line rate  
conversion of all global TV standards.  
• 100/120 Hz 2 : 1, 50/60 Hz 1 : 1 and 100/120 Hz 1 : 1  
It features improved Natural Motion (1) performance.  
output formats  
• 4 : 1 : 1, 4 : 2 : 2 and 4 : 2 : 2 Differential Pulse Code  
Modulation (DPCM) input colour formats; 4 : 1 : 1 and  
4 : 2 : 2 output colour formats  
It can be configured to emulate the SAA4990H as well as  
the SAA4991WP. For demonstration purposes a split  
screen mode to show the Dynamic Noise Reduction  
(DNR) function and natural motion is available, and a  
colour vector overlay mode exists.  
• Full 8-bit accuracy  
• Scalable performance by applying 2 or 3 external field  
memories  
The SAA4993H supports a Boundary Scan Test (BST)  
circuit in accordance with IEEE 1149.  
• Improved recursive de-interlacing  
• Film (25 and 30 Hz) upconversion to 100/120  
movement phases per second  
2.1  
Patent notice  
Notice is herewith given that the subject integrated circuit  
uses one or more of the following US patents and that  
each of these patents may have corresponding patents in  
other jurisdictions.  
• Variable vertical sharpness enhancement  
• Motion compensated 3D dynamic noise reduction  
• High quality vertical zoom  
• 2 Mbaud serial interface (SNERT)  
US 4740842, US 5929919, US 6034734, US 5534946,  
US 5532750, US 5495300, US 5903680, US 5365280,  
US 5148269, US 5072293, US 5771074, and  
US 5302909.  
• Demonstration mode for noise reduction, motion  
compensation and colour overlay.  
(1) Natural Motion is a trademark of Koninklijke Philips  
Electronics N.V.  
3
QUICK REFERENCE DATA  
SYMBOL  
PARAMETER  
MIN.  
2.3  
TYP. MAX. UNIT  
VDDI  
VDDE  
core supply voltage  
2.5  
3.3  
280  
32  
2.7  
3.6  
−
V
external supply voltage (output pads)  
supply current  
3.0  
−
V
IDD  
mA  
MHz  
°C  
fCLK32  
Tamb  
operating clock frequency  
ambient temperature  
−
33.3  
70  
0
−
4
ORDERING INFORMATION  
PACKAGE  
TYPE  
NUMBER  
NAME  
DESCRIPTION  
VERSION  
SAA4993H  
QFP160  
plastic quad flat package; 160 leads (lead length 1.6 mm);  
SOT322-2  
body 28 × 28 × 3.4 mm; high stand-off height  
2001 Nov 23  
3
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ahdnbok,uflapegwidt  
FIELD MEMORY 2  
YB7 to YB0  
FIELD MEMORY 3  
YD7 to YD0  
YC0 to YC7  
2 to 9  
YE0 to YE7  
122 to 129  
151, 152,  
111, 112,  
154 to 159  
114 to 119  
COMPRESS  
DECOMPRESS  
45 to 52  
DYNAMIC  
NOISE  
YA0 to YA7  
REDUCTION  
SEQUENCER  
27  
26  
MUX  
MUX  
SNCL  
SNDA  
SNERT  
INTERFACE  
25  
SAA4993H  
SNRST  
DE-INTERLACER  
vectors  
61 to 68  
82 to 89  
CONTROL  
YF7 to YF0  
YG7 to YG0  
MPR  
LEFT  
VERTICAL  
ZOOM  
VERTICAL  
PEAKING  
MPR  
RIGHT  
35  
34  
33  
32  
31  
30  
SPM  
TPM  
ESM  
TCK  
TDO  
TDI  
MOTION ESTIMATOR  
BST/TEST  
vectors  
TMS  
TRST  
TE  
UPCONVERSION  
79  
CLK32  
MHC054  
The solid lines represent pixel data; the broken lines represent controls.  
Fig.1 Block diagram of the luminance part.  
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ahdnbok,uflapegwidt  
FIELD MEMORY 2  
FIELD MEMORY 3  
UVB3 to UVB0  
147 to 150  
UVC0 to UVC3  
10 to 13  
UVD3 to UVD0  
107 to 110  
UVE0 to UVE3  
130 to 133  
COMPRESS/  
FORMAT  
DECOMPRESS/  
REFORMAT  
37 to 44  
DECOMPRESS/  
REFORMAT  
UVA0 to UVA7  
DNR  
SAA4993H  
vectors  
MPR  
LEFT  
MPR  
RIGHT  
70 to 77  
91 to 98  
UPCONVERSION  
FORMAT  
UVF7 to YVF0  
UVG7 to YVG0  
VERTICAL  
ZOOM  
MHC055  
The solid lines represent pixel data; the broken lines represent the data flow, if the (optional) field memory 3 is also used.  
Fig.2 Block diagram of the chrominance part.  
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
6
PINNING  
SYMBOL  
PIN  
TYPE  
DESCRIPTION(1)(2)  
VSSE  
YC0  
1
2
ground ground of output pads  
input  
input  
input  
input  
input  
input  
input  
input  
input  
input  
input  
input  
bus C luminance input from field memory 2 bit 0 (LSB)  
bus C luminance input from field memory 2 bit 1  
bus C luminance input from field memory 2 bit 2  
bus C luminance input from field memory 2 bit 3  
bus C luminance input from field memory 2 bit 4  
bus C luminance input from field memory 2 bit 5  
bus C luminance input from field memory 2 bit 6  
bus C luminance input from field memory 2 bit 7 (MSB)  
bus C chrominance input from field memory 2 bit 0 (LSB)  
bus C chrominance input from field memory 2 bit 1  
bus C chrominance input from field memory 2 bit 2  
bus C chrominance input from field memory 2 bit 3 (MSB)  
YC1  
3
YC2  
4
YC3  
5
YC4  
6
YC5  
7
YC6  
8
YC7  
9
UVC0  
UVC1  
UVC2  
UVC3  
REC  
VSSE  
VDDE  
VSSI  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
output read enable output for bus C  
ground ground of output pads  
supply external supply voltage (output pads)  
ground core ground  
VDDI  
supply core supply voltage  
JUMP0  
input  
configuration pin 0; will be stored in register 0B3 e.g. to indicate presence of 3rd field  
memory; should be connected to ground or to VDDE via a pull-up resistor of 47 kΩ  
JUMP1  
20  
input  
configuration pin 1; will be stored in register 0B5 e.g. to indicate presence of 16-bit  
1st field memory for full 4 : 2 : 2; should be connected to ground or to VDDE via a pull-up  
resistor of 47 kΩ  
VDDE  
21  
22  
23  
24  
supply external supply voltage (output pads)  
supply core supply voltage  
VDDI  
VSSI  
ground core ground  
RAMTST1  
input  
test pin 1 input for internal RAM testing with internal pull-down; connect to ground for  
normal operation  
SNRST  
SNDA  
25  
26  
27  
28  
29  
input  
I/O  
SNERT bus reset input  
SNERT bus data input and output  
SNERT bus clock input  
SNCL  
input  
VSSE  
ground ground of output pads  
RAMTST2  
input  
test pin 2 input for internal RAM testing with internal pull-down; connect to ground for  
normal operation  
TE  
30  
31  
input  
input  
test mode input with internal pull-down; if not used it has to be connected to ground  
TRST  
boundary scan test reset input (active LOW); if not used it has to be connected to VDDE  
via a pull-up resistor of 47 kΩ  
TMS  
TDI  
32  
33  
input  
input  
boundary scan test mode select input; if not used it has to be connected to VDDE via a  
pull-up resistor of 47 kΩ  
boundary scan test data input; if not used it has to be connected to VDDE via a pull-up  
resistor of 47 kΩ  
2001 Nov 23  
6
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
SYMBOL  
PIN  
TYPE  
DESCRIPTION(1)(2)  
TDO  
TCK  
34  
35  
3-state boundary scan test data output  
input  
boundary scan test clock input; if not used it has to be connected to VDDE via a pull-up  
resistor of 47 kΩ  
VSSE  
UVA0  
UVA1  
UVA2  
UVA3  
UVA4  
UVA5  
UVA6  
UVA7  
YA0  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
ground ground of output pads  
bus A chrominance input from field memory 1 bit 0 (LSB)  
input  
input  
input  
input  
input  
input  
input  
input  
input  
input  
input  
input  
input  
input  
input  
input  
bus A chrominance input from field memory 1 bit 1  
bus A chrominance input from field memory 1 bit 2  
bus A chrominance input from field memory 1 bit 3  
bus A chrominance input from field memory 1 bit 4  
bus A chrominance input from field memory 1 bit 5  
bus A chrominance input from field memory 1 bit 6  
bus A chrominance input from field memory 1 bit 7 (MSB)  
bus A luminance input from field memory 1 bit 0 (LSB)  
bus A luminance input from field memory 1 bit 1  
bus A luminance input from field memory 1 bit 2  
bus A luminance input from field memory 1 bit 3  
bus A luminance input from field memory 1 bit 4  
bus A luminance input from field memory 1 bit 5  
bus A luminance input from field memory 1 bit 6  
bus A luminance input from field memory 1 bit 7 (MSB)  
YA1  
YA2  
YA3  
YA4  
YA5  
YA6  
YA7  
REA  
VSSE  
VSSI  
output read enable output for bus A  
ground ground of output pads  
ground core ground  
VDDI  
VDDI  
VSSI  
supply core supply voltage  
supply core supply voltage  
ground core ground  
VSSE  
REF  
YF7  
ground ground of output pads  
input  
read enable input for bus F and G  
output bus F luminance output bit 7 (MSB)  
output bus F luminance output bit 6  
output bus F luminance output bit 5  
output bus F luminance output bit 4  
output bus F luminance output bit 3  
output bus F luminance output bit 2  
output bus F luminance output bit 1  
output bus F luminance output bit 0 (LSB)  
supply external supply voltage (output pads)  
output bus F chrominance output bit 7 (MSB)  
output bus F chrominance output bit 6  
output bus F chrominance output bit 5  
output bus F chrominance output bit 4  
YF6  
YF5  
YF4  
YF3  
YF2  
YF1  
YF0  
VDDE  
UVF7  
UVF6  
UVF5  
UVF4  
2001 Nov 23  
7
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
SYMBOL  
PIN  
TYPE  
DESCRIPTION(1)(2)  
UVF3  
UVF2  
UVF1  
UVF0  
VSSE  
CLK32  
VSSI  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
output bus F chrominance output bit 3  
output bus F chrominance output bit 2  
output bus F chrominance output bit 1  
output bus F chrominance output bit 0 (LSB)  
ground ground of output pads  
input  
system clock input  
ground core ground  
VSSE  
YG7  
ground ground of output pads  
3-state bus G luminance output bit 7 (MSB)  
3-state bus G luminance output bit 6  
YG6  
YG5  
3-state bus G luminance output bit 5  
YG4  
3-state bus G luminance output bit 4  
YG3  
3-state bus G luminance output bit 3  
YG2  
3-state bus G luminance output bit 2  
YG1  
3-state bus G luminance output bit 1  
YG0  
3-state bus G luminance output bit 0 (LSB)  
supply external supply voltage (output pads)  
3-state bus G chrominance output bit 7 (MSB) or vector output bit 7  
3-state bus G chrominance output bit 6 or vector output bit 6  
3-state bus G chrominance output bit 5 or vector output bit 5  
3-state bus G chrominance output bit 4 or vector output bit 4  
3-state bus G chrominance output bit 3 or vector output bit 3  
3-state bus G chrominance output bit 2 or vector output bit 2  
3-state bus G chrominance output bit 1 or vector output bit 1  
3-state bus G chrominance output bit 0 (LSB) or vector output bit 0  
ground ground of output pads  
VDDE  
UVG7  
UVG6  
UVG5  
UVG4  
UVG3  
UVG2  
UVG1  
UVG0  
VSSE  
VSSI  
100 ground core ground  
VDDI  
101 supply core supply voltage  
VDDE  
VDDI  
102 supply external supply voltage (output pads)  
103 supply core supply voltage  
VSSI  
104 ground core ground  
VSSE  
WED  
UVD3  
UVD2  
UVD1  
UVD0  
YD7  
105 ground ground of output pads  
106 3-state write enable output for bus D  
107 3-state bus D chrominance output to field memory 3 bit 3 (MSB)  
108 3-state bus D chrominance output to field memory 3 bit 2  
109 3-state bus D chrominance output to field memory 3 bit 1  
110 3-state bus D chrominance output to field memory 3 bit 0 (LSB)  
111 3-state bus D luminance output to field memory 3 bit 7 (MSB)  
112 3-state bus D luminance output to field memory 3 bit 6  
113 supply external supply voltage (output pads)  
114 3-state bus D luminance output to field memory 3 bit 5  
YD6  
VDDE  
YD5  
2001 Nov 23  
8
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
SYMBOL  
PIN  
TYPE  
DESCRIPTION(1)(2)  
YD4  
115 3-state bus D luminance output to field memory 3 bit 4  
116 3-state bus D luminance output to field memory 3 bit 3  
117 3-state bus D luminance output to field memory 3 bit 2  
118 3-state bus D luminance output to field memory 3 bit 1  
119 3-state bus D luminance output to field memory 3 bit 0 (LSB)  
120 ground ground of output pads  
YD3  
YD2  
YD1  
YD0  
VSSE  
VSSE  
YE0  
121 ground ground of output pads  
122 input  
123 input  
124 input  
125 input  
126 input  
127 input  
128 input  
129 input  
130 input  
131 input  
132 input  
133 input  
bus E luminance input from field memory 3 bit 0 (LSB)  
bus E luminance input from field memory 3 bit 1  
bus E luminance input from field memory 3 bit 2  
bus E luminance input from field memory 3 bit 3  
bus E luminance input from field memory 3 bit 4  
bus E luminance input from field memory 3 bit 5  
bus E luminance input from field memory 3 bit 6  
bus E luminance input from field memory 3 bit 7 (MSB)  
bus E chrominance input from field memory 3 bit 0 (LSB)  
bus E chrominance input from field memory 3 bit 1  
bus E chrominance input from field memory 3 bit 2  
bus E chrominance input from field memory 3 bit 3 (MSB)  
YE1  
YE2  
YE3  
YE4  
YE5  
YE6  
YE7  
UVE0  
UVE1  
UVE2  
UVE3  
REE  
VSSE  
HREF  
VSSI  
134 output read enable output for bus E  
135 ground ground of output pads  
136 input  
horizontal reference synchronization input  
137 ground core ground  
138 supply core supply voltage  
VDDI  
OSCI  
RESFM  
139 input  
test pin input with internal pull-down; connect to ground for normal operation  
140 output reset field memory output for pin OSCI = LOW or test output OSCOUT for  
pin OSCI = HIGH  
VDDE  
VDDI  
141 supply external supply voltage (output pads)  
142 supply core supply voltage  
VSSI  
143 ground core ground  
ACV  
VSSE  
WEB  
UVB3  
UVB2  
UVB1  
UVB0  
YB7  
144 output active video output  
145 ground ground of output pads  
146 output write enable output for bus B  
147 output bus B chrominance output to field memory 2 bit 3 (MSB)  
148 output bus B chrominance output to field memory 2 bit 2  
149 output bus B chrominance output to field memory 2 bit 1  
150 output bus B chrominance output to field memory 2 bit 0 (LSB)  
151 output bus B luminance output to field memory 2 bit 7 (MSB)  
152 output bus B luminance output to field memory 2 bit 6  
153 supply external supply voltage (output pads)  
154 output bus B luminance output to field memory 2 bit 5  
YB6  
VDDE  
YB5  
2001 Nov 23  
9
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
SYMBOL  
PIN  
TYPE  
DESCRIPTION(1)(2)  
YB4  
YB3  
YB2  
YB1  
YB0  
VSSE  
155 output bus B luminance output to field memory 2 bit 4  
156 output bus B luminance output to field memory 2 bit 3  
157 output bus B luminance output to field memory 2 bit 2  
158 output bus B luminance output to field memory 2 bit 1  
159 output bus B luminance output to field memory 2 bit 0 (LSB)  
160 ground ground of output pads  
Notes  
1. Not used input pins (e.g. bus E) should be connected to ground.  
2. Because of the noisy characteristic of the output pad supply, it is recommended not to connect the core supply and  
the output pad supply directly at the device. The output pad supply should be buffered as close as possible to the  
device.  
2001 Nov 23  
10  
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
V
V
SSE  
1
2
3
4
5
6
7
8
9
120  
SSE  
YC0  
119 YD0  
118 YD1  
117 YD2  
116 YD3  
115 YD4  
114 YD5  
YC1  
YC2  
YC3  
YC4  
YC5  
YC6  
YC7  
V
113  
DDE  
112 YD6  
UVC0 10  
UVC1 11  
UVC2 12  
UVC3 13  
REC 14  
111 YD7  
110 UVD0  
109 UVD1  
108 UVD2  
107 UVD3  
106 WED  
V
V
15  
16  
17  
18  
SSE  
V
V
V
V
V
V
V
105  
104  
103  
102  
101  
100  
99  
DDE  
SSE  
SSI  
V
SSI  
DDI  
V
DDI  
DDE  
DDI  
SSI  
JUMP0 19  
JUMP1 20  
SAA4993H  
V
21  
22  
23  
DDE  
V
DDI  
SSE  
V
98 UVG0  
97 UVG1  
96 UVG2  
95 UVG3  
94 UVG4  
93 UVG5  
92 UVG6  
91 UVG7  
SSI  
RAMTST1 24  
SNRST 25  
SNDA 26  
SNCL 27  
V
28  
SSE  
RAMTST2 29  
TE 30  
V
TRST 31  
TMS 32  
TDI 33  
90  
DDE  
89 YG0  
88 YG1  
87 YG2  
86 YG3  
85 YG4  
84 YG5  
83 YG6  
82 YG7  
TDO 34  
TCK 35  
V
36  
SSE  
UVA0 37  
UVA1 38  
UVA2 39  
UVA3 40  
V
81  
SSE  
MHC056  
Fig.3 Pin configuration.  
2001 Nov 23  
11  
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
7
FUNCTIONAL DESCRIPTION  
Table 1 Clock cycle references  
The fal_top module builds the functional top level of the  
SAA4993H. It connects the luminance data path, the  
chrominance data path and the luminance  
(de)compression with SAA4993H inputs and outputs as  
well as controlling logic. Outside of the fal_top module,  
there are only the pad cells, boundary scan test cells, the  
boundary scan test controller, the clock tree, the test  
enable tree and the input port registers.  
SIGNAL  
LATENCY  
RE_F  
0
RE_C and  
RE_E  
62 cycles + REceShift  
YC, YE, UVC  
and UVE  
63 cycles  
RE_A  
93 cycles + REaShift  
94 cycles  
YA and UVA  
Figure 4 shows a simplified block diagram of the fal_top  
module. It displays the flow of pixel data (solid lines) and  
controls (broken lines) between the modules inside.  
YF, YG, UVF  
and UVG  
147 cycles + 3 input lines  
WE_B and  
WE_D  
159 cycles + 4 input lines + WEbdShift  
159 cycles + 4 input lines  
Basic functionality of the modules in the fal_top module is  
as follows:  
YB, YD, UVB  
and UVD  
• KER (kernel): Y (luminance) data path  
• COL (colour): UV (chrominance) data path  
• YDP (Y-DPCM): compression (and decompression) of  
luminance output (and input) data by Differential Pulse  
Code Modulation (DPCM)  
There is an algorithmic delay of 3 lines between input and  
output data. Therefore, the main data output on the  
F and G bus begins while the fourth input line is read.  
Writing to the B and D bus starts one input line later. The  
read and write enable signals RE_A, WE_B, RE_C, WE_D  
and RE_E can be shifted by control registers REaShift,  
WEbdShift and REceShift, which are implemented in the  
line sequencer.  
• LSE (line sequencer): generate line frequent control  
signals  
• SNE (interface): Synchronous No parity Eight bit  
Reception and Transmission (SNERT) interface to a  
microcontroller.  
The SNERT interface operates in a slave receive and  
transmit mode for communication with a microcontroller,  
which resides on peripheral circuits (e.g. SAA4978H)  
together with a SNERT master. The SNERT interface  
transforms serial data from the microcontroller (via the  
SNERT bus) into parallel data to be written into the  
SAA4993Hs write registers and parallel data from  
SAA4993Hs read registers into serial data to be sent to the  
microcontroller. The SNERT bus consists of 3 signals:  
The fal_top module itself reads the following control  
register bits (addresses):  
• NrofFMs (017H)  
• MatrixOn (026H) and BusGControl (028H)  
• MemComp and MemDecom (026H).  
NrofFMs, MatrixOn and BusGControl are used to enable  
the D and G output bus, respectively. MemComp and  
MemDecom are connected to YDP to control luminance  
data compression and decompression. These control  
register signals are not displayed in Fig.4. Further  
information on the control registers is given in Chapter 8.  
1. SNCL: used as serial clock signal, generated by the  
master  
2. SNDA: used as bidirectional data line  
3. SNRST: used as a reset signal, generated by the  
microcontroller to indicate the start of a transmission.  
The processing of a video field begins on the rising edge  
of the RE_F input signal. As indicated in Fig.4, the  
SAA4993H receives its inputs and generates its outputs at  
the following clock cycles after RE_F (see Table 1).  
2001 Nov 23  
12  
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
external field memories  
WE_B,  
WE_D  
RE_C,  
RE_E  
UVB,  
UVD  
UVC,  
UVE  
YB,  
YD  
YC,  
YE  
159  
cycles  
62  
cycles  
159  
63  
159  
63  
cycles cycles cycles cycles  
fal_top  
UVA  
94 cycles  
YDP  
COL  
UVF, UVG  
147 cycles  
SNDA  
SNE  
LSE  
RE_A  
RE_F  
93 cycles  
0 cycles  
YF, YG  
147 cycles  
KER  
YA  
94 cycles  
MHC057  
The solid lines represent pixel data; the broken lines represent controls.  
Fig.4 Block diagram of fal_top.  
2001 Nov 23  
13  
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8
CONTROL REGISTER DESCRIPTION  
SNERT  
ADDRESS  
(HEX)  
READ/  
WRITE(1)  
NAME  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
DNR/peaking/colour  
Kstep10  
Kstep0  
Kstep1  
Kstep32  
Kstep2  
Kstep3  
Kstep54  
Kstep4  
Kstep5  
Kstep76  
Kstep6  
010  
011  
012  
013  
write; S  
write; S  
write; S  
write; S  
X X X X set LUT value: k = 1⁄16 if difference below (0 to 15)  
set LUT value: k = 1⁄8 if difference below (0 to 15)  
X X X X  
X X X X  
X X X X  
X X X X set LUT value: k = 2⁄8 if difference below (0 to 30 in multiples of 2)  
set LUT value: k = 3⁄8 if difference below (0 to 30 in multiples of 2)  
X X X X set LUT value: k = 4⁄8 if difference below (0 to 60 in multiples of 4)  
set LUT value: k = 5⁄8 if difference below (0 to 60 in multiples of 4)  
X X X X set LUT value: k = 6⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,  
64, 72, 80, 88, 96, 104, 112 or 120)  
Kstep7  
X X X X  
set LUT value: k = 7⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,  
64, 72, 80, 88, 96, 104, 112 or 120)  
Gain_fix_y  
014  
015  
016  
write; S  
write; S  
write; S  
FixvalY  
X X X X set fixed Y value; used when FixY = 1 or in left part of split screen  
(0, 1⁄16 to 14 16 or 16⁄16)  
⁄
GainY  
FixY  
X X X  
X
set gain in difference signal for adaptive DNR Y (1⁄8, 1⁄4, 1⁄2, 1, 2 or 4)  
select fixed Y (adaptive or fixed) (full screen)  
Gain_fix_uv  
FixvalUV  
X X X X set fixed UV value; used when FixUV = 1 or in left part of split screen  
(0, 1⁄16 to 14 16 or 16⁄16)  
⁄
GainUV  
FixUV  
X X X  
X
set gain in difference signal for adaptive DNR UV (1⁄8, 1⁄4, 1⁄2, 1, 2 or 4)  
select fixed UV (adaptive or fixed) (full screen)  
Peak_Vcomp  
VecComp  
X X X set degree of horizontal vector compensation in Y DNR:  
(0, 1⁄8, 2⁄8, 3⁄8, 4⁄8, 5⁄8, 6⁄8 or 7⁄8) of the vector  
PeakCoef  
X X X X  
set vertical peaking level: (0, +2, +3.5, +5, +6, x, x, x, x, x, x, x, x,  
−12, −6 or −2.5) dB  
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SNERT  
READ/  
NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
DNR_Colour_mode  
017  
write; S  
ColourIn  
X X select colour input format: (4 : 1 : 1, 4 : 2 : 2, 4 : 2 : 2 DPCM or  
4 : 2 : 2)  
ColourOut  
NrofFMs  
ColOvl  
X
select colour output format: (4 : 1 : 1 or 4 : 2 : 2)  
X
set number of field memories connected: (1 or 2 plus 3)  
X
select vector overlay on colour output: (vector overlay or colour  
from video path)  
SlaveUVtoY  
DnrSplit  
X
slave UV noise reduction to K factor of Y: (separate or slaved)  
select split screen mode for DNR: (normal or split screen)  
X
DnrHpon  
X
switch DNR high-pass on (DNR only active on low frequent spectrum:  
(all through DNR or high bypassed)  
Vertical zoom  
Zoom1  
018  
write; F  
ZoomSt98  
X X zoom line step bits 9 and 8; line step = vertical distance between  
successive output lines; usable range = 0 to 2 frame lines;  
resolution 1⁄256 frame line  
ZoomPo98  
X X  
zoom start position bits 9 and 8; start position = vertical position of the  
top display line; usable range = 1 to 3 frame lines; resolution 1⁄256  
frame line  
Zoom2  
019  
01A  
01B  
write; F  
write; F  
write; F  
ZoomSt70  
Zoom3  
X X X X X X X X zoom line step bits 7 to 0 (see above)  
X X X X X X X X zoom start position bits 7 to 0 (see above)  
ZoomPo70  
Zoom4  
ZoomEnVal  
X X X X zoom run in value = number of lines without zoom active  
(0 to 15 lines)  
ZoomDiVal  
X X X X  
zoom run out value = number of lines without zoom active  
(−8 to +7 lines)  
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SNERT  
READ/  
NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
De-interlacer  
Proscan1  
01C  
write; S  
KlfLim  
X X X X limitation of recursion factor in calculation of original line positions:  
(1 to 16); 1 limits to almost full recursion, 16 limits to no recursion  
KlfOfs  
X X X X  
The transfer curve of the de-interlacing filter coefficient is determined  
by the difference (Diff) between a line in the input field and the  
counterpart in the previous field shifted over the estimated motion  
vector. KlfOfs determines the bias of the transfer curve for the original  
input line, such that coefficient = KlfOfs + F(Diff), where the function F  
is calculated in the SAA4993H. The bias can take a value in the range  
(0 to 15), representing decreasing filter strength.  
Proscan2  
01D  
01E  
write; S  
write; S  
PlfLim  
X X X X limitation of recursion factor in calculation of interpolated line  
positions: (1 to 16); 1 limits to almost full recursion, 16 limits to no  
recursion  
PlfOfs  
Proscan3  
PeakLim  
X X X X  
see KlfOfs; this offset applies to interpolated lines  
X X X X Maximum that the peaked pixel is allowed to deviate from original pixel  
value: deviation (0 to 30 in steps of 2). Above this deviation, the  
peaked pixel is clipped to (original pixel + or − PeakLim).  
DeiOfs  
X X X X  
offset to bias between average and median in the initial de-interlacing,  
if the KplFad = MIX option is chosen  
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SNERT  
READ/  
NAME  
Proscan4  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
01F  
write; F  
PlfThr  
X X X Multiplier threshold at which to switch the lower limit of the filter  
coefficient for interpolated lines. Above this threshold, the differences  
corresponding to the two neighbouring lines are used as clipping  
parameters, below this threshold, the interpolated line difference is  
used as clipping level. This parameter can be used to optimize the  
de-interlacing quality in slowly moving edges; it is not likely to have  
effect if PlfLim is high.  
AdRecOut  
ProDiv  
X
select adaptive recursive or order statistic output (order statistic or  
adaptive)  
X X  
Scaling factor to control the strength of the filtering for the interpolated  
lines. A value 0 means no scaling (normal filtering), while 3 means  
scaling by factor 8 (very strong filtering). This parameter can be used  
to adjust the de-interlacing to varying level of noise in the input picture;  
use higher scaling for higher noise.  
KplOff  
X
disable all recursion in calculating pixels for frame memory (recursive  
or non recursive); to be true SAA4991WP and digital scan emulation  
modes  
Proscan5  
0CB  
write; S  
VecRbf  
X X X X Roll back factor on vectors used for motion-compensated  
de-interlacing. Values 0 to 14 (on a scale of 16) indicate attenuation.  
A value of 15 indicates no attenuation.  
FadDiv  
KplFad  
X X X  
sensitivity scaling factor in transition from average to median in initial  
de-interlacing  
X
chooses between majority selection and median/average mix for initial  
de-interlacing (majority or mix); when KplFad = 0, FadDiv and  
DeiOfs are don’t cares  
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SNERT  
READ/  
NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
General  
NrBlks  
020  
write; S  
NrBlks  
X X X X X X number of blocks in active video (6 to 53, corresponds to  
96 to 848 pixels), to be set as 1⁄16 (number of active pixels per  
line + 15); take remarks on TotalPxDiv8 into consideration  
TotalLnsAct98  
TotalLnsAct70  
TotalPxDiv8  
X X  
total number of output lines (bits 9 and 8)  
021  
022  
write; S  
write; S  
X X X X X X X X total number of output lines (bits 7 to 0)  
X X X X X X X X Total number of pixels per line divided-by-8 (80 to 128, corresponds to  
640 to 1024 pixels). The horizontal blanking interval is calculated as  
TotalPxDiv8 − 2 × NrBlks and has to be in the range from 12 to 124  
(corresponds to 96 to 992 pixels). Conclusion: TotalPxDiv8 has to be  
set to 12 + 2 × NrBlks < TotalPxDiv8 < 124 + 2 × NrBlks and NrBlks  
TotalPxDiv8 – 124  
-----------------------------------------------  
2
TotalPxDiv8 – 12  
--------------------------------------------  
2
has to be set to  
< NrBlks <  
REaShift  
023  
024  
write; S  
write; S  
X X X shift of RE_A signal in number of pixels  
(0, +1, +2, +3, −4, −3, −2 or −1)  
WEbdREceShift  
WEbdShift  
X X X shift of WE_B and WE_D signal in number of pixels  
(0, +1, +2, +3, −4, −3, −2 or −1)  
REceShift  
POR  
X X X  
shift of RE_C and RE_E signal in number of pixels  
(0, +1, +2, +3, −4, −3, −2 or −1)  
025  
0D6  
write; S  
write; S  
X power-on reset command, to be set high temporarily during start-up  
(normal or reset); note 3  
ScalingFactor  
X X X X X X X X 8-bit scaling factor for EggSliceMix, EggSliceRgt and global activity  
(the same factor for all registers).  
ScalingFactor  
output value (n+1) =  
× output value (n)  
------------------------------------  
128  
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SNERT  
READ/  
NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
Mode control  
Control1  
026  
write; F  
EstMode  
X Set estimator mode; 0 = line alternating use of left and right estimator:  
use in progressive scan except with vertical compress. 1 = field  
alternating use of left and right estimator: use in field doubling and  
progressive scan with vertical compress.  
FilmMode  
UpcMode  
X
set film mode; 0 = video camera mode; 1 = film mode  
X X  
select upconversion quality; 00 = full, 01 = economy (DPCM),  
10 = SAA4991WP, 11 = SAA4990H  
MatrixOn  
X
set matrix output mode; 1 = double output, disabling vertical peaking;  
0 = normal single output mode; this bit setting is the AND function of  
BusGControl bits  
EmbraceOn  
X
Master enable for embrace mode (off or on); SwapMpr in control2  
should be at ‘swap’ position to really cross-switch FM1 and FM3 field  
outputs. Should be set to logic 0 except in film mode and FM3 is  
present, or in SAA4991WP film mode and MemComp bit is active.  
MemComp  
X
set memory compression (luminance DPCM) (off or on)  
set memory decompression (luminance DPCM) (off or on)  
MemDecom  
X
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SNERT  
READ/  
NAME  
Control2  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
027  
write; F  
QQcurr  
X Quincunx phase of current field (in TPM) (phase0 or phase1); this  
needs to toggle each time a new field comes from FM1. In phase0 the  
estimator operates on a checker-board pattern that starts with the left  
upper block; in phase1 the other blocks are estimated.  
QQprev  
FldStat  
X
quincunx phase of previous field (in TPM) (phase0 or phase1); this is  
the value of QQcur during the last estimate written into the temporal  
prediction memory  
X
Field status (same input field or new input field); reflects whether  
the output of FM1 is a new or a repeated field. This bit will toggle field  
by field in field doubling mode and is continuously HIGH in progressive  
output mode.  
FieldWeYUV  
X
enable writing FM2 and FM3 for both luminance and chrominance  
(recirculation of data for luminance alone can be controlled with  
OrigFmEnY and IntpFmEnY in Control3) (off or on)  
OddFM1  
SwapMpr  
X
odd input field (even or odd), this is to be set equal to the detected  
field interlace for the field that comes out of FM1  
X
Swap multi port RAMs (normal or swap); this bit needs to be set to  
get real frame data at the temporal position from FM1. If swapped, the  
current field (FM1) will be stored in the right line memory tree, while  
the original lines from the stored frame (FM2/3) are stored in the left  
memory tree. Should be set only in film mode if FM3 is present;  
EmbraceOn must be set as well.  
VecOffs  
X X  
Set vertical vector offset (0, +1, − or −1) frame lines; vertical offset of  
the right line memory tree with respect to the left line memory tree.  
A higher offset value means: on the right memory tree access to less  
delayed video lines is taken; in interlaced video operation, the vertical  
offset will be −1 with an odd field on the left side and +1 with an even  
field on the left. With non-interlaced input, vertical offset should be  
constantly 0. In film mode, vertical offset is dynamically switched  
between +1, 0 and −1.  
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SNERT  
READ/  
NAME  
Control3  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
028  
write  
F
OddLeft  
X interlace (even or odd) phase of the field which is written to the left  
line memory tree (left MPRAM)  
OrigFmEnY  
X
enables writing luminance from de-interlacer in original field memory  
(FM2), otherwise recirculation of luminance that is just read from FM2  
(recirculate or update)  
IntpFmEnY  
FillTPM  
X
enables writing luminance from de-interlacer in interpolated field  
memory (FM3), otherwise recirculation of luminance that is just read  
from FM3 (recirculate or update)  
X
Enables writing in temporal prediction memory (keep or update);  
FillTPM should be set to ‘keep’ in SAA4991WP/film mode, in those  
output fields where FM1 and FM2 contain the same motion phase.  
FillTPM should be set to ‘update’ in all other situations.  
VertOffsDNR  
X X  
Set vertical vector offset of DNR (0, +1, − or −1) frame lines; vertical  
offset of the right line memory tree with respect to the left line memory  
tree, before the swap action. A higher offset value means: on the right  
memory tree access to less delayed video lines is taken; in interlaced  
video operation, the vertical offset will be −1 with an odd field on the  
left side and +1 with an even field on the left. With non-interlaced  
input, vertical offset should be constantly logic 0; in film mode, vertical  
offset is dynamically switched between +1, 0 and −1. It should be  
noted that the signal OddFM1 is used to determine this offset.  
BusGControl  
S
X X  
Select output mode of bus G; 00 = normal single output mode (bus G  
in 3-state), 01 = output of motion vectors to UVG (motion_x on U and  
motion_y on V), 10 = copy bus F to G, 11 = double output, disabling  
vertical peaking. Only when double output is selected, the MatrixOn  
bit in register Control1 should be set, otherwise it needs to be cleared.  
Upconversion  
Upconv1  
029  
write; F  
UpcShFac  
X X X X X X temporal interpolation factor used in luminance upconverter; value  
ranges from 0 (for current field position) to 32 (for previous field  
position)  
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SNERT  
READ/  
NAME  
Upconv2  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
02A  
write  
S
YVecClip  
X X X value used for coring the vertical vector component before application  
in the upconverter; range: 0 to 3.5 in steps of 0.5 line; should remain  
at logic 0 in normal operation  
RollBack  
F
X X X X X  
roll back factor ranging from 0 (use 0% of estimated vectors) to 16  
(use 100% of estimated vectors)  
Upconv3  
02B  
write; S  
MelzLfbm  
X SAA4991WP type local fallback method instead of more robust local  
fallback (complex or SAA4991WP type fallback)  
Melzmemc  
MelDeint  
MixCtrl  
X
SAA4991WP film mode memory control (normal or SAA4991WP  
type); should be set in SAA4991WP film mode to ensure that only  
original lines are selected as output when UpcShFac is 0 or 32  
X
use (as in SAA4991WP) horizontal motion compensated median for  
upconverter de-interlacing (normal or SAA4991WP type  
de-interlacing)  
X X X X X  
Bits 3 and 4 are used to control sensitivity to local vector smoothness  
(0 = sensitive to unsmoothness, 3 = hardly sensitive to  
unsmoothness). Bits 5 to 7 define the maximum contribution of  
non-motion compensated pixels to the output  
(0, 1⁄8, 2⁄8, 3⁄8, 4⁄8, 5⁄8, 6⁄8 or 7⁄8).  
UpcColShiFac  
0C4  
0C5  
write; F  
write; S  
X X X X X X temporal interpolation factor used in chrominance upconverter; value  
ranges from 0 (for current field position) to 32 (for previous field  
position)  
Upconv4  
LfIndex  
X X X Number of consecutive lines to have bad egg-slice values before  
upconverter goes into protection mode (0, 1, 2, 4, 8, 16, 32 or 64).  
A value of 0 switches off the possibility to go into protection.  
MCDemo  
X
mode switch on left side of the screen; 0 (natural motion); 1 (digital  
scan-like processing)  
EggSlice1  
0C6  
write; S  
EggStartLine  
X X X X X X X X Reference line number at which the egg slice measurement should  
start. SAA4993H defines a window internally as number of lines  
between EggStartLine and (MaxRefLine − EggStartLine).  
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SNERT  
READ/  
NAME  
EggSlice2  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
0C7  
write; S  
EggSlcThr  
X X X X X X Minimum line egg slice right value to activate reliability measurement.  
The parameter is multiplied internally by 4.  
EggRelInd  
X X  
the egg slice reliability is computed internally as  
EggSliceRgt (ESR) > RelFactor × EggSliceMix (ESM). RelFactor is  
determined by EggRelInd (2⁄8, 3⁄8, 4⁄8, or 6⁄8).  
SafeShiFac  
0C8  
02C  
write; F  
write; S  
X X X X X X upconverter shift factor to be used in protection mode; 0 (for current  
field position) to 32 (for previous field position)  
Motion estimator  
Motest1  
PenOdd  
X X X additional penalty on vector candidates with odd vertical component  
(0, 8, 16, 32, 64, 128, 256 or 511)  
SpcThr  
X X X  
Active when EstMode = 0; replace the spatial prediction of one  
estimator (left or right) by that of the other if the match error of the  
former exceeds that of the latter by more than (0, 8, 16, 32, 64, 128,  
256 or 511). A higher threshold means the two estimators are very  
independent.  
BmsThr  
X X  
Active when EstMode = 0; select as estimated vector the output of the  
right estimator unless its match error exceeds that of the left estimator  
by more than (0, 8, 16 or 32). This parameter should normally be set  
to logic 0.  
Motest2  
02D  
write; S  
TavLow  
X If the difference between the current vector and the previous one in  
the same spatial location is within a small window, then the two  
vectors are averaged to improve temporal consistency. TavLow is the  
lower threshold of this window (1 or 2).  
TavUpp  
MedEns  
X X  
see above; TavUpp is the upper threshold (0, 4, 8 or 16)  
X X  
scaling factor to reduce all sizes of update vectors in the ensemble  
with medium sized vector templates (1, 1⁄2, 1⁄4 or 1⁄8)  
LarEns  
X X  
scaling factor to reduce all sizes of update vectors in the ensemble  
with large sized vector templates (1, 1⁄2, 1⁄4 or 1⁄8)  
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SNERT  
READ/  
NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
Motest3  
MotShiFac  
02E  
write; F  
X X X X X X Motion estimator shift factor, being the temporal position used in the  
estimator at which the matching is done; value 32 for matching at  
previous field position down to 0 for matching at current field position.  
Keeping MotShiFac equal to UpShiFac in the next upconverted output  
field estimates for minimum matching errors (minimum Halo’s).  
MotShiFac at value 16 gives the largest natural vector range (twice as  
large as with value 0 or 32). Going above the range with  
MotShiFac ≠ 16 is dealt with in SAA4993H by shifting towards 16, but  
for the horizontal and vertical component separately (consequence is  
that vector candidates tend to rotate towards the diagonal directions).  
Motest4  
02F  
write; S  
PenRng  
X Penalty for vectors estimated on the first row and the first column (if  
left estimator is used) or the right column (if right estimator is used),  
whenever the spatial prediction candidate is selected (64 or 511).  
For noisy pictures, this register could be set to logic 1 to improve  
border processing in the estimator.  
CndSet  
X
choice of candidate set (left or right) for which data (Candidate1 to  
Candidate8) is written in this field (becomes active in next field);  
note 3  
ErrThr  
ErrHbl  
X X X  
threshold on block match error for considering a block to be bad  
(16, 32, 64, 128, 256, 512, 1024 or 2032)  
X X  
number of horizontally adjacent blocks that have to be all bad before  
considering an occurrence of a burst error (1, 2, 4 or 8) (counting of  
burst errors is read out with BlockErrCnt, address 0A8H)  
TstMod  
Motest5  
X
X
to be kept to logic 1 for normal operation  
0CC  
write; S  
ActOption  
X X selection of the vector component to take in the activity count  
( x + y , x , y or −)  
ClearTPM  
LoActThr  
HiActThr  
write zeros in the temporal prediction memory  
(no writing or writing zeros)  
0CD  
0CE  
write; S  
write; S  
X X X X X X X X blocks having an activity value below or equal to this threshold are  
counted as having LOW activity  
X X X X X X X X blocks having an activity value above this threshold are counted as  
having HIGH activity  
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SNERT  
READ/  
NAME  
LeftBorder  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
0CF  
write; S  
LeftBorder  
X X X X X X X estimator left border (in 8-pixel blocks)  
enable writing of null vectors outside estimators’ active window  
WinNullWrite  
X
(off or on)  
RightBorder  
TopBorder  
BottomBorder  
Candidate1  
Candidat1  
0D0  
0D1  
0D2  
090  
write; S  
write; S  
write; S  
write; S  
X X X X X X X estimator right border (in 8-pixel blocks)  
X X X X X X X estimator top border (in 4-line blocks)  
X X X X X X X estimator bottom border (in 4-line blocks)  
X X X selection Candidate1 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update1  
X X  
X X  
X X  
X X  
update for Candidate1 (zero update, medium update, large update  
or zero update)  
Penalty1  
Candidate2  
Candidat2  
X X X  
X X X  
X X X  
X X X  
penalty for Candidate1 (0, 8, 16, 32, 64, 128, 256 or 511)  
091  
092  
093  
write; S  
write; S  
write; S  
X X X selection Candidate2 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update2  
update for Candidate2 (zero update, medium update, large update  
or zero update)  
Penalty2  
Candidate3  
Candidat3  
penalty for Candidate2 (0, 8, 16, 32, 64, 128, 256 or 511)  
X X X selection Candidate3 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update3  
update for Candidate3 (zero update, medium update, large update  
or zero update)  
Penalty3  
Candidate4  
Candidat4  
penalty for Candidate3 (0, 8, 16, 32, 64, 128, 256 or 511)  
X X X selection Candidate4 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update4  
Penalty4  
update for Candidate4 (zero update, medium update, large update  
or zero update)  
penalty for Candidate4 (0, 8, 16, 32, 64, 128, 256 or 511)  
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SNERT  
READ/  
NAME  
Candidate5  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
094  
095  
096  
097  
write; S  
Candidat5  
X X X selection Candidate5 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update5  
X X  
X X  
X X  
X X  
update for Candidate5 (zero update, medium update, large update  
or zero update)  
Penalty5  
Candidate6  
Candidat6  
X X X  
X X X  
X X X  
X X X  
penalty for Candidate5 (0, 8, 16, 32, 64, 128, 256 or 511)  
write; S  
write; S  
write; S  
X X X selection Candidate6 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update6  
update for Candidate6 (zero update, medium update, large update  
or zero update)  
Penalty6  
Candidate7  
Candidat7  
penalty for Candidate6 (0, 8, 16, 32, 64, 128, 256 or 511)  
X X X selection Candidate7 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update7  
update for Candidate7 (zero update, medium update, large update  
or zero update)  
Penalty7  
Candidate8  
Candidat8  
penalty for Candidate7 (0, 8, 16, 32, 64, 128, 256 or 511)  
X X X selection Candidate8 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update8  
update for Candidate8 (zero update, medium update, large update  
or zero update)  
Penalty8  
penalty for Candidate8 (0, 8, 16, 32, 64, 128, 256 or 511)  
PZpositionLeftUppX  
098  
099  
write; S  
write; S  
write; S  
write; S  
write; F  
X X X X X X X position of LeftUpp measurement point for pan-zoom calculations  
(resolution: 16 pixels)  
PZpositionLeftUppY  
X X X X X X X Y position of LeftUpp measurement point for pan-zoom calculations  
(resolution: 4 lines)  
PZpositionRightLowX 09A  
PZpositionRightLowY 09B  
X X X X X X X position of RightLow measurement point for pan-zoom calculations  
(resolution: 16 pixels)  
X X X X X X X Y position of RightLow measurement point for pan-zoom calculations  
(resolution: 4 lines)  
PZvectorStartX  
09C  
X X X X X X X X X start value of pan-zoom vectors  
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SNERT  
READ/  
NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
PZvectorDeltaX  
PZvectorStartY  
PZvectorDeltaY  
09D  
09E  
09F  
write; F  
write; F  
write; F  
X X X X X X X X X delta value of pan-zoom vectors  
X X X X X X X X Y start value of pan-zoom vectors  
X X X X X X X X Y delta value of pan-zoom vectors  
Read data; note 3  
GlobalMSEmsb  
GlobalMSElsb  
0A0  
0A1  
read; F  
read; F  
X X X X X X X X Global Mean Square Error (MSE) = summation within a field period of  
squared differences in comparing vector shifted video from frame  
X X X X X X X X  
memory (FM2/3) with new field input (FM1) in those lines coinciding  
with new field lines. The window for the measurement is kept at  
40 pixels horizontal and 20 field lines vertical from the border of the  
video. Measurements is only done in fields where the de-interlacer is  
active, otherwise reading is zero. In field doubling mode, MSE is zero  
at the end of every new input field.  
GlobalMTImsb  
GlobalMTIlsb  
0A2  
0A3  
read; F  
read; F  
X X X X X X X X Global Motion Trajectory Inconsistency (MTI) = summation within a  
field period of squared differences comparing shifted video from frame  
X X X X X X X X  
memory (FM2/3 output) with filtered data that is rewritten to the frame  
memory (FM2/3 input) in those lines coinciding with new field lines.  
The window for the measurement is kept at 40 pixels horizontal and  
20 field lines vertical from the border of the video. Measurement is  
done only in fields where de-interlacer is active, otherwise reading is  
zero; in field doubling mode, MTI is zero at the end of every new input  
field.  
GlobalACTmsb  
GlobalACTlsb  
VectTempCons  
0A4  
0A5  
0A6  
read; F  
read; F  
read; F  
X X X X X X X X global activity (ACT) = summation over a field period of the horizontal  
plus the vertical components of the vectors of all blocks  
X X X X X X X X  
X X X X X X X X Vector temporal consistency = summation over a field period of  
absolute differences of horizontal plus vertical components of vectors  
newly estimated for each block compared with those vectors  
estimated in the previous run at the same spatial block position.  
It should be noted that a lower figure implies better consistency.  
VectSpatCons  
BlockErrCnt  
0A7  
0A8  
read; F  
read; F  
X X X X X X X X Vector spatial consistency = summation over a field period of absolute  
differences of horizontal and vertical components of vectors compared  
with those of the neighbour blocks (L, R, U and D); in the comparison,  
all vector data is used from the previous estimator run. It should be  
noted that a lower figure implies better consistency.  
X X X X X X X X burst error count (number of burst errors)  
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SNERT  
READ/  
NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
LeastErrSum  
0A9  
read; F  
X X X X X X X X least error sum (summation over a field period of the smallest match  
error that the estimator has found for each block: indicates reliability of  
the estimation process)  
YvecRangeErrCntmsb 0AA  
read; F  
X X X X X X X X Y vector range error count (number of vectors that have a vertical  
component that is out of range for upconversion at the chosen  
temporal position) (15 to 8)  
YvecRangeErrCntlsb 0AB  
read; F  
read; F  
write; F  
X X X X X X X X Y vector range error count (7 to 0)  
RefLineCountPrev  
RefLineCountNew  
0AC  
0AD  
X X X X X X X X read out of (number of input (run-) lines − 40) used in previous field  
X X X X X X X X Write of [number of input (run-) lines − 40] to be used in new field  
(actual maximum number of input lines in normal operation: 292;  
register value 252). Nominally this is to be set as an exact copy of the  
value read from RefLineCountPrev before a new field starts. In case  
the effective number of input (run-) lines has increased,  
RefLineCountNew should, for one field, be set to 255. This will occur  
e.g. with decreasing vertical zoom magnification or changing from  
525 lines video standard to 625 lines standard. If this is not done, a  
deadlock will occur with too few lines processed correctly by the  
motion estimator.  
PanZoomVec0-X  
PanZoomVec0-Y  
FalconIdent  
0B0  
0B1  
read; F  
read  
S
X X X X X X X X pan-zoom vector 0 (8-bit X value)  
0
SAA4993H identification: fixed bit, reading this bit as zero means  
SAA4993H is present  
PanZoomVec0-Y  
PanZoomVec1-X  
PanZoomVec1-Y  
StatusJump0  
F
X X X X X X X pan-zoom vector 0 (7-bit Y value)  
X X X X X X X X pan-zoom vector 1 (8-bit X value)  
0B2  
0B3  
read; F  
read  
S
X
read out of configuration pin JUMP0  
PanZoomVec1-Y  
PanZoomVec2-X  
PanZoomVec2-Y  
StatusJump1  
F
X X X X X X X pan-zoom vector 1 (7-bit Y value)  
0B4  
0B5  
read; F  
read  
S
X X X X X X X X pan-zoom vector 2 (8-bit X value)  
X
read out of configuration pin JUMP1  
PanZoomVec2-Y  
PanZoomVec3-X  
PanZoomVec3-Y  
F
X X X X X X X pan-zoom vector 2 (7-bit Y value)  
0B6  
0B7  
read; F  
read; F  
X X X X X X X X pan-zoom vector 2 (8-bit X value)  
X X X X X X X pan-zoom vector 3 (7-bit Y value)  
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SNERT  
READ/  
NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
PanZoomVec4-X  
PanZoomVec4-Y  
PanZoomVec5-X  
PanZoomVec5-Y  
PanZoomVec6-X  
PanZoomVec6-Y  
PanZoomVec7-X  
PanZoomVec7-Y  
PanZoomVec8-X  
PanZoomVec8-Y  
EggSliceRgtMSB  
EggSliceRgtLSB  
EggSliceMixMSB  
EggSliceMixLSB  
SafeFbLine  
0B8  
0B9  
0BA  
0BB  
0BC  
0BD  
0BE  
0BF  
0AE  
0AF  
0C0  
0C1  
0C2  
0C3  
0C9  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
X X X X X X X X pan-zoom vector 4 (8-bit X value)  
X X X X X X X pan-zoom vector 4 (7-bit Y value)  
X X X X X X X X pan-zoom vector 5 (8-bit X value)  
X X X X X X X pan-zoom vector 5 (7-bit Y value)  
X X X X X X X X pan-zoom vector 6 (8-bit X value)  
X X X X X X X pan-zoom vector 6 (7-bit Y value)  
X X X X X X X X pan-zoom vector 7 (8-bit X value)  
X X X X X X X pan-zoom vector 7 (7-bit Y value)  
X X X X X X X X pan-zoom vector 8 (8-bit X value)  
X X X X X X X pan-zoom vector 8 (7-bit Y value)  
X X X X X X X X result of right pixels egg-slice detector (15 to 8)  
X X X X X X X X result of right pixels egg-slice detector (7 to 0)  
X X X X X X X X result of mixed pixels egg-slice detector (15 to 8)  
X X X X X X X X result of mixed pixels egg-slice detector (7 to 0)  
X X X X X X X X reference line number (divided by two) at which the upconverter goes  
into protection mode  
EggBinGoodness  
0CA  
read; F  
X X X X X X X X Goodness of the four egg-slice sections, from top to bottom, 2 bits per  
section. Each section is represented with 2 bits in this register, where  
bits 0 and 1 represent the top section and bits 6 and 7 represent the  
lowest of the 4 sections. Each pair of bits indicate  
00 = (ESR > 3⁄4ESM), 01 = (1⁄2ESM < ESR ≤ 3⁄4ESM),  
10 = (1⁄4ESM < ESR ≤ 1⁄2ESM), 11 = (ESR ≤ 1⁄4ESM).  
LoActCnt  
HiActCnt  
0D3  
0D4  
0D5  
read; F  
read; F  
read; F  
X X X X X X X X number of blocks having low activity  
X X X X X X X X number of blocks having high activity  
NullErrSum  
X X X X X X X X sum of errors for the null candidate over the complete field; when no  
null candidate is selected a value of 0xFF will be read  
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Notes  
1. S means semi static, used at initialization or mode changes; F means field frequent, in general updated in each display field.  
2. Selectable items are marked bold.  
3. Almost all of the R(ead) and W(rite) registers of SAA4993H are double buffered. The Write registers are latched by a signal called New_field.  
New_field gets set, when RE_F rises after RSTR (New_field is effectively at the start of active video). The Read registers are latched by a signal  
called Reg_upd. Reg_upd gets set, when half the number of active pixels of the fourth line of vertical blanking have entered the SAA4993H  
(Reg_upd will effectively be active 31⁄2 lines after the RE_A, RE_C and RE_E have ended). The only exception are the registers which are not  
double buffered, these are as follows:  
a) Write register 025H: power_on_reset  
b) Write register 02FH, bit 1: CndSet  
c) Read register 0B0H to 0BFH, 0AEH and 0AFH: pan_zoom_vectors, including FalconIdent (= 0), StatusJump0 and StatusJump1.  
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
9
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
SYMBOL PARAMETER MIN.  
VDDI core supply voltage  
MAX.  
UNIT  
−0.5  
−0.5  
−
+2.7  
+3.6  
600  
4
V
VDDE  
IDD  
Io  
external supply voltage (output pads)  
supply current  
V
mA  
mA  
V
output current  
−
Vi  
input voltage for all I/O pins  
storage temperature  
junction temperature  
−0.5  
−40  
0
+3.6  
+125  
125  
Tstg  
Tj  
°C  
°C  
10 THERMAL CHARACTERISTICS  
SYMBOL  
Rth(j-a)  
Rth(j-c)  
PARAMETER  
thermal resistance from junction to ambient in free air  
thermal resistance from junction to case  
CONDITIONS  
VALUE  
UNIT  
27  
K/W  
K/W  
2.9  
11 CHARACTERISTICS  
DDE = 3.0 to 3.6 V; Tamb = 0 to 70 °C; unless otherwise specified.  
V
SYMBOL  
Supplies  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
VDDI  
VDDE  
IDD  
core supply voltage  
2.3  
2.5  
2.7  
V
external supply voltage (output pads)  
supply current  
3.0  
3.3  
3.6  
V
−
280  
−
mA  
General  
VOH  
VOL  
VIH  
VIL  
HIGH-level output voltage  
LOW-level output voltage  
HIGH-level input voltage  
LOW-level input voltage  
HIGH-level output current  
2.4  
−
−
−
−
−
−
−
V
0.4  
−
V
2
V
−
0.8  
−
V
IOH  
10 ns slew rate  
output;  
−4  
mA  
VOH = 2.4 V  
IOL  
LOW-level output current  
10 ns slew rate  
output;  
4
−
−
mA  
VOL = 0.4 V  
CL  
Ci  
load capacitance  
input capacitance  
input leakage current  
−
−
−
−
−
−
50  
8
pF  
pF  
µA  
ILI  
1
2001 Nov 23  
31  
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Outputs; see Fig.5; note 1  
IOZ  
output current in 3-state mode  
output delay time (except pin RESFM)  
output hold time (except pin RESFM)  
slew rate  
−0.5 < Vo < 3.6  
−
−
4
−
−
−
−
1
µA  
td(o)  
th(o)  
SR  
21  
−
ns  
ns  
300  
700  
mV/ns  
Inputs; see Fig.5; note 2  
tsu(i) input set-up time  
th(i) input hold time  
Input CLK32; see Fig.5  
6
2
−
−
−
−
ns  
ns  
tr  
rise time  
fall time  
−
−
−
−
−
4
ns  
ns  
%
tf  
−
4
δ
duty factor  
cycle time  
40  
30  
60  
39  
Tcy  
ns  
BST interface; see Fig.6  
Tcy(BST)  
tsu(i)(BST)  
th(i)(BST)  
th(o)(BST)  
td(o)(BST)  
BST cycle time  
−
3
6
4
−
1
−
−
−
−
−
µs  
ns  
ns  
ns  
ns  
input set-up time  
input hold time  
output hold time  
output delay  
−
−
−
30  
SNERT interface; see Fig.7  
tSNRST(H)  
td(SNRST-SNCL)  
Tcy(SNCL)  
tsu(i)(SNCL)  
th(i)(SNCL)  
th(o)  
SNRST pulse HIGH time  
500  
200  
0.5  
53  
−
−
−
−
−
−
−
−
−
ns  
ns  
µs  
ns  
ns  
ns  
ns  
ns  
delay SNRST pulse to SNCL LOW time  
SNCL cycle time  
−
1
input set-up time to SNCL  
input hold time to SNCL  
output hold time  
−
10  
−
30  
−
td(o)  
output delay  
−
330  
−
to(en)  
output enable time  
210  
Notes  
1. Timing characteristics are measured with CL = 15 pF; IOL = 2 mA; RL = 2 kΩ.  
2. All inputs except SNERT interface inputs, CLK32 input and BST/TEST inputs.  
2001 Nov 23  
32  
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
t
t
r
f
90%  
10%  
90%  
10%  
CLOCK  
1.5 V  
INPUT  
DATA  
MHB175  
t
t
su(i)  
h(i)  
OUTPUT  
DATA  
data  
valid  
data transition  
period  
t
h(o)  
t
d(o)  
Fig.5 Data input/output timing diagram.  
T
cy(BST)  
TCK  
TDI, TMS  
TDO  
MHB649  
t
t
su(i)(BST)  
h(o)(BST)  
h(i)(BST)  
t
t
d(o)(BST)  
Fig.6 Boundary scan test interface timing diagram.  
33  
2001 Nov 23  
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
SNCL  
write sequence:  
a0  
a0  
a1  
a1  
a2  
a2  
a3  
a3  
a4  
a4  
a5  
a5  
a6  
a6  
a7  
a7  
w0  
w1  
w2  
w3  
w4  
w5  
w6  
w7  
SNDA  
read sequence:  
SNDA  
driven by  
master  
r0  
r1  
r2  
r3  
r4  
r5  
r6  
r7  
SNDA  
driven by  
SAA4993H  
SNCL  
50%  
50%  
50%  
t
t
h(i)(SNCL)  
su(i)(SNCL)  
a6  
write sequence:  
SNDA  
a7  
w0  
w1  
read sequence:  
SNDA  
driven by  
master  
a6  
a7  
t
t
h(o)  
o(en)  
SNDA  
driven by  
SAA4993H  
r0  
r1  
t
t
d(o)  
MHC058  
d(o)  
Fig.7 SNERT interface timing diagram.  
2001 Nov 23  
34  
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
Table 2 YUV formats  
FORMAT(2)  
I/O PIN(1)  
4 : 1 : 1  
4 : 2 : 2  
4 : 2 : 2 DPCM  
YX7  
YX6  
Y07  
Y06  
Y05  
Y04  
Y03  
Y02  
Y01  
Y00  
U07  
U06  
V07  
V06  
−
Y17  
Y16  
Y15  
Y14  
Y13  
Y12  
Y11  
Y10  
U05  
U04  
V05  
V04  
−
Y27  
Y26  
Y25  
Y24  
Y23  
Y22  
Y21  
Y20  
U03  
U02  
V03  
V02  
−
Y37  
Y07  
Y06  
Y05  
Y04  
Y03  
Y02  
Y01  
Y00  
U07  
U06  
U05  
U04  
U03  
U02  
U01  
U00  
Y17  
Y16  
Y15  
Y14  
Y13  
Y12  
Y11  
Y10  
V07  
V06  
V05  
V04  
V03  
V02  
V01  
V00  
Y07  
Y06  
Y05  
Y04  
Y03  
Y02  
Y01  
Y00  
UC03  
UC02  
UC01  
UC00  
−
Y17  
Y16  
Y15  
Y14  
Y13  
Y12  
Y11  
Y10  
VC03  
VC02  
VC01  
VC00  
−
Y36  
Y35  
Y34  
Y33  
Y32  
Y31  
Y30  
U01  
U00  
V01  
V00  
−
YX5  
YX4  
YX3  
YX2  
YX1  
YX0  
UVX7  
UVX6  
UVX5  
UVX4  
UVX3  
UVX2  
UVX1  
UVX0  
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Notes  
1. Digit X refers to different I/O buses:  
a) A = input from 1st field memory  
b) B = output to 2nd field memory  
c) C = input from 2nd field memory  
d) D = output to 3rd field memory  
e) E = input from 3rd field memory  
f) F = main output  
g) G = 2nd output for matrix purposes.  
2. The first index digit defines the sample number and the second defines the bit number.  
2001 Nov 23  
35  
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
12 PACKAGE OUTLINE  
QFP160: plastic quad flat package;  
160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height  
SOT322-2  
y
X
A
120  
121  
81  
80  
Z
E
e
A
2
H
A
E
E
A
(A )  
3
1
θ
w M  
p
L
p
b
L
pin 1 index  
detail X  
41  
160  
1
40  
Z
w M  
D
v M  
A
b
p
e
D
B
H
v M  
B
D
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.  
7o  
0o  
0.50 3.60  
0.25 3.20  
0.38 0.23 28.1 28.1  
0.22 0.13 27.9 27.9  
31.45 31.45  
30.95 30.95  
1.03  
0.73  
1.5  
1.1  
1.5  
1.1  
mm  
4.07  
0.25  
0.13 0.1  
0.65  
1.6  
0.3  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
99-11-03  
00-01-19  
SOT322-2  
135E12  
MS-022  
2001 Nov 23  
36  
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
13 SOLDERING  
If wave soldering is used the following conditions must be  
observed for optimal results:  
13.1 Introduction to soldering surface mount  
packages  
• Use a double-wave soldering method comprising a  
turbulent wave with high upward pressure followed by a  
smooth laminar wave.  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “Data Handbook IC26; Integrated Circuit Packages”  
(document order number 9398 652 90011).  
• For packages with leads on two sides and a pitch (e):  
– larger than or equal to 1.27 mm, the footprint  
longitudinal axis is preferred to be parallel to the  
transport direction of the printed-circuit board;  
There is no soldering method that is ideal for all surface  
mount IC packages. Wave soldering can still be used for  
certain surface mount ICs, but it is not suitable for fine pitch  
SMDs. In these situations reflow soldering is  
recommended.  
– smaller than 1.27 mm, the footprint longitudinal axis  
must be parallel to the transport direction of the  
printed-circuit board.  
The footprint must incorporate solder thieves at the  
downstream end.  
13.2 Reflow soldering  
• For packages with leads on four sides, the footprint must  
be placed at a 45° angle to the transport direction of the  
printed-circuit board. The footprint must incorporate  
solder thieves downstream and at the side corners.  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
Several methods exist for reflowing; for example,  
convection or convection/infrared heating in a conveyor  
type oven. Throughput times (preheating, soldering and  
cooling) vary between 100 and 200 seconds depending  
on heating method.  
Typical dwell time is 4 seconds at 250 °C.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
Typical reflow peak temperatures range from  
215 to 250 °C. The top-surface temperature of the  
packages should preferable be kept below 220 °C for  
thick/large packages, and below 235 °C for small/thin  
packages.  
13.4 Manual soldering  
Fix the component by first soldering two  
diagonally-opposite end leads. Use a low voltage (24 V or  
less) soldering iron applied to the flat part of the lead.  
Contact time must be limited to 10 seconds at up to  
300 °C.  
13.3 Wave soldering  
Conventional single wave soldering is not recommended  
for surface mount devices (SMDs) or printed-circuit boards  
with a high component density, as solder bridging and  
non-wetting can present major problems.  
When using a dedicated tool, all other leads can be  
soldered in one operation within 2 to 5 seconds between  
270 and 320 °C.  
To overcome these problems the double-wave soldering  
method was specifically developed.  
2001 Nov 23  
37  
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
13.5 Suitability of surface mount IC packages for wave and reflow soldering methods  
SOLDERING METHOD  
PACKAGE  
WAVE  
not suitable  
REFLOW(1)  
BGA, HBGA, LFBGA, SQFP, TFBGA  
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS  
PLCC(3), SO, SOJ  
suitable  
not suitable(2)  
suitable  
suitable  
suitable  
LQFP, QFP, TQFP  
not recommended(3)(4) suitable  
not recommended(5)  
suitable  
SSOP, TSSOP, VSO  
Notes  
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum  
temperature (with respect to time) and body size of the package, there is a risk that internal or external package  
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the  
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.  
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink  
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).  
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.  
The package footprint must incorporate solder thieves downstream and at the side corners.  
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;  
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is  
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.  
2001 Nov 23  
38  
Philips Semiconductors  
Product specification  
Field and line rate converter  
with noise reduction  
SAA4993H  
14 DATA SHEET STATUS  
PRODUCT  
DATA SHEET STATUS(1)  
STATUS(2)  
DEFINITIONS  
Objective data  
Development This data sheet contains data from the objective specification for product  
development. Philips Semiconductors reserves the right to change the  
specification in any manner without notice.  
Preliminary data  
Qualification  
This data sheet contains data from the preliminary specification.  
Supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to change the specification without  
notice, in order to improve the design and supply the best possible  
product.  
Product data  
Production  
This data sheet contains data from the product specification. Philips  
Semiconductors reserves the right to make changes at any time in order  
to improve the design, manufacturing and supply. Changes will be  
communicated according to the Customer Product/Process Change  
Notification (CPCN) procedure SNW-SQ-650A.  
Notes  
1. Please consult the most recently issued data sheet before initiating or completing a design.  
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was  
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.  
15 DEFINITIONS  
Semiconductors customers using or selling these products  
for use in such applications do so at their own risk and  
agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Short-form specification  
The data in a short-form  
specification is extracted from a full data sheet with the  
same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
Right to make changes  
Philips Semiconductors  
reserves the right to make changes, without notice, in the  
products, including circuits, standard cells, and/or  
software, described or contained herein in order to  
improve design and/or performance. Philips  
Semiconductors assumes no responsibility or liability for  
the use of any of these products, conveys no licence or title  
under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that  
these products are free from patent, copyright, or mask  
work right infringement, unless otherwise specified.  
Limiting values definition Limiting values given are in  
accordance with the Absolute Maximum Rating System  
(IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device.  
These are stress ratings only and operation of the device  
at these or at any other conditions above those given in the  
Characteristics sections of the specification is not implied.  
Exposure to limiting values for extended periods may  
affect device reliability.  
Application information  
Applications that are  
ICs with field conversion functionality Purchase of a  
Philips IC with field conversion functionality does not  
convey any implied license under any Intellectual Property  
Right to use this IC in any field conversion application,  
such as but not limited to a TV set having a display with a  
100 Hz field refresh rate. A license can be obtained via the  
Philips Corporate Intellectual Property department. For  
more information, please contact Philips Corporate  
Intellectual Property, Attn. Patent Licensing Manager, P.O.  
Box 220, 5600 AE Eindhoven, The Netherlands, email:  
licensing.cip@philips.com.  
described herein for any of these products are for  
illustrative purposes only. Philips Semiconductors make  
no representation or warranty that such applications will be  
suitable for the specified use without further testing or  
modification.  
16 DISCLAIMERS  
Life support applications  
These products are not  
designed for use in life support appliances, devices, or  
systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips  
2001 Nov 23  
39  
Philips Semiconductors – a worldwide company  
Contact information  
For additional information please visit http://www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.  
© Koninklijke Philips Electronics N.V. 2001  
SCA73  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
753504/01/pp40  
Date of release: 2001 Nov 23  
Document order number: 9397 750 08704  

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