SAA4997H [NXP]
VErtical Reconstruction IC VERIC for PALplus; 垂直重建IC VERIC的PALplus
| 型号： | SAA4997H |
| 厂家： | 
NXP |
| 描述： | VErtical Reconstruction IC VERIC for PALplus |
| 文件： | 总28页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA4997H
VErtical Reconstruction IC (VERIC)
for PALplus
1996 Oct 24
Preliminary specification
File under Integrated Circuits, IC02
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
FEATURES
GENERAL DESCRIPTION
• PALplus decoding
The VErtical Reconstruction IC (VERIC) for PALplus
(VERIC) is especially designed for use in conjunction with
the Motion Adaptive Colour Plus And Control IC
(MACPACIC) to decode the transmitted PALplus video
signal in PALplus colour TV receivers. It provides the full
vertical resolution of a PALplus picture from the letter box
part and the decoded helper information.
• Vertical reconstruction
• Quadrature mirror filter
• Luminance and chrominance processing
• Controlling.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
MAX.
5.25
70
UNIT
VDD
supply voltage
−
V
Tamb
operating ambient temperature
0
°C
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
SAA4997H QFP64
plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm SOT319-2
1996 Oct 24
2
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
BLOCK DIAGRAMS
GM4E3
1996 Oct 24
3
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
GME4
o
1996 Oct 24
4
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
PINNING
SYMBOL
Y_VE_1
PIN
TYPE
output
DESCRIPTION
1
2
luminance output data bit 1
luminance output data bit 0
Y_VE_0
U_VE_1
U_VE_0
V_VE_1
V_VE_0
VSS1
output
output
output
output
output
input
input
−
3
chrominance output data bit 1 U-component
chrominance output data bit 0 U-component
chrominance output data bit 1 V-component
chrominance output data bit 0 V-component
ground 1
4
5
6
7
VDD1
8
positive supply voltage 1 (+5 V)
not connected
n.c.
9
n.c.
10
11
12
13
14
15
16
17
18
19
20
−
not connected
n.c.
−
not connected
n.c.
−
not connected
n.c.
−
not connected
n.c.
−
not connected
n.c.
−
not connected
n.c.
−
not connected
HREF_MA
n.c.
input
−
horizontal reference
not connected
VA_AI
INTPOL
input
input
vertical reference pulse related to output data
INTPOL = 1: PALplus interpolation active
INTPOL = 0: VERIC switched to bypass mode (standard signal)
FILM = 0: CAMERA mode
FILM
21
22
input
input
FILM = 1: FILM mode
EVEN_FIELD
EVEN_FIELD = 0: odd field related to MACPACIC input data
EVEN_FIELD = 1: even field related to MACPACIC input data
buffered clock input (16 MHz)
ground 2
CLK_16B2
VSS2
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
input
input
input
input
input
input
output
input
−
VDD2
positive supply voltage 2 (+5 V)
boundary scan test clock input
boundary scan test mode select input
boundary scan test data input
boundary scan test data output
boundary scan test reset input
not connected
TCK
TMS
TDI
TDO_VE
TRSTN
n.c.
n.c.
−
not connected
TEST1
TEST2
TEST3
CLK_32B3
VSS3
tbf
test pins
tbf
tbf
input
input
buffered clock input (32 MHz)
ground 3
1996 Oct 24
5
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
SYMBOL
VDD3
PIN
TYPE
input
DESCRIPTION
positive supply voltage 3 (+5 V)
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
OE_FM3
RE_FM3
V_FM23_1
V_FM23_0
U_FM23_1
U_FM23_0
Y_FM23_7
Y_FM23_6
Y_FM23_5
Y_FM23_4
Y_FM23_3
n.c.
output
output
input
input
input
input
input
input
input
input
input
−
output enable field memory 3
read enable field memory 3
chrominance input data bit 1 V-component
chrominance input data bit 0 V-component
chrominance input data bit 1 U-component
chrominance input data bit 0 U-component
Y input data bit 7
Y input data bit 6
Y input data bit 5
Y input data bit 4
Y input data bit 3
not connected
Y_FM23_2
Y_FM23_1
Y_FM23_0
RSTR_FM23
RE_FM2
OE_FM2
VDD4
input
input
input
output
output
output
input
input
output
output
output
output
output
output
Y input data bit 2
Y input data bit 1
Y input data bit 0
reset read field memory 2 and 3
read enable field memory 2
output enable field memory 2
positive supply voltage 4 (+5 V)
ground 4
VSS4
Y_VE_7
luminance output data bit 7
luminance output data bit 6
luminance output data bit 5
luminance output data bit 4
luminance output data bit 3
luminance output data bit 2
Y_VE_6
Y_VE_5
Y_VE_4
Y_VE_3
Y_VE_2
1996 Oct 24
6
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
Y_VE_1
Y_VE_0
U_VE_1
U_VE_0
V_VE_1
V_VE_0
1
2
3
4
5
6
7
8
9
51 Y_FM23_2
50 n.c.
49 Y_FM23_3
48 Y_FM23_4
47 Y_FM23_5
46 Y_FM23_6
45 Y_FM23_7
44 U_FM23_0
V
SS1
V
DD1
n.c.
U_FM23_1
42 V_FM23_0
V_FM23_1
43
n.c. 10
n.c. 11
SAA4997H
41
n.c. 12
40 RE_FM3
39 OE_FM3
n.c. 13
n.c. 14
38
37
V
V
DD3
SS3
n.c. 15
n.c 16
36 CLK_32B3
35 TEST3
34 TEST2
33 TEST1
HREF_MA 17
n.c. 18
VA_AI 19
MGE442
Fig.3 Pin configuration.
7
1996 Oct 24
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
The luminance vertical conversion process in the decoder
is complementary to that of the encoder.
FUNCTIONAL DESCRIPTION
Introduction
In the decoder the inverse QMF function is implemented to
recombine the two separated sub-bands and to generate
the original video signal with 576 active lines per frame.
As shown in Fig.2 the PALplus module consists of two
special integrated circuits:
• Motion Adaptive Colour Plus And Control IC
(MACPACIC)
Each output line is calculated from up to seven input lines
stored in line memories containing main or helper
information. The various lines are multiplied by switched
coefficients, changing every line within a sequence of four
lines, depending on the specific mode (CAMERA or FILM).
• VErtical Reconstruction IC (VERIC)
and four field memories TMS4C2970.
The MACPACIC and the VERIC are intended to generate
digitally decoded 50 Hz YUV signals. The MACPACIC
performs the decompanding function for the helper lines
and the motion adaptive luminance/chrominance
separation. Furthermore, PALplus system controlling,
memory controlling and clock generation are carried out in
this circuit.
In case of standard PAL reception, the VERIC is switched
to bypass mode controlled by the signal INTPOL.
For multi-PIP processing the VERIC is also switched to
bypass mode, but controlling of FM2/3 is different (see
Fig.6). The total signal delay between the MACPACIC
input and the VERIC output is one line for this mode.
FM2/3 are driven with 32 MHz clock frequency.
The non-multiplexed input data are clocked out with
16 MHz.
The function of the VERIC is to reconstruct the separated
2 × 72 helper lines and the 430 main lines into a standard
576 lines frame according the PALplus system description
“REV 2.0”. Chrominance is converted from 430 lines to
576 lines using a vertical sample rate converter.
Chrominance processing
The chrominance processing is carried out by the vertical
interpolation filter (poly phase filter).
The data of the VERIC are clocked out with 16 MHz.
The Y : U : V bandwidth ratio is 4 : 1 : 1.
In CAMERA and FILM mode, intra-field vertical sample
rate conversion is carried out.
The functional block diagram of the VERIC is shown in
Fig.1. The device consists of 3 main parts:
• Luminance processing
• Chrominance processing
• Controlling.
One output line is calculated out of three or four lines in
CAMERA or FILM mode using different coefficients or
passed through in bypass mode.
The input data are delivered by the field memories FM2
and FM3, which include multiplexed first and second field
data processed by the MACPACIC. The luminance and
chrominance input data of the VERIC are clocked with
32 MHz (CLK_32B3). Internally the device operates at
32 or 16 MHz clock frequency.
Control functions
The VERIC controller generates the necessary internal
control signals for the line memories, formatters,
reformatters, the selector signals for the multiplexers and
the read signals for the field memories FM2/3.
The system control input signals EVEN_FIELD, INTPOL
and FILM are derived from the control part of the
MACPACIC. The field selection information EVEN_FIELD
is related to the input data of the MACPACIC and is
adapted in the VERIC to its input data.
Luminance processing
In the PALplus encoder the luminance signal is separated
vertically into two sub-bands by a special Quadrature
Mirror Filter (QMF).
The control functions are described in Tables 1 and 2.
A vertical low-pass sub-band consists of the 430 main
letter box lines per frame, and a vertical high-pass
sub-band includes the 144 helper lines per frame.
Table 1 EVEN_FIELD
VALUE
STATUS
The used QMF technique has two advantages:
EVEN_FIELD = 1
EVEN_FIELD = 0
even field selected
odd field selected
• Essentially loss-free data processing
• Cancellation of alias components in the main and helper
signal in the decoder.
1996 Oct 24
8
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
Table 2 INTPOL and FILM
Table 3 Delays
VALUE
STATUS
bypass mode;
MODE
FIELD
VERIC I/O DELAY
INTPOL = 0 FILM = 0
FILM mode
first
second
CAMERA mode first
second
2 lines
3 lines
3 lines
4 lines
standard signals
INTPOL = 1 FILM = 0
interpolation active;
PALplus CAMERA mode
INTPOL = 0 FILM = 1
INTPOL = 1 FILM = 1
bypass mode; multi-PIP
interpolation active;
PALplus FILM mode
Input/Output formats
INPUT FORMATS
Modes and delays
The luminance input range of the main and helper signal
has the following values:
The PALplus module can operate in two different
hardware configurations:
Main signal: black = 16, white = 191 (straight binary)
Helper signal: ±70, mid = 128 (straight binary)
• Full PALplus configuration (MACPACIC and VERIC)
• Stand alone MACPACIC.
Chrominance format: ±90, mid = 0 (two’s complement).
The vertical interpolation of the VERIC can be activated by
the signal INTPOL depending on the PALplus signalling
bits, transmitted in line 23 indicating the type of signal
being received.
OUTPUT FORMATS
Luminance format: black = 16, white = 191 (straight
binary)
Blanking: code 16
However, the delay between input data of the MACPACIC
and output data of the VERIC always has to be 1.5 fields.
This is achieved with a suitable read timing of the field
memories FM2 and FM3 controlled by VA_AI which is
derived from the field length measurement in the
MACPACIC.
Chrominance format: ±90, mid = 0 (two’s complement)
Blanking: code 0.
Test activities
The pins TEST1, TEST2 and TEST3 are provided to
perform the IC test activities, such as scan test.
In case of INTPOL = LOW and additionally FILM = HIGH
(FILM mode), the VERIC is switched to multi-PIP mode.
In case the delay between input of the MACPACIC and
output of the VERIC is one line (1024 CLK_16 periods).
The pins TRSTN, TDI, TMS, TCK and TDO_VE are
intended for a boundary scan test.
The line and pixel timings of the VERIC are shown in
Figures 5 to 14.
1996 Oct 24
9
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
DC CHARACTERISTICS
Tj = 0 to 125 °C
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
supply voltage
4.75
5.0
−
5.25
V
DD
I
supply current
VDD = 5 V
−
−
80
mA
DD
DD(q)
I
quiescent supply current
all inputs to VDD or VSS
−
100
µA
Inputs
V
V
LOW level input voltage
HIGH level input voltage
input leakage current
−0.5
2.0
−
−
−
−
+0.8
VDD
1.0
V
IL
V
IH
I
LI
µA
Outputs
V
V
LOW level output voltage
HIGH level output voltage
LOW level output current
HIGH level output current
IO = 20 µA
−
−
0.1
−
V
OL
IO = 20 µA
V
DD − 0.1 −
V
OH
I
I
VO = 0.5 V
4.0
4.0
−
−
−
mA
mA
OL
OH
VO = VDD − 0.5 V
−
AC CHARACTERISTICS
Tj = 0 to 125 °C
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clock timing CLK_32B3 (see Fig.4)
TCY(32)
cycle time
28.1
9.2
9.2
2.0
2.0
−10
31.25
−
ns
ns
ns
ns
ns
%
tH
tL
HIGH time
−
−
−
−
−
−
LOW time
−
t
r
t
f
rise time
4.0
4.0
+10
fall time
∆fclk
deviation of clock frequency
Clock timing CLK_16B2 (see Fig.4)
TCY(16)
cycle time
HIGH time
LOW time
rise time
56.2
20.5
20.5
2.0
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
%
tH
tL
−
−
t
r
t
f
4.0
4.0
50
fall time
4.0
δ
duty cycle
40
tH
δ =
----
tL
1996 Oct 24
10
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input data timing (CLK_32)
t
t
input data set-up time
CLK_16B2
su
−4.7
−
−
−
−
ns
Y and UV_FM23
input data hold time
CLK_16B2
−0.8
ns
h(i)
5.1
5.2
−
−
−
−
ns
ns
Y and UV_FM23
Input control timing (CLK_16B2)
HREF_MA, VA_AI, FILM, EVEN_FIELD AND INTPOL
t
t
input data set-up time
input data hold time
4.5
0.1
−
−
−
−
ns
ns
su
h(i)
Output data timing (CLK_16B2)
Y AND UV_FM23
t
t
output data hold time
output data delay time
CL = 15 pF
CL = 15 pF
8
−
−
−
ns
ns
h(o)
−
27
d(o)
Output control timing (CLK_32B3)
OE_FM2, OE_FM3, RE_FM2, RE_FM3 AND RSTR_FM23
t
t
output data hold time
output data delay time
CL = 15 pF
CL = 15 pF
5
−
−
−
ns
ns
h(o)
−
20
d(o)
Delays
t
t
HREF_MA pulse width
−
−
60 × TCY(16)
−
−
ns
ns
w(HREF)
delay
127 × TCY(32)
d(RE)
RE_FM2/3 to HREF_MA
t
t
t
t
t
t
RE_FM2/3 pulse width
delay HREF_MA to YUV_VE
delay data input to output
delay data input to output
delay RSTR
−
−
−
−
−
−
1680 × TCY(32)
80 × TCY(16)
16 × TCY(16)
2 × TCY(16)
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
w(RE)
d(VE)(MA)
d(VE)
multi-PIP
multi-PIP
multi-PIP
d(VE)
2016 × TCY(32)
2040 × TCY(32)
d(RSTR)
d(FM2)
delay FM2 input to output
1996 Oct 24
11
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
TIMING
t
t
r
f
90%
50%
CLK
10%
t
t
H
L
XX
DATA/CONTROL
Dn
D(n+1)
t
t
h(i)
h(o)
t
t
su
d(o)
MGE445
Data input: CLK = CLK_32B3
Data output: CLK = CLK_16B2
Control input: CLK = CLK_16B2
Control output: CLK = CLK_32B3
Fig.4 Data/control input/output set-up and hold timing.
1996 Oct 24
12
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
GM4E6
1996 Oct 24
13
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
GM4E7
1996 Oct 24
14
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
GM4E8
1996 Oct 24
15
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
GM4E9
1996 Oct 24
16
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
GM4E50
1996 Oct 24
17
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
GM4E51
1996 Oct 24
18
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
GM4E52
u
1996 Oct 24
19
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
GM4E53
1996 Oct 24
20
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
GM5E4
1996 Oct 24
21
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
GM4E5
1996 Oct 24
22
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
PACKAGE OUTLINE
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT319-2
y
X
A
51
33
52
32
Z
E
e
Q
A
2
H
A
E
(A )
3
E
A
1
θ
w M
p
pin 1 index
L
p
b
L
20
64
detail X
1
19
w M
Z
D
v
M
A
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.25 2.90
0.05 2.65
0.50 0.25 20.1 14.1
0.35 0.14 19.9 13.9
24.2 18.2
23.6 17.6
1.0
0.6
1.4
1.2
1.2
0.8
1.2
0.8
mm
3.20
0.25
1
1.95
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT319-2
1996 Oct 24
23
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
QFP100 (SOT382-1) or QFP160 (SOT322-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9398 510 63011).
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1996 Oct 24
24
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Oct 24
25
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
NOTES
1996 Oct 24
26
Philips Semiconductors
Preliminary specification
VErtical Reconstruction IC (VERIC) for
PALplus
SAA4997H
NOTES
1996 Oct 24
27
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© Philips Electronics N.V. 1996
SCA52
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Printed in The Netherlands
537021/1200/01/pp28
Date of release: 1996 Oct 24
Document order number: 9397 750 01423
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