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SAA4998H [PHILIPS]

Consumer Circuit, PQFP100,;
SAA4998H
型号： SAA4998H
厂家： PHILIPS SEMICONDUCTORS    PHILIPS SEMICONDUCTORS
描述：

Consumer Circuit, PQFP100,

商用集成电路
文件： 总39页 (文件大小：155K)
中文：  中文翻译
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INTEGRATED CIRCUITS  
DATA SHEET  
SAA4998H  
Field and line rate converter with  
noise reduction and embedded  
memory  
Product specification  
2004 Feb 18  
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
CONTENTS  
10  
CHARACTERISTICS  
PACKAGE OUTLINE  
SOLDERING  
11  
1
2
FEATURES  
12  
GENERAL DESCRIPTION  
12.1  
Introduction to soldering surface mount  
packages  
Reflow soldering  
Wave soldering  
Manual soldering  
Suitability of surface mount IC packages for  
wave and reflow soldering methods  
Additional soldering information  
2.1  
2.2  
Patent notice  
Latch-up test  
12.2  
12.3  
12.4  
12.5  
3
4
5
6
7
8
9
QUICK REFERENCE DATA  
ORDERING INFORMATION  
BLOCK DIAGRAMS  
PINNING  
12.6  
13  
CONTROL REGISTER DESCRIPTION  
LIMITING VALUES  
DATA SHEET STATUS  
DEFINITIONS  
14  
THERMAL CHARACTERISTICS  
15  
DISCLAIMERS  
2004 Feb 18  
2
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
1
FEATURES  
2
GENERAL DESCRIPTION  
• Motion compensated frame rate upconversion of all 1fH  
film and video standards up to 292 active input lines per  
field:  
The SAA4998H is a high performance video processor  
featuring Natural Motion (2), for all global TV standards  
(PAL, NTSC and SECAM). It is used together with the  
picture improvement processor SAA4978H and  
SAA4979H.  
– 50 Hz interlaced to 60 Hz progressive  
{(60p mode for LCD and Plasma Display (PDP) TV}  
The SAA4998H is an advanced version of the SAA4993H.  
By embedding the field memories it reduces the part count  
of the realized concept from 4 to 6 parts to only 2 parts and  
reduces the package size from a QFP160 to a QFP100.  
– 50 Hz interlaced to 75 Hz interlaced  
{75i mode for jumbo screens, Projection TV (PTV)}  
– 50 Hz interlaced to 100 Hz interlaced  
(high-end 100 Hz TV)  
The full FALCONIC mode uses full motion estimation and  
motion compensation on 1/4 pixel accuracy to perform  
– 50 Hz interlaced to 50 Hz progressive  
(progressive scan TV and LCD and PDP TV)  
• Frame rate upconversion  
– 60 Hz interlaced to 60 Hz progressive  
(progressive scan TV and LCD and PDP TV)  
• Film mode detection  
– 60 Hz interlaced to 90 Hz interlaced  
(jumbo screens, PTV)  
• Movie judder cancellation  
• Dynamic Noise Reduction (DNR)  
• Edge Dependent De-Interlacing (EDDI).  
– 60 Hz interlaced to 120 Hz interlaced  
(multistandard high-end 100 Hz TV)  
The motion compensated de-interlacer is improved with a  
new patented Edge Dependent De-Interlacing (EDDI)  
method. This avoids jagged edges of diagonal lines. The  
better de-interlacer leads to a significant better  
performance of progressive as well as interlaced output  
formats.  
• 480 active lines (NTSC like) or 506 active lines in 50 Hz  
interlaced to 60 Hz progressive mode  
• Motion compensated and Edge Dependent  
De-Interlacing (EDDI)(1)  
• Motion estimated film mode detection  
• Motion compensated movie judder cancellation:  
A 60 Hz progressive output frame rate can be generated  
for 50 Hz PAL sources to enable the use of 60 Hz LCD or  
PDP panels in PAL regions.  
– 25 Hz 2 : 2 pull-down (PAL) to 60 Hz progressive or  
75 Hz interlaced or 100 Hz interlaced or 50 Hz  
progressive  
50 Hz interlaced to 75 Hz interlaced and 60 Hz interlaced  
to 90 Hz interlaced can be generated to achieve an  
increased number of lines and hence a reduction of line  
visibility for jumbo screens and PTV applications.  
– 30 Hz 2 : 2 pull-down (NTSC) to 60 Hz progressive or  
90 Hz interlaced or 120 Hz interlaced  
– 24 Hz 3 : 2 pull-down (NTSC) to 60 Hz progressive or  
90 Hz interlaced or 120 Hz interlaced  
The embedded memory can be used to synchronize the  
main channel and the 2nd channel for PIP and double  
window applications. This avoids to add additional buffer  
memory devices to the application.  
• Variable vertical sharpness enhancement  
• High quality vertical zoom  
• Motion compensated temporal noise reduction with  
For demonstration purposes a split screen mode to show  
the Dynamic Noise Reduction (DNR) function, natural  
motion, and EDDI is available. The estimated motion  
vectors can be made visible by colour overlay mode.  
after-imaging cancellation  
• Split screen demonstration mode  
• 2 Mbaud serial interface (SNERT)  
• Embedded 2 × 2.9-Mbit DRAM  
• Full 8-bit accuracy  
The SAA4998H supports a Boundary Scan Test (BST)  
circuit in accordance with “IEEE Std. 1149.1”.  
• Memory buffer for Picture-In-Picture (PIP)  
• Lead-free package.  
(1) EDDI is protected with two patents of Koninklijke Philips  
Electronics N.V.  
(2) Natural Motion is a trademark of Koninklijke Philips  
Electronics N.V.  
2004 Feb 18  
3
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
2.1  
Patent notice  
2.2  
Latch-up test  
Notice is herewith given that the subject integrated circuit  
uses one or more of the following US patents and that  
each of these patents may have corresponding patents in  
other jurisdictions.  
Latch-up test in accordance with “Latch-up Resistance  
and Maximum Ratings Test; SNW-FQ-303”; the  
SAA4998H fulfils the requirements.  
US 4740842, US 5929919, US 6034734, US 5534946,  
US 5532750, US 5495300, US 5903680, US 5365280,  
US 5148269, US 5072293, US 5771074, and  
US 5302909.  
3
QUICK REFERENCE DATA  
SYMBOL  
PARAMETER  
MIN.  
1.65  
TYP.  
1.8  
MAX.  
1.95  
UNIT  
VDDD  
core supply voltage (internal rail)  
V
V
VDDA  
VDDM  
VDDS  
VDDE  
VDDP  
IDD  
analog supply voltage  
field memory supply voltage  
SRAM supply voltage  
external supply voltage (output pads)  
high supply voltage of internal field memories  
sum of supply current  
3.0  
3.3  
3.6  
at 1.8 V supply voltage pins  
at 3.3 V supply voltage pins  
operating clock frequency  
ambient temperature  
−
−
−
0
180  
6
−
mA  
mA  
MHz  
°C  
−
fCLK  
32  
−
33.3  
70  
Tamb  
4
ORDERING INFORMATION  
PACKAGE  
TYPE  
NUMBER  
NAME  
DESCRIPTION  
VERSION  
SAA4998H  
QFP100  
plastic quad flat package; 100 leads (lead length 1.95 mm);  
SOT317-2  
body 14 × 20 × 2.8 mm  
2004 Feb 18  
4
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DYNAMIC  
NOISE  
FIELD MEMORY 2  
MEMORY CONTROL  
FIELD MEMORY 3  
55 to 62  
YA0 to YA7  
REDUCTION  
94  
41  
34  
VD  
SNCL  
SNERT  
INTERFACE  
SNDA  
33  
COMPRESS  
DECOMPRESS  
SNRST  
25  
32  
36  
ACV  
RST  
MUX  
MUX  
PIPON  
50  
63  
CONTROL  
TWOFMON  
REA  
DE-INTERLACER  
WITH EDDI  
68, 69,  
71 to 76  
64  
67  
IE  
YF7 to YF0  
YG7 to YG0  
vectors  
REF  
95, 100,  
1, 2,  
5 to 8  
MPR  
LEFT  
VERTICAL  
ZOOM  
VERTICAL  
PEAKING  
MPR  
RIGHT  
SPM  
TPM  
ESM  
31  
30  
29  
28  
27  
TCK  
TDO  
MOTION ESTIMATOR  
vectors  
TDI  
BST/TEST  
TMS  
UPCONVERSION  
SAA4998H  
LUMINANCE PART  
TRSTN  
83  
CLK32  
coc001  
Fig.1 Block diagram luminance part in full FALCONIC mode.  
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FIELD MEMORY 2  
FIELD MEMORY 3  
COMPRESS/  
FORMAT  
DECOMPRESS/  
REFORMAT  
42 to 47,  
53, 54  
DECOMPRESS/  
REFORMAT  
UVA0 to UVA7  
DNR  
vectors  
MPR  
LEFT  
MPR  
RIGHT  
78 to 81,  
88, 89,  
92, 93  
UPCONVERSION  
FORMAT  
UVF7 to UVF0  
UVG7 to UVG0  
VERTICAL  
ZOOM  
9 to 13,  
17 to 19  
SAA4998H  
CHROMINANCE PART  
coc002  
Fig.2 Block diagram chrominance part in full FALCONIC mode.  
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
6
PINNING  
SYMBOL  
PIN  
TYPE  
DESCRIPTION(1)(2)(3)  
YG5/DPIP5  
1
output/input PIP mode disabled: bus G luminance output bit 5;  
PIP mode enabled: PIP data input bit 5  
YG4/DPIP4  
2
output/input PIP mode disabled: bus G luminance output bit 4;  
PIP mode enabled: PIP data input bit 4  
VDDE  
3
4
5
supply  
ground  
supply voltage of output pads (3.3 V)  
ground of output pads  
VSSE  
YG3/DPIP3  
output/input PIP mode disabled: bus G luminance output bit 3;  
PIP mode enabled: PIP data input bit 3  
YG2/DPIP2  
YG1/DPIP1  
YG0/DPIP0  
UVG7/QPIP7  
UVG6/QPIP6  
UVG5/QPIP5  
UVG4/QPIP4  
UVG3/QPIP3  
n.c./LLC  
6
7
output/input PIP mode disabled: bus G luminance output bit 2;  
PIP mode enabled: PIP data input bit 2  
output/input PIP mode disabled: bus G luminance output bit 1;  
PIP mode enabled: PIP data input bit 1  
8
output/input PIP mode disabled: bus G luminance output bit 0 (LSB);  
PIP mode enabled: PIP data input bit 0 (LSB)  
9
output  
output  
output  
output  
output  
input  
PIP mode disabled: bus G chrominance output bit 7 (MSB);  
PIP mode enabled: PIP data output bit 7 (MSB)  
10  
11  
12  
13  
14  
PIP mode disabled: bus G chrominance output bit 6;  
PIP mode enabled: PIP data output bit 6  
PIP mode disabled: bus G chrominance output bit 5;  
PIP mode enabled: PIP data output bit 5  
PIP mode disabled: bus G chrominance output bit 4;  
PIP mode enabled: PIP data output bit 4  
PIP mode disabled: bus G chrominance output bit 3;  
PIP mode enabled: PIP data output bit 3  
PIP mode disabled: not connected;  
PIP mode enabled: line locked clock signal for PIP mode  
VSSE  
15  
16  
ground  
input  
ground of output pads  
n.c./SWCK2  
PIP mode disabled: not connected;  
PIP mode enabled: serial write clock for PIP memory  
UVG2/QPIP2  
UVG1/QPIP1  
UVG0/QPIP0  
n.c./RSTW2  
n.c./OIE2  
17  
18  
19  
20  
21  
22  
output  
output  
output  
input  
PIP mode disabled: bus G chrominance output bit 2;  
PIP mode enabled: PIP data output bit 2  
PIP mode disabled: bus G chrominance output bit 1;  
PIP mode enabled: PIP data output bit 1  
PIP mode disabled: bus G chrominance output bit 0 (LSB);  
PIP mode enabled: PIP data output bit 0 (LSB)  
PIP mode disabled: not connected;  
PIP mode enabled: write reset clock for PIP memory  
input  
PIP mode disabled: not connected;  
PIP mode enabled: output enable for PIP memory output QPIPx  
n.c./IE2  
input  
PIP mode disabled: not connected;  
PIP mode enabled: input enable for PIP memory  
VDDP  
23  
24  
supply  
input  
high supply voltage of the internal field memories (3.3 V)  
n.c./WE2  
PIP mode disabled: not connected;  
PIP mode enabled: write enable for PIP memory  
2004 Feb 18  
7
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
SYMBOL  
ACV/RE2  
PIN  
TYPE  
DESCRIPTION(1)(2)(3)  
25  
output/input PIP mode disabled: active video output;  
PIP mode enabled: read enable for PIP memory  
n.c./RSTR2  
26  
input  
PIP mode disabled: not connected;  
PIP mode enabled: read reset for PIP memory  
TRSTN  
TMS  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
input  
input  
input  
3-state  
input  
input  
input  
boundary scan test reset input (active LOW); with internal pull-up resistor  
boundary scan test mode select input; with internal pull-up resistor  
boundary scan test data input; with internal pull-up resistor  
boundary scan test data output  
TDI  
TDO  
TCK  
boundary scan test clock input; with internal pull-up resistor  
reset input; see Fig.4  
RST  
SNRST  
SNDA  
VDDE  
PIPON  
VSSM  
VDDM  
VSSM  
VDDM  
SNCL  
UVA0  
UVA1  
UVA2  
UVA3  
UVA4  
UVA5  
VDDD  
VSSD  
TWOFMON  
VDDS  
VSSS  
UVA6  
UVA7  
YA0  
SNERT bus reset input; with internal pull-down resistor  
input/output SNERT bus data input and output; with internal pull-down resistor  
supply  
input  
supply voltage of output pads (3.3 V)  
PIP mode enable input  
ground  
supply  
ground  
supply  
input  
field memory ground  
supply voltage of the internal field memories (1.8 V)  
field memory ground  
supply voltage of the internal field memories (1.8 V)  
SNERT bus clock input; with internal pull-down resistor  
bus A chrominance input bit 0 (LSB)  
bus A chrominance input bit 1  
bus A chrominance input bit 2  
bus A chrominance input bit 3  
bus A chrominance input bit 4  
bus A chrominance input bit 5  
core supply voltage (1.8 V)  
input  
input  
input  
input  
input  
input  
supply  
ground  
input  
core ground  
to be connected to ground  
supply  
ground  
input  
supply voltage of the internal SRAMs (1.8 V)  
ground of the internal SRAMs  
bus A chrominance input bit 6  
bus A chrominance input bit 7 (MSB)  
bus A luminance input bit 0 (LSB)  
bus A luminance input bit 1  
input  
input  
YA1  
input  
YA2  
input  
bus A luminance input bit 2  
YA3  
input  
bus A luminance input bit 3  
YA4  
input  
bus A luminance input bit 4  
YA5  
input  
bus A luminance input bit 5  
YA6  
input  
bus A luminance input bit 6  
YA7  
input  
bus A luminance input bit 7 (MSB)  
read enable output for bus A  
REA  
output  
2004 Feb 18  
8
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
SYMBOL  
PIN  
TYPE  
input  
DESCRIPTION(1)(2)(3)  
IE  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
input enable for PIP mode  
core supply voltage (1.8 V)  
core ground  
VDDD  
VSSD  
REF  
supply  
ground  
input  
read enable input for bus F and G; note 4  
bus F luminance output bit 7 (MSB)  
bus F luminance output bit 6  
YF7  
output  
output  
ground  
output  
output  
output  
output  
output  
output  
supply  
output  
output  
output  
output  
ground  
input  
YF6  
VSSE  
YF5  
ground of output pads  
bus F luminance output bit 5  
YF4  
bus F luminance output bit 4  
YF3  
bus F luminance output bit 3  
YF2  
bus F luminance output bit 2  
YF1  
bus F luminance output bit 1  
YF0  
bus F luminance output bit 0 (LSB)  
supply voltage of output pads (3.3 V)  
bus F chrominance output bit 7 (MSB)  
bus F chrominance output bit 6  
bus F chrominance output bit 5  
bus F chrominance output bit 4  
ground of output pads  
VDDE  
UVF7  
UVF6  
UVF5  
UVF4  
VSSE  
CLK32  
VDDS  
VSSS  
VDDD  
VSSD  
UVF3  
UVF2  
VSSA  
VDDA  
UVF1  
UVF0  
VD  
system clock input (32 MHz)  
supply  
ground  
supply  
ground  
output  
output  
ground  
supply  
output  
output  
input  
supply voltage of the internal SRAMs (1.8 V)  
ground of the internal SRAMs  
core supply voltage (1.8 V)  
core ground  
bus F chrominance output bit 3  
bus F chrominance output bit 2  
analog ground of the internal PLL  
analog supply voltage of the internal PLL (1.8 V)  
bus F chrominance output bit 1  
bus F chrominance output bit 0 (LSB)  
vertical display synchronization input (reset for field memories)  
YG7/DPIP7  
output/input PIP mode disabled: bus G luminance output bit 7 (MSB);  
PIP mode enabled: PIP data input bit 7 (MSB)  
VDDM  
VSSM  
96  
97  
supply  
ground  
supply voltage of the internal field memories (1.8 V)  
field memory ground  
2004 Feb 18  
9
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
SYMBOL  
VDDM  
PIN  
TYPE  
supply  
ground  
DESCRIPTION(1)(2)(3)  
98  
99  
supply voltage of the internal field memories (1.8 V)  
field memory ground  
VSSM  
YG6/DPIP6  
100 output/input PIP mode disabled: bus G luminance output bit 6;  
PIP mode enabled: PIP data input bit 6  
Notes  
1. Not used input pins should be connected to ground.  
2. Because of the noisy characteristic of the supply voltage of output pads (VDDE), it is recommended not to connect  
VDDE directly at the high supply voltage of the intern field memories (VDDP). All pins VDDE should be buffered as close  
as possible to the device. VDDP needs a low noise supply voltage, therefore, it is recommended that VDDP has to be  
separated from VDDE by an external filter structure. Because of the high working frequency of the device, it is also  
recommended to filter the core supply voltage (VDDD). All pins VDDD should be buffered as close as possible to the  
device.  
3. VSSD, VSSM and VSSS are connected internally.  
4. REF rising edge must be after rising edge of SNRST in order to be detected.  
2004 Feb 18  
10  
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
YG5/DPIP5  
YG4/DPIP4  
1
2
3
4
5
6
7
8
9
80 UVF5  
79 UVF6  
78 UVF7  
V
DDE  
V
V
DDE  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
SSE  
YG3/DPIP3  
YG2/DPIP2  
YG1/DPIP1  
YG0/DPIP0  
UVG7/QPIP7  
YF0  
YF1  
YF2  
YF3  
YF4  
UVG6/QPIP6 10  
UVG5/QPIP5 11  
UVG4/QPIP4 12  
UVG3/QPIP3 13  
YF5  
V
SSE  
YF6  
YF7  
REF  
n.c./LLC 14  
V
V
15  
SSE  
SSD  
SAA4998H  
V
n.c./SWCK2 16  
UVG2/QPIP2 17  
UVG1/QPIP1 18  
UVG0/QPIP0 19  
n.c./RSTW2 20  
n.c./OIE2 21  
DDD  
IE  
REA  
YA7  
YA6  
YA5  
YA4  
YA3  
YA2  
YA1  
YA0  
UVA7  
UVA6  
n.c./IE2 22  
V
DDP  
23  
n.c./WE2 24  
ACV/RE2 25  
n.c./RSTR2 26  
TRSTN 27  
TMS 28  
TDI 29  
V
V
SSS  
DDS  
TDO 30  
001aaa057  
Fig.3 Pin configuration.  
11  
2004 Feb 18  
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7
CONTROL REGISTER DESCRIPTION  
SNERT  
ADDRESS  
(HEX)  
READ/  
WRITE(1)  
NAME  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
DNR/peaking/colour  
Kstep10  
Kstep0  
Kstep1  
Kstep32  
Kstep2  
Kstep3  
Kstep54  
Kstep4  
Kstep5  
Kstep76  
Kstep6  
010  
011  
012  
013  
write; S  
write; S  
write; S  
write; S  
X X X X set LUT value: k = 1⁄16 if difference below (0 to 15)  
set LUT value: k = 1⁄8 if difference below (0 to 15)  
X X X X  
X X X X  
X X X X  
X X X X set LUT value: k = 2⁄8 if difference below (0 to 30 in multiples of 2)  
set LUT value: k = 3⁄8 if difference below (0 to 30 in multiples of 2)  
X X X X set LUT value: k = 4⁄8 if difference below (0 to 60 in multiples of 4)  
set LUT value: k = 5⁄8 if difference below (0 to 60 in multiples of 4)  
X X X X set LUT value: k = 6⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,  
64, 72, 80, 88, 96, 104, 112 or 120)  
Kstep7  
X X X X  
set LUT value: k = 7⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,  
64, 72, 80, 88, 96, 104, 112 or 120)  
Gain_fix_y  
014  
015  
write; S  
write; S  
FixvalY  
X X X X set fixed Y value; used when FixY = 1 or in left part of split screen  
(0, 1⁄16 to 14 16 or 16⁄16)  
⁄
GainY  
FixY  
X X X  
X
set gain in difference signal for adaptive DNR Y (1⁄8, 1⁄4, 1⁄2, 1, 2 or 4)  
select fixed Y (adaptive or fixed) (full screen)  
Gain_fix_uv  
FixvalUV  
X X X X set fixed UV value; used when FixUV = 1 or in left part of split screen  
(0, 1⁄16 to 14 16 or 16⁄16)  
⁄
GainUV  
FixUV  
X X X  
X
set gain in difference signal for adaptive DNR UV (1⁄8, 1⁄4, 1⁄2, 1, 2 or 4)  
select fixed UV (adaptive or fixed) (full screen)  
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SNERT  
READ/  
NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
Peak_Vcomp  
016  
write; S  
VecComp  
X X X set degree of horizontal vector compensation in Y DNR:  
(0, 1⁄8, 2⁄8, 3⁄8, 4⁄8, 5⁄8, 6⁄8 or 7⁄8) of the vector  
NoiseShape  
PeakCoef  
X
noise shaping enable; this bit is set to logic 1 after reset or power-up  
X X X X  
set vertical peaking level: (0, +2, +3.5, +5, +6, x, x, x, x, x, x, x, x,  
−12, −6 or −2.5) dB  
DNR_Colour_mode  
017  
write; S  
ColourIn  
X X select colour input format: (4 : 1 : 1, 4 : 2 : 2, 4 : 2 : 2 DPCM or  
4 : 2 : 2)  
ColourOut  
NrofFMs  
ColOvl  
X
select colour output format: (4 : 1 : 1 or 4 : 2 : 2)  
X
set number of field memories used for motion compensation: (1 or 2)  
X
select vector overlay on colour output: (vector overlay or colour  
from video path)  
SlaveUVtoY  
DnrSplit  
X
slave UV noise reduction to K factor of Y: (separate or slaved)  
select split screen mode for DNR: (normal or split screen)  
X
X
DnrHpon  
switch DNR high-pass on (DNR only active on low frequent spectrum:  
(all through DNR or high bypassed)  
Vertical zoom  
Zoom1  
018  
write; F  
ZoomSt98  
X X zoom line step bits 9 and 8; line step = vertical distance between  
successive output lines; usable range = 0 to 2 frame lines;  
resolution 1⁄256 frame line  
ZoomPo98  
X X  
zoom start position bits 9 and 8; start position = vertical position of the  
top display line; usable range = 1 to 3 frame lines; resolution 1⁄256  
frame line  
Zoom2  
019  
01A  
write; F  
write; F  
ZoomSt70  
Zoom3  
X X X X X X X X zoom line step bits 7 to 0 (see above)  
X X X X X X X X zoom start position bits 7 to 0 (see above)  
ZoomPo70  
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READ/  
NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
Zoom4  
01B  
write; F  
ZoomEnVal  
X X X X zoom run in value = number of lines without zoom active  
(0 to 15 lines)  
ZoomDiVal  
X X X X  
zoom run out value = number of lines without zoom active  
(−8 to +7 lines)  
De-interlacer  
Proscan1  
01C  
write; S  
KlfLim  
X X X X limitation of recursion factor in calculation of original line positions:  
(1 to 16); 1 limits to almost full recursion, 16 limits to no recursion  
KlfOfs  
X X X X  
The transfer curve of the de-interlacing filter coefficient is determined  
by the difference (Diff) between a line in the input field and the  
counterpart in the previous field shifted over the estimated motion  
vector. KlfOfs determines the bias of the transfer curve for the original  
input line, such that coefficient = KlfOfs + F(Diff), where the function F  
is calculated in the SAA4998H. The bias can take a value in the range  
(0 to 15), representing decreasing filter strength.  
Proscan2  
01D  
01E  
write; S  
write; S  
PlfLim  
X X X X limitation of recursion factor in calculation of interpolated line  
positions: (1 to 16); 1 limits to almost full recursion, 16 limits to no  
recursion  
PlfOfs  
Proscan3  
PeakLim  
X X X X  
see KlfOfs; this offset applies to interpolated lines  
X X X X Maximum that the peaked pixel is allowed to deviate from original pixel  
value: deviation (0 to 30 in steps of 2). Above this deviation, the  
peaked pixel is clipped to (original pixel + or − PeakLim).  
DeiOfs  
X X X X  
offset to bias between average and median in the initial de-interlacing,  
if the KplFad = MIX option is chosen  
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NAME  
Proscan4  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
01F  
write; F  
PlfThr  
X X X Multiplier threshold at which to switch the lower limit of the filter  
coefficient for interpolated lines. Above this threshold, the differences  
corresponding to the two neighbouring lines are used as clipping  
parameters, below this threshold, the interpolated line difference is  
used as clipping level. This parameter can be used to optimize the  
de-interlacing quality in slowly moving edges; it is not likely to have  
effect if PlfLim is high.  
AdRecOut  
ProDiv  
X
select adaptive recursive or order statistic output (order statistic or  
adaptive)  
X X  
Scaling factor to control the strength of the filtering for the interpolated  
lines. A value 0 means no scaling (normal filtering), while 3 means  
scaling by factor 8 (very strong filtering). This parameter can be used  
to adjust the de-interlacing to varying level of noise in the input picture;  
use higher scaling for higher noise.  
KplOff  
X
disable all recursion in calculating pixels for frame memory (recursive  
or non recursive)  
Proscan5  
0CB  
write; S  
VecRbf  
X X X X Roll back factor on vectors used for motion-compensated  
de-interlacing. Values 0 to 14 (on a scale of 16) indicate attenuation.  
A value of 15 indicates no attenuation.  
FadDiv  
KplFad  
X X X  
sensitivity scaling factor in transition from average to median in initial  
de-interlacing  
X
chooses between majority selection and median/average mix for initial  
de-interlacing (majority or mix); when KplFad = 0, FadDiv and  
DeiOfs are don’t cares  
Proscan6  
EddiOut  
0F0  
write; S  
X turns EDDI on and off (off or on)  
EddiDemo  
EddiCmp  
X
activates split screen demonstration mode for EDDI (off or on)  
X X  
Factor to specify the size of the additional compensation area left and  
right of the ‘real’ edge. A high factor (e.g. 1) can increase the  
compensation in regions far away from the true edge (1, 1⁄2, 1⁄4 or 1⁄8).  
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NAME  
Proscan7  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
0F1  
write; S  
EddiMR  
X X Factor for the comparison of the monotonous regions belonging to two  
edge points to verify an edge (1, 1⁄2, 1⁄4 or 1⁄8).  
EddiED  
X X  
Factor for the comparison of the monotonous regions belonging to two  
edge points and the edge point distance to verify an edge  
(1, 1⁄2, 1⁄4 or 1⁄8).  
EddiDif  
X X X X  
minimal required Y difference at edge point position to be a reliable  
edge point; higher values result in higher reliability of EDDI, but less  
edges will be detected (0 to 60 in multiples of 4)  
Proscan8  
0F2  
0F3  
write; S  
EddiFil  
X X X X minimal required edge filter value at start and end of the monotonous  
region to be a reliable edge point; should be set higher in pictures with  
noise (0 to 60 in multiples of 4)  
EddiLng  
X X  
minimal required length of monotonous region to be reliable; higher  
values result in higher reliability of EDDI, but less steep edges will be  
detected (2, 3, 4 or 5)  
Proscan9  
write; S  
EddiOfs  
X X X X offset to increase or decrease the amount of EDDI compensation;  
lower values increase the amount of compensation (1 to 16)  
EddiLim  
X X X X  
limitation of the compensation factor of EDDI; 1 limits to full EDDI  
compensation, 16 limits to almost no EDDI compensation (1 to 16)  
General  
NrBlks  
NrBlks  
020  
021  
write; S  
write; S  
X X X X X X number of blocks in active video (6 to 53, corresponds to  
96 to 848 pixels), to be set as 1⁄16 (number of active pixels per  
line + 15); take remarks on TotalPxDiv8 into consideration  
TotalLnsAct98  
X X  
total number of output lines (bits 9 and 8)  
TotalLnsAct70  
X X X X X X X X total number of output lines (bits 7 to 0)  
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READ/  
NAME  
TotalPxDiv8  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
022  
write; S  
X X X X X X X X Total number of pixels per line divided-by-8 (80 to 128, corresponds to  
640 to 1024 pixels). The horizontal blanking interval is calculated as  
TotalPxDiv8 − 2 × NrBlks and has to be in the range from 12 to 124  
(corresponds to 96 to 992 pixels). Conclusion: TotalPxDiv8 has to be  
set to 12 + 2 × NrBlks < TotalPxDiv8 < 124 + 2 × NrBlks and NrBlks  
TotalPxDiv8 – 124  
-----------------------------------------------  
2
TotalPxDiv8 – 12  
--------------------------------------------  
2
has to be set to  
< NrBlks <  
REaShift  
023  
024  
write; S  
write; S  
X X X shift of REA signal in number of pixels (0, +1, +2, +3, −4, −3, −2 or −1)  
WEbdREceShift  
WEbdShift  
REceShift  
POR  
X X X reserved  
reserved  
X X X  
025  
0D6  
write; S  
write; S  
X power-on reset command, to be set high temporarily during start-up  
(normal or reset); note 3  
ScalingFactor  
X X X X X X X X 8-bit scaling factor for EggSliceMix, EggSliceRgt and global activity  
(the same factor for all registers).  
ScalingFactor  
output value (n+1) =  
× output value (n)  
------------------------------------  
128  
FieldMemoryControl  
PIPON  
000  
write; F  
X Picture-In-Picture (PIP) field memory mode enable  
0 has to be set to logic 0  
TWOFMON  
PIPDataDelay  
X
input data will be delayed by one clock cycle with respect to WE2  
(write enable)  
PIPStillPicture  
X
no new data will be written into the field memory  
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READ/  
NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
Mode control  
Control1  
026  
write; F  
EstMode  
X Set estimator mode; 0 = line alternating use of left and right estimator:  
use in progressive scan except with vertical compress. 1 = field  
alternating use of left and right estimator: use in field doubling and  
progressive scan with vertical compress.  
FilmMode  
UpcMode  
X
set film mode; 0 = video camera mode; 1 = film mode  
X X  
select upconversion quality; 00 = full, 01 = economy (DPCM),  
10 = single memory with motion compensation, 11 = single memory  
without motion compensation  
MatrixOn  
X
set matrix output mode; 1 = double output, disabling vertical peaking;  
0 = normal single output mode; this bit setting is the AND function of  
BusGControl bits  
EmbraceOn  
X
Master enable for embrace mode (off or on); SwapMpr in control2  
should be at ‘swap’ position to really cross-switch FM1 and FM3 field  
outputs. Should be set to logic 0 except in film mode and FM3 is  
present.  
MemComp  
X
set memory compression (luminance DPCM) (off or on)  
set memory decompression (luminance DPCM) (off or on)  
MemDecom  
X
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NAME  
Control2  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
027  
write; F  
QQcurr  
X Quincunx phase of current field (in TPM) (phase0 or phase1); this  
needs to toggle each time a new field comes from FM1. In phase0 the  
estimator operates on a checker-board pattern that starts with the left  
upper block; in phase1 the other blocks are estimated.  
QQprev  
FldStat  
X
Quincunx phase of previous field (in TPM) (phase0 or phase1); this is  
the value of QQcurr during the last estimate written into the temporal  
prediction memory  
X
Field status (same input field or new input field); reflects whether  
the output of FM1 is a new or a repeated field. This bit will toggle field  
by field in field doubling mode and is continuously HIGH in progressive  
output mode.  
FieldWeYUV  
X
enable writing FM2 and FM3 for both luminance and chrominance  
(recirculation of data for luminance alone can be controlled with  
OrigFmEnY and IntpFmEnY in Control3) (off or on)  
OddFM1  
SwapMpr  
X
odd input field (even or odd), this is to be set equal to the detected  
field interlace for the field that comes out of FM1  
X
Swap multi port RAMs (normal or swap); this bit needs to be set to  
get real frame data at the temporal position from FM1. If swapped, the  
current field (FM1) will be stored in the right line memory tree, while  
the original lines from the stored frame (FM2/3) are stored in the left  
memory tree. Should be set only in film mode if FM3 is present;  
EmbraceOn must be set as well.  
VecOffs  
X X  
Set vertical vector offset (0, +1, − or −1) frame lines; vertical offset of  
the right line memory tree with respect to the left line memory tree.  
A higher offset value means: on the right memory tree access to less  
delayed video lines is taken; in interlaced video operation, the vertical  
offset will be −1 with an odd field on the left side and +1 with an even  
field on the left. With non-interlaced input, vertical offset should be  
constantly 0. In film mode, vertical offset is dynamically switched  
between +1, 0 and −1.  
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NAME  
Control3  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
028  
write  
F
OddLeft  
X interlace (even or odd) phase of the field which is written to the left  
line memory tree (left MPRAM)  
OrigFmEnY  
X
enables writing luminance from de-interlacer in original field memory  
(FM2), otherwise recirculation of luminance that is just read from FM2  
(recirculate or update)  
IntpFmEnY  
FillTPM  
X
enables writing luminance from de-interlacer in interpolated field  
memory (FM3), otherwise recirculation of luminance that is just read  
from FM3 (recirculate or update)  
X
Enables writing in temporal prediction memory (keep or update);  
FillTPM should be set to ‘keep’ in single memory film mode, in those  
output fields where FM1 and FM2 contain the same motion phase.  
FillTPM should be set to ‘update’ in all other situations.  
VertOffsDNR  
X X  
Set vertical vector offset of DNR (0, +1, − or −1) frame lines; vertical  
offset of the right line memory tree with respect to the left line memory  
tree, before the swap action. A higher offset value means: on the right  
memory tree access to less delayed video lines is taken; in interlaced  
video operation, the vertical offset will be −1 with an odd field on the  
left side and +1 with an even field on the left. With non-interlaced  
input, vertical offset should be constantly logic 0; in film mode, vertical  
offset is dynamically switched between +1, 0 and −1. It should be  
noted that the signal OddFM1 is used to determine this offset.  
BusGControl  
S
X X  
Select output mode of bus G; 00 = normal single output mode (bus G  
in 3-state), 01 = output of motion vectors to UVG (motion_x on U and  
motion_y on V), 10 = copy bus F to G, 11 = double output, disabling  
vertical peaking. Only when double output is selected, the MatrixOn  
bit in register Control1 should be set, otherwise it needs to be cleared.  
Upconversion  
Upconv1  
029  
write; F  
UpcShFac  
X X X X X X temporal interpolation factor used in luminance upconverter; value  
ranges from 0 (for current field position) to 32 (for previous field  
position)  
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Upconv2  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
02A  
write  
S
YVecClip  
X X X value used for coring the vertical vector component before application  
in the upconverter; range: 0 to 3.5 in steps of 0.5 line; should remain  
at logic 0 in normal operation  
RollBack  
F
X X X X X  
roll back factor ranging from 0 (use 0% of estimated vectors) to 16  
(use 100% of estimated vectors)  
Upconv3  
02B  
write; S  
MelzLfbm  
X single memory type local fallback method instead of more robust local  
fallback (double memory or single memory type fallback)  
Melzmemc  
MelDeint  
MixCtrl  
X
single memory film mode control (double memory or single memory  
type); should be set in single memory film mode to ensure that only  
original lines are selected as output when UpcShFac is 0 or 32  
X
use horizontal motion compensated median for upconverter  
de-interlacing (full FALCONIC or single memory type  
de-interlacing)  
X X X X X  
Bits 3 and 4 are used to control sensitivity to local vector smoothness  
(0 = sensitive to unsmoothness, 3 = hardly sensitive to  
unsmoothness). Bits 5 to 7 define the maximum contribution of  
non-motion compensated pixels to the output  
(0, 1⁄8, 2⁄8, 3⁄8, 4⁄8, 5⁄8, 6⁄8 or 7⁄8).  
UpcColShiFac  
0C4  
0C5  
write; F  
write; S  
X X X X X X temporal interpolation factor used in chrominance upconverter; value  
ranges from 0 (for current field position) to 32 (for previous field  
position)  
Upconv4  
LfIndex  
X X X Number of consecutive lines to have bad egg-slice values before  
upconverter goes into protection mode (0, 1, 2, 4, 8, 16, 32 or 64).  
A value of 0 switches off the possibility to go into protection.  
MCDemo  
X
mode switch on left side of the screen; 0 (natural motion); 1 (digital  
scan-like processing)  
EggSlice1  
0C6  
write; S  
EggStartLine  
X X X X X X X X Reference line number at which the egg slice measurement should  
start. SAA4998H defines a window internally as number of lines  
between EggStartLine and (MaxRefLine − EggStartLine).  
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NAME  
EggSlice2  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
0C7  
write; S  
EggSlcThr  
X X X X X X Minimum line egg slice right value to activate reliability measurement.  
The parameter is multiplied internally by 4.  
EggRelInd  
X X  
The egg slice reliability is computed internally as  
EggSliceRgt (ESR) > RelFactor × EggSliceMix (ESM). RelFactor is  
determined by EggRelInd (2⁄8, 3⁄8, 4⁄8 or 6⁄8).  
SafeShiFac  
0C8  
02C  
write; F  
write; S  
X X X X X X upconverter shift factor to be used in protection mode; 0 (for current  
field position) to 32 (for previous field position)  
Motion estimator  
Motest1  
PenOdd  
X X X additional penalty on vector candidates with odd vertical component  
(0, 8, 16, 32, 64, 128, 256 or 511)  
SpcThr  
X X X  
Active when EstMode = 0; replace the spatial prediction of one  
estimator (left or right) by that of the other if the match error of the  
former exceeds that of the latter by more than (0, 8, 16, 32, 64, 128,  
256 or 511). A higher threshold means the two estimators are very  
independent.  
BmsThr  
X X  
Active when EstMode = 0; select as estimated vector the output of the  
right estimator unless its match error exceeds that of the left estimator  
by more than (0, 8, 16 or 32). This parameter should normally be set  
to logic 0.  
Motest2  
02D  
write; S  
TavLow  
X If the difference between the current vector and the previous one in  
the same spatial location is within a small window, then the two  
vectors are averaged to improve temporal consistency. TavLow is the  
lower threshold of this window (1 or 2).  
TavUpp  
MedEns  
X X  
see above; TavUpp is the upper threshold (0, 4, 8 or 16)  
X X  
scaling factor to reduce all sizes of update vectors in the ensemble  
with medium sized vector templates (1, 1⁄2, 1⁄4 or 1⁄8)  
LarEns  
X X  
scaling factor to reduce all sizes of update vectors in the ensemble  
with large sized vector templates (1, 1⁄2, 1⁄4 or 1⁄8)  
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NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
Motest3  
MotShiFac  
02E  
write; F  
X X X X X X Motion estimator shift factor, being the temporal position used in the  
estimator at which the matching is done; value 32 for matching at  
previous field position down to 0 for matching at current field position.  
Keeping MotShiFac equal to UpShiFac in the next upconverted output  
field estimates for minimum matching errors (minimum Halo’s).  
MotShiFac at value 16 gives the largest natural vector range (twice as  
large as with value 0 or 32). Going above the range with  
MotShiFac ≠ 16 is dealt with in SAA4998H by shifting towards 16, but  
for the horizontal and vertical component separately (consequence is  
that vector candidates tend to rotate towards the diagonal directions).  
Motest4  
02F  
write; S  
PenRng  
X Penalty for vectors estimated on the first row and the first column (if  
left estimator is used) or the right column (if right estimator is used),  
whenever the spatial prediction candidate is selected (64 or 511).  
For noisy pictures, this register could be set to logic 1 to improve  
border processing in the estimator.  
CndSet  
X
choice of candidate set (left or right) for which data (Candidate1 to  
Candidate8) is written in this field (becomes active in next field);  
note 3  
ErrThr  
ErrHbl  
X X X  
threshold on block match error for considering a block to be bad  
(16, 32, 64, 128, 256, 512, 1024 or 2032)  
X X  
number of horizontally adjacent blocks that have to be all bad before  
considering an occurrence of a burst error (1, 2, 4 or 8) (counting of  
burst errors is read out with BlockErrCnt, address 0A8H)  
TstMod  
Motest5  
X
X
to be kept to logic 1 for normal operation  
0CC  
write; S  
ActOption  
X X selection of the vector component to take in the activity count  
( x + y , x , y or −)  
ClearTPM  
LoActThr  
HiActThr  
write zeros in the temporal prediction memory  
(no writing or writing zeros)  
0CD  
0CE  
write; S  
write; S  
X X X X X X X X blocks having an activity value below or equal to this threshold are  
counted as having LOW activity  
X X X X X X X X blocks having an activity value above this threshold are counted as  
having HIGH activity  
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SNERT  
READ/  
NAME  
LeftBorder  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
0CF  
write; S  
LeftBorder  
X X X X X X X estimator left border (in 8-pixel blocks)  
enable writing of null vectors outside estimators’ active window  
WinNullWrite  
X
(off or on)  
RightBorder  
TopBorder  
BottomBorder  
Candidate1  
Candidat1  
0D0  
0D1  
0D2  
090  
write; S  
write; S  
write; S  
write; S  
X X X X X X X estimator right border (in 8-pixel blocks)  
X X X X X X X estimator top border (in 4-line blocks)  
X X X X X X X estimator bottom border (in 4-line blocks)  
X X X selection Candidate1 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update1  
X X  
X X  
X X  
X X  
update for Candidate1 (zero update, medium update, large update  
or zero update)  
Penalty1  
Candidate2  
Candidat2  
X X X  
X X X  
X X X  
X X X  
penalty for Candidate1 (0, 8, 16, 32, 64, 128, 256 or 511)  
091  
092  
093  
write; S  
write; S  
write; S  
X X X selection Candidate2 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update2  
update for Candidate2 (zero update, medium update, large update  
or zero update)  
Penalty2  
Candidate3  
Candidat3  
penalty for Candidate2 (0, 8, 16, 32, 64, 128, 256 or 511)  
X X X selection Candidate3 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update3  
update for Candidate3 (zero update, medium update, large update  
or zero update)  
Penalty3  
Candidate4  
Candidat4  
penalty for Candidate3 (0, 8, 16, 32, 64, 128, 256 or 511)  
X X X selection Candidate4 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update4  
Penalty4  
update for Candidate4 (zero update, medium update, large update  
or zero update)  
penalty for Candidate4 (0, 8, 16, 32, 64, 128, 256 or 511)  
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SNERT  
READ/  
NAME  
Candidate5  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
094  
095  
096  
097  
write; S  
Candidat5  
X X X selection Candidate5 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update5  
X X  
X X  
X X  
X X  
update for Candidate5 (zero update, medium update, large update  
or zero update)  
Penalty5  
Candidate6  
Candidat6  
X X X  
X X X  
X X X  
X X X  
penalty for Candidate5 (0, 8, 16, 32, 64, 128, 256 or 511)  
write; S  
write; S  
write; S  
X X X selection Candidate6 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update6  
update for Candidate6 (zero update, medium update, large update  
or zero update)  
Penalty6  
Candidate7  
Candidat7  
penalty for Candidate6 (0, 8, 16, 32, 64, 128, 256 or 511)  
X X X selection Candidate7 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update7  
update for Candidate7 (zero update, medium update, large update  
or zero update)  
Penalty7  
Candidate8  
Candidat8  
penalty for Candidate7 (0, 8, 16, 32, 64, 128, 256 or 511)  
X X X selection Candidate8 (SpatLeft, SpatRight, TemporalRight,  
TemporalLeft, TemporalCentre, Null, Panzoom or Max)  
Update8  
update for Candidate8 (zero update, medium update, large update  
or zero update)  
Penalty8  
penalty for Candidate8 (0, 8, 16, 32, 64, 128, 256 or 511)  
PZpositionLeftUppX  
098  
099  
write; S  
write; S  
write; S  
write; S  
write; F  
X X X X X X X position of LeftUpp measurement point for pan-zoom calculations  
(resolution: 16 pixels)  
PZpositionLeftUppY  
X X X X X X X Y position of LeftUpp measurement point for pan-zoom calculations  
(resolution: 4 lines)  
PZpositionRightLowX 09A  
PZpositionRightLowY 09B  
X X X X X X X position of RightLow measurement point for pan-zoom calculations  
(resolution: 16 pixels)  
X X X X X X X Y position of RightLow measurement point for pan-zoom calculations  
(resolution: 4 lines)  
PZvectorStartX  
09C  
X X X X X X X X X start value of pan-zoom vectors  
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SNERT  
READ/  
NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
PZvectorDeltaX  
PZvectorStartY  
PZvectorDeltaY  
09D  
09E  
09F  
write; F  
write; F  
write; F  
X X X X X X X X X delta value of pan-zoom vectors  
X X X X X X X X Y start value of pan-zoom vectors  
X X X X X X X X Y delta value of pan-zoom vectors  
Read data; note 3  
GlobalMSEmsb  
GlobalMSElsb  
0A0  
0A1  
read; F  
read; F  
X X X X X X X X Global Mean Square Error (MSE) = summation within a field period of  
squared differences in comparing vector shifted video from frame  
X X X X X X X X  
memory (FM2/3) with new field input (FM1) in those lines coinciding  
with new field lines. The window for the measurement is kept at  
40 pixels horizontal and 20 field lines vertical from the border of the  
video. Measurements is only done in fields where the de-interlacer is  
active, otherwise reading is zero. In field doubling mode, MSE is zero  
at the end of every new input field.  
GlobalMTImsb  
GlobalMTIlsb  
0A2  
0A3  
read; F  
read; F  
X X X X X X X X Global Motion Trajectory Inconsistency (MTI) = summation within a  
field period of squared differences comparing shifted video from frame  
X X X X X X X X  
memory (FM2/3 output) with filtered data that is rewritten to the frame  
memory (FM2/3 input) in those lines coinciding with new field lines.  
The window for the measurement is kept at 40 pixels horizontal and  
20 field lines vertical from the border of the video. Measurement is  
done only in fields where de-interlacer is active, otherwise reading is  
zero; in field doubling mode, MTI is zero at the end of every new input  
field.  
GlobalACTmsb  
GlobalACTlsb  
VectTempCons  
0A4  
0A5  
0A6  
read; F  
read; F  
read; F  
X X X X X X X X global activity (ACT) = summation over a field period of the horizontal  
plus the vertical components of the vectors of all blocks  
X X X X X X X X  
X X X X X X X X Vector temporal consistency = summation over a field period of  
absolute differences of horizontal plus vertical components of vectors  
newly estimated for each block compared with those vectors  
estimated in the previous run at the same spatial block position.  
It should be noted that a lower figure implies better consistency.  
VectSpatCons  
BlockErrCnt  
0A7  
0A8  
read; F  
read; F  
X X X X X X X X Vector spatial consistency = summation over a field period of absolute  
differences of horizontal and vertical components of vectors compared  
with those of the neighbour blocks (L, R, U and D); in the comparison,  
all vector data is used from the previous estimator run. It should be  
noted that a lower figure implies better consistency.  
X X X X X X X X burst error count (number of burst errors)  
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SNERT  
READ/  
NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
LeastErrSum  
0A9  
read; F  
X X X X X X X X least error sum (summation over a field period of the smallest match  
error that the estimator has found for each block: indicates reliability of  
the estimation process)  
YvecRangeErrCntmsb 0AA  
read; F  
X X X X X X X X Y vector range error count (number of vectors that have a vertical  
component that is out of range for upconversion at the chosen  
temporal position) (15 to 8)  
YvecRangeErrCntlsb 0AB  
read; F  
read; F  
write; F  
X X X X X X X X Y vector range error count (7 to 0)  
RefLineCountPrev  
RefLineCountNew  
0AC  
0AD  
X X X X X X X X read out of [number of input (run-) lines − 40] used in previous field  
X X X X X X X X Write of [number of input (run-) lines − 40] to be used in new field  
(actual maximum number of input lines in normal operation: 292;  
register value 252). Nominally this is to be set as an exact copy of the  
value read from RefLineCountPrev before a new field starts. In case  
the effective number of input (run-) lines has increased,  
RefLineCountNew should, for one field, be set to 255. This will occur  
e.g. with decreasing vertical zoom magnification or changing from  
525 lines video standard to 625 lines standard. If this is not done, a  
deadlock will occur with too few lines processed correctly by the  
motion estimator.  
PanZoomVec0-X  
PanZoomVec0-Y  
FalconIdent  
0B0  
0B1  
read; F  
read  
S
X X X X X X X X pan-zoom vector 0 (8-bit X value)  
0
SAA4998H identification: fixed bit, reading this bit as zero means  
SAA4998H is present  
PanZoomVec0-Y  
PanZoomVec1-X  
PanZoomVec1-Y  
StatusJump0  
F
X X X X X X X pan-zoom vector 0 (7-bit Y value)  
X X X X X X X X pan-zoom vector 1 (8-bit X value)  
0B2  
0B3  
read; F  
read  
S
X
1: both field memories are in use by the motion estimation and motion  
compensation function; see Fig.1  
0: field memory 2 is in use by the motion estimation and motion  
compensation function; field memory 3 for PIP application; see Fig.1  
PanZoomVec1-Y  
PanZoomVec2-X  
PanZoomVec2-Y  
StatusJump1  
F
read; F  
read  
S
X X X X X X X pan-zoom vector 1 (7-bit Y value)  
X X X X X X X X pan-zoom vector 2 (8-bit X value)  
0B4  
0B5  
1
logic 1  
PanZoomVec2-Y  
F
X X X X X X X pan-zoom vector 2 (7-bit Y value)  
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SNERT  
READ/  
NAME  
ADDRESS  
(HEX)  
7
6
5
4
3
2
1
0
DESCRIPTION(2)  
WRITE(1)  
PanZoomVec3-X  
PanZoomVec3-Y  
PanZoomVec4-X  
PanZoomVec4-Y  
PanZoomVec5-X  
PanZoomVec5-Y  
PanZoomVec6-X  
PanZoomVec6-Y  
PanZoomVec7-X  
PanZoomVec7-Y  
PanZoomVec8-X  
PanZoomVec8-Y  
EggSliceRgtMSB  
EggSliceRgtLSB  
EggSliceMixMSB  
EggSliceMixLSB  
SafeFbLine  
0B6  
0B7  
0B8  
0B9  
0BA  
0BB  
0BC  
0BD  
0BE  
0BF  
0AE  
0AF  
0C0  
0C1  
0C2  
0C3  
0C9  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
read; F  
X X X X X X X X pan-zoom vector 2 (8-bit X value)  
X X X X X X X pan-zoom vector 3 (7-bit Y value)  
X X X X X X X X pan-zoom vector 4 (8-bit X value)  
X X X X X X X pan-zoom vector 4 (7-bit Y value)  
X X X X X X X X pan-zoom vector 5 (8-bit X value)  
X X X X X X X pan-zoom vector 5 (7-bit Y value)  
X X X X X X X X pan-zoom vector 6 (8-bit X value)  
X X X X X X X pan-zoom vector 6 (7-bit Y value)  
X X X X X X X X pan-zoom vector 7 (8-bit X value)  
X X X X X X X pan-zoom vector 7 (7-bit Y value)  
X X X X X X X X pan-zoom vector 8 (8-bit X value)  
X X X X X X X pan-zoom vector 8 (7-bit Y value)  
X X X X X X X X result of right pixels egg-slice detector (15 to 8)  
X X X X X X X X result of right pixels egg-slice detector (7 to 0)  
X X X X X X X X result of mixed pixels egg-slice detector (15 to 8)  
X X X X X X X X result of mixed pixels egg-slice detector (7 to 0)  
X X X X X X X X reference line number (divided by two) at which the upconverter goes  
into protection mode  
EggBinGoodness  
0CA  
read; F  
X X X X X X X X Goodness of the four egg-slice sections, from top to bottom, 2 bits per  
section. Each section is represented with 2 bits in this register, where  
bits 0 and 1 represent the top section and bits 6 and 7 represent the  
lowest of the 4 sections. Each pair of bits indicate  
00 = (ESR > 3⁄4ESM), 01 = (1⁄2ESM < ESR ≤ 3⁄4ESM),  
10 = (1⁄4ESM < ESR ≤ 1⁄2ESM), 11 = (ESR ≤ 1⁄4ESM).  
LoActCnt  
HiActCnt  
0D3  
0D4  
0D5  
read; F  
read; F  
read; F  
X X X X X X X X number of blocks having low activity  
X X X X X X X X number of blocks having high activity  
NullErrSum  
X X X X X X X X sum of errors for the null candidate over the complete field; when no  
null candidate is selected a value of FFH will be read  
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
Notes  
1. S means semi static, used at initialization or mode changes; F means field frequent, in general updated in each  
display field.  
2. Selectable items are marked bold.  
3. Almost all of the R(ead) and W(rite) registers of SAA4998H are double buffered. The write registers are latched by  
a signal called New_field. New_field gets set, when REF rises after SNRST (New_field is effectively at the start of  
active video). The read registers are latched by a signal called Reg_upd. Reg_upd gets set, when half the number  
of active pixels of the fourth line of vertical blanking have entered the SAA4998H (Reg_upd will effectively be  
active 31⁄2 lines after the REA has ended). The only exception are the registers which are not double buffered, these  
are as follows:  
a) Write register 025H: power_on_reset  
b) Write register 02FH, bit 1: CndSet  
c) Read register 0B0H to 0BFH, 0AEH and 0AFH: pan_zoom_vectors, including FalconIdent (= 0), StatusJump0  
and StatusJump1.  
8
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
SYMBOL  
PARAMETER  
core supply voltage (internal rail)  
analog supply voltage  
CONDITIONS  
MIN.  
−0.5  
MAX.  
+2.5  
UNIT  
VDDD  
VDDA  
VDDM  
VDDS  
VDDE  
VDDP  
Vi  
V
field memory supply voltage  
SRAM supply voltage  
external supply voltage (output pads)  
high supply voltage of internal field memories  
input voltage of all I/O pins  
output current  
−0.5  
+4.6  
V
V
−0.5  
−
+6(1)  
4
Io  
mA  
°C  
°C  
V
Tstg  
Tj  
storage temperature  
−40  
0
+125  
125  
junction temperature  
Vesd  
electrostatic discharge voltage on all pins  
MM; note 2  
−400  
−3000  
+400  
+3000  
HBM; note 3  
V
Notes  
1. Only valid, if VDDE is present.  
2. In accordance with “Transient energy (ESD machine model); SNW-FQ-302B” class C, discharging a 200 pF  
capacitor via a 0.75 µH series inductance.  
3. In accordance with “Transient energy (ESD human body model); SNW-FQ-302A” class 2, discharging a 100 pF  
capacitor via a 1.5 kΩ series resistor.  
9
THERMAL CHARACTERISTICS  
SYMBOL PARAMETER  
CONDITIONS  
VALUE  
UNIT  
Rth(j-a)  
Rth(j-c)  
thermal resistance from junction to ambient  
thermal resistance from junction to case  
in free air  
45  
10  
K/W  
K/W  
2004 Feb 18  
29  
 
 
 
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
10 CHARACTERISTICS  
VDDE = 3.0 to 3.6 V; Tamb = 0 to 70 °C; unless otherwise specified.  
SYMBOL  
Supplies  
PARAMETER  
CONDITIONS  
MIN.  
TYP. MAX. UNIT  
VDDD  
VDDA  
VDDM  
VDDS  
VDDE  
VDDP  
core supply voltage (internal rail)  
analog supply voltage  
1.65  
1.8  
1.95  
V
field memory supply voltage  
SRAM supply voltage  
external supply voltage (output pads)  
3.0  
3.3  
3.6  
V
high supply voltage of internal field  
memories  
IDD  
sum of supply current  
at 1.8 V supply voltage pins  
at 3.3 V supply voltage pins  
−
−
180  
6
−
−
mA  
mA  
General  
VOH  
VOL  
HIGH-level output voltage  
LOW-level output voltage  
HIGH-level input voltage  
LOW-level input voltage  
HIGH-level output current  
V
−
2
−
DDE − 0.4  
−
−
−
−
−
−
V
0.4  
−
V
VIH  
V
VIL  
0.8  
−
V
IOH  
10 ns slew rate output; −4  
VOH = VDDE − 0.4 V  
mA  
IOL  
LOW-level output current  
10 ns slew rate output;  
VOL = 0.4 V  
−
−
4
mA  
Ci  
ILI  
input capacitance  
−
−
−
−
8
1
pF  
input leakage current  
note 1  
µA  
Outputs; see Fig.5; note 2  
IOZ  
output current in 3-state mode  
−0.5 < Vo < 3.6  
−
−
4
−
−
−
1
µA  
ns  
ns  
td(o)  
th(o)  
output delay time  
output hold time  
23  
−
Inputs  
tr  
rise time  
−
−
6
2
−
−
−
−
30  
30  
−
ns  
ns  
ns  
ns  
tf  
fall time  
tsu(i)  
th(i)  
input set-up time  
input hold time  
see Fig.5; note 3  
see Fig.5; note 3  
−
Input CLK32; see Fig.5  
tr  
rise time  
fall time  
−
−
−
−
−
4
ns  
ns  
%
tf  
−
4
δ
duty factor  
cycle time  
40  
30  
60  
39  
Tcy  
ns  
2004 Feb 18  
30  
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP. MAX. UNIT  
BST interface; see Fig.6  
Tcy(BST)  
tsu(i)(BST)  
th(i)(BST)  
th(o)(BST)  
td(o)(BST)  
BST cycle time  
input set-up time  
−
3
6
4
−
1
−
−
−
−
−
µs  
ns  
ns  
ns  
ns  
−
input hold time  
output hold time  
output delay  
−
−
30  
SNERT interface; see Fig.7  
tSNRST(H)  
SNRST pulse HIGH time  
500  
200  
−
−
−
−
ns  
ns  
td(SNRST-SNCL) delay SNRST pulse to SNCL LOW  
time  
Tcy(SNCL)  
tsu(i)(SNCL)  
th(i)(SNCL)  
th(o)  
SNCL cycle time  
0.5  
53  
10  
30  
−
−
−
−
−
−
−
1
µs  
ns  
ns  
ns  
ns  
ns  
input set-up time to SNCL  
input hold time to SNCL  
output hold time  
−
−
−
td(o)  
output delay  
330  
−
to(en)  
output enable time  
210  
Notes  
1. All inputs except inputs with internal pull-up or pull-down resistor. These inputs have an absolute leakage current of  
maximum 50 µA.  
2. Timing characteristics are measured with CL = 15 pF.  
3. All inputs except SNERT interface inputs, CLK32 input and BST/TEST inputs.  
stable power supply  
CLK32  
RST  
≥10 cycles of CLK32  
coc003  
Fig.4 Timing for RST input.  
2004 Feb 18  
31  
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
t
t
r
f
90%  
10%  
90%  
10%  
CLOCK  
1.5 V  
INPUT  
DATA  
MHB175  
t
t
su(i)  
h(i)  
OUTPUT  
DATA  
data  
valid  
data transition  
period  
t
h(o)  
t
d(o)  
Fig.5 Data input/output timing diagram.  
T
cy(BST)  
TCK  
TDI, TMS  
TDO  
MHB649  
t
t
su(i)(BST)  
h(o)(BST)  
h(i)(BST)  
t
t
d(o)(BST)  
Fig.6 Boundary scan test interface timing diagram.  
32  
2004 Feb 18  
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
SNCL  
write sequence:  
SNDA  
a0  
a0  
a1  
a1  
a2  
a2  
a3  
a3  
a4  
a4  
a5  
a5  
a6  
a6  
a7  
a7  
w0  
w1  
w2  
w3  
w4  
w5  
w6  
w7  
read sequence:  
SNDA  
driven by  
master  
r0  
r1  
r2  
r3  
r4  
r5  
r6  
r7  
SNDA  
driven by  
SAA4998H  
SNCL  
50 %  
50 %  
50 %  
t
t
h(i)(SNCL)  
su(i)(SNCL)  
a6  
write sequence:  
SNDA  
a7  
w0  
w1  
read sequence:  
SNDA  
driven by  
master  
a6  
a7  
t
t
h(o)  
o(en)  
90 %  
SNDA  
driven by  
SAA4998H  
r0  
r1  
10 %  
t
t
d(o)  
d(o)  
coc004  
Fig.7 SNERT interface timing diagram.  
2004 Feb 18  
33  
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
Table 1 YUV formats  
FORMAT(2)(3)  
I/O PIN(1)  
4 : 1 : 1  
4 : 2 : 2  
4 : 2 : 2 DPCM  
Yx7  
Yx6  
Y07  
Y06  
Y05  
Y04  
Y03  
Y02  
Y01  
Y00  
U07  
U06  
V07  
V06  
X
Y17  
Y16  
Y15  
Y14  
Y13  
Y12  
Y11  
Y10  
U05  
U04  
V05  
V04  
X
Y27  
Y26  
Y25  
Y24  
Y23  
Y22  
Y21  
Y20  
U03  
U02  
V03  
V02  
X
Y37  
Y36  
Y35  
Y34  
Y33  
Y32  
Y31  
Y30  
U01  
U00  
V01  
V00  
X
Y07  
Y06  
Y05  
Y04  
Y03  
Y02  
Y01  
Y00  
U07  
U06  
U05  
U04  
U03  
U02  
U01  
U00  
Y17  
Y16  
Y15  
Y14  
Y13  
Y12  
Y11  
Y10  
V07  
V06  
V05  
V04  
V03  
V02  
V01  
V00  
Y07  
Y06  
Y05  
Y04  
Y03  
Y02  
Y01  
Y00  
UC03  
UC02  
UC01  
UC00  
X
Y17  
Y16  
Y15  
Y14  
Y13  
Y12  
Y11  
Y10  
VC03  
VC02  
VC01  
VC00  
X
Yx5  
Yx4  
Yx3  
Yx2  
Yx1  
Yx0  
UVx7  
UVx6  
UVx5  
UVx4  
UVx3  
UVx2  
UVx1  
UVx0  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Notes  
1. Digit x refers to different I/O buses:  
a) A = input from 1st field memory  
b) F = main output  
c) G = 2nd output for matrix purposes.  
2. The first index digit defines the sample number and the second defines the bit number.  
3. X = don’t care or not available.  
2004 Feb 18  
34  
 
 
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
11 PACKAGE OUTLINE  
QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm  
SOT317-2  
y
X
A
80  
51  
81  
50  
Z
E
e
A
2
H
A
E
E
(A )  
3
A
1
θ
w
p
M
pin 1 index  
L
p
b
L
31  
100  
detail X  
1
30  
w
M
Z
v
v
M
D
A
b
p
e
D
B
H
M
B
D
0
5
scale  
10 mm  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.  
7o  
0o  
0.25 2.90  
0.05 2.65  
0.40 0.25 20.1 14.1  
0.25 0.14 19.9 13.9  
24.2 18.2  
23.6 17.6  
1.0  
0.6  
0.8  
0.4  
1.0  
0.6  
mm  
3.2  
0.25  
0.65  
1.95  
0.2 0.15 0.1  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-25  
SOT317-2  
MO-112  
2004 Feb 18  
35  
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
12 SOLDERING  
To overcome these problems the double-wave soldering  
method was specifically developed.  
12.1 Introduction to soldering surface mount  
packages  
If wave soldering is used the following conditions must be  
observed for optimal results:  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “Data Handbook IC26; Integrated Circuit Packages”  
(document order number 9398 652 90011).  
• Use a double-wave soldering method comprising a  
turbulent wave with high upward pressure followed by a  
smooth laminar wave.  
• For packages with leads on two sides and a pitch (e):  
There is no soldering method that is ideal for all surface  
mount IC packages. Wave soldering can still be used for  
certain surface mount ICs, but it is not suitable for fine pitch  
SMDs. In these situations reflow soldering is  
recommended.  
– larger than or equal to 1.27 mm, the footprint  
longitudinal axis is preferred to be parallel to the  
transport direction of the printed-circuit board;  
– smaller than 1.27 mm, the footprint longitudinal axis  
must be parallel to the transport direction of the  
printed-circuit board.  
12.2 Reflow soldering  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
Driven by legislation and environmental forces the  
The footprint must incorporate solder thieves at the  
downstream end.  
• For packages with leads on four sides, the footprint must  
be placed at a 45° angle to the transport direction of the  
printed-circuit board. The footprint must incorporate  
solder thieves downstream and at the side corners.  
worldwide use of lead-free solder pastes is increasing.  
Several methods exist for reflowing; for example,  
convection or convection/infrared heating in a conveyor  
type oven. Throughput times (preheating, soldering and  
cooling) vary between 100 and 200 seconds depending  
on heating method.  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
Typical reflow peak temperatures range from  
215 to 270 °C depending on solder paste material. The  
top-surface temperature of the packages should  
preferably be kept:  
Typical dwell time of the leads in the wave ranges from  
3 to 4 seconds at 250 °C or 265 °C, depending on solder  
material applied, SnPb or Pb-free respectively.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
• below 225 °C (SnPb process) or below 245 °C (Pb-free  
process)  
– for all BGA, HTSSON-T and SSOP-T packages  
12.4 Manual soldering  
– for packages with a thickness ≥ 2.5 mm  
Fix the component by first soldering two  
diagonally-opposite end leads. Use a low voltage (24 V or  
less) soldering iron applied to the flat part of the lead.  
Contact time must be limited to 10 seconds at up to  
300 °C.  
– for packages with a thickness < 2.5 mm and a  
volume ≥ 350 mm3 so called thick/large packages.  
• below 240 °C (SnPb process) or below 260 °C (Pb-free  
process) for packages with a thickness < 2.5 mm and a  
volume < 350 mm3 so called small/thin packages.  
When using a dedicated tool, all other leads can be  
soldered in one operation within 2 to 5 seconds between  
270 and 320 °C.  
Moisture sensitivity precautions, as indicated on packing,  
must be respected at all times.  
12.3 Wave soldering  
Conventional single wave soldering is not recommended  
for surface mount devices (SMDs) or printed-circuit boards  
with a high component density, as solder bridging and  
non-wetting can present major problems.  
2004 Feb 18  
36  
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
12.5 Suitability of surface mount IC packages for wave and reflow soldering methods  
SOLDERING METHOD  
PACKAGE(1)  
WAVE  
not suitable  
REFLOW(2)  
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,  
USON, VFBGA  
suitable  
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,  
HTQFP, HTSSOP, HVQFN, HVSON, SMS  
PLCC(5), SO, SOJ  
not suitable(4)  
suitable  
suitable  
suitable  
LQFP, QFP, TQFP  
not recommended(5)(6) suitable  
SSOP, TSSOP, VSO, VSSOP  
CWQCCN..L(8), PMFP(9), WQCCN..L(8)  
not recommended(7)  
suitable  
not suitable  
not suitable  
Notes  
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy  
from your Philips Semiconductors sales office.  
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum  
temperature (with respect to time) and body size of the package, there is a risk that internal or external package  
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the  
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.  
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account  
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature  
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature  
must be kept as low as possible.  
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder  
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,  
the solder might be deposited on the heatsink surface.  
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.  
The package footprint must incorporate solder thieves downstream and at the side corners.  
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not  
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than  
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.  
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted  
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar  
soldering process. The appropriate soldering profile can be provided on request.  
9. Hot bar or manual soldering is suitable for PMFP packages.  
12.6 Additional soldering information  
The package QFP100 (lead-free; SOT317GC11, subpackage of the SOT317-2) is granted the Moisture Sensitivity  
Level (MSL) 3.  
Soldering temperature of > 215 °C is recommended or RMA flux.  
2004 Feb 18  
37  
 
 
 
 
 
 
 
 
Philips Semiconductors  
Product specification  
Field and line rate converter with noise  
reduction and embedded memory  
SAA4998H  
13 DATA SHEET STATUS  
DATA SHEET  
STATUS(1)  
PRODUCT  
STATUS(2)(3)  
LEVEL  
DEFINITION  
I
Objective data  
Development This data sheet contains data from the objective specification for product  
development. Philips Semiconductors reserves the right to change the  
specification in any manner without notice.  
II  
Preliminary data Qualification  
This data sheet contains data from the preliminary specification.  
Supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to change the specification without  
notice, in order to improve the design and supply the best possible  
product.  
III  
Product data  
Production  
This data sheet contains data from the product specification. Philips  
Semiconductors reserves the right to make changes at any time in order  
to improve the design, manufacturing and supply. Relevant changes will  
be communicated via a Customer Product/Process Change Notification  
(CPCN).  
Notes  
1. Please consult the most recently issued data sheet before initiating or completing a design.  
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was  
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.  
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.  
14 DEFINITIONS  
15 DISCLAIMERS  
Short-form specification  
The data in a short-form  
Life support applications  
These products are not  
specification is extracted from a full data sheet with the  
same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
designed for use in life support appliances, devices, or  
systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips  
Semiconductors customers using or selling these products  
for use in such applications do so at their own risk and  
agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in  
accordance with the Absolute Maximum Rating System  
(IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device.  
These are stress ratings only and operation of the device  
at these or at any other conditions above those given in the  
Characteristics sections of the specification is not implied.  
Exposure to limiting values for extended periods may  
affect device reliability.  
Right to make changes  
Philips Semiconductors  
reserves the right to make changes in the products -  
including circuits, standard cells, and/or software -  
described or contained herein in order to improve design  
and/or performance. When the product is in full production  
(status ‘Production’), relevant changes will be  
Application information  
Applications that are  
communicated via a Customer Product/Process Change  
Notification (CPCN). Philips Semiconductors assumes no  
responsibility or liability for the use of any of these  
products, conveys no licence or title under any patent,  
copyright, or mask work right to these products, and  
makes no representations or warranties that these  
products are free from patent, copyright, or mask work  
right infringement, unless otherwise specified.  
described herein for any of these products are for  
illustrative purposes only. Philips Semiconductors make  
no representation or warranty that such applications will be  
suitable for the specified use without further testing or  
modification.  
2004 Feb 18  
38  
 
 
Philips Semiconductors – a worldwide company  
Contact information  
For additional information please visit http://www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.  
© Koninklijke Philips Electronics N.V. 2004  
SCA76  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
R24/01/pp39  
Date of release: 2004 Feb 18  
Document order number: 9397 750 12217  

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